Chapter 4 Sub-0.2mW Ultra-low Power LNA Design using Forward Body
4.3 LNA Circuit Analysis
4.4.2 ULP LNA Simulation Results
The whole circuit schematics for the proposed ULP LNA is illustrated in Fig. 4.5, in which three major blocks such as input matching network, cascade amplifying stage, and output matching network are included and the layout dimensions for active transistors and parasitic elements (R, L, C) are remarked for simulation. Note that all the components in this design, including spiral inductors and metal-insulator-metal (MIM) capacitors, are realized on a single chip. Fig. 4.6 depicts the chip layout of the proposed ULP LNA. The chip area including all of probing pads is 0.778×0.669 mm2. This proposed ULP LNA is simulated with Agilent ADS simulator using UMC 90nm RFCMOS Spice Model. In the following, the simulation results will be presented, including pre-layout and post-layout under typical (TT) and corner conditions (FF, SS). For this ULP LNA design, the key performance parameters, such as power gain (S21), input return loss (S11), output return loss (S22), reverse isolation (S12), noise figure (NF), stability (μ), and third-order intercept point (IIP3) have been calculated by ADS simulation. Fig. 4.7 show the pre-layout simulation results, under the typical condition
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of VDD=0.18V, VG=0.45V, VG2=0.8V, and frequencies in 0.8~2 GHz. Note that the third-order intercept point (IIP3) shown in Fig. 4.7(d) is determined by two-tone test with tone space of 10MHz, and fundamental frequency at 1.4GHz. Fig. 4.8 presents a comparison for all of the performance parameters, between pre-layout and post-layout simulation.
Table 4.1 and Table 4.2 summarizes the pre-layout and post-layout simulation for all of the performance parameters, with a comparison between typical (TT) and corner conditions (FF, SS). For mentioned simulation, the bias conditions are fixed at VDD=0.18V, VG=0.45V, VG2=0.8V, VB1=0.4V,.and VB2=0V. Note that VB1=0.4V is the forward body bias (FBB) applied to amplifier transistor M1, which enables VG scaling to 0.45V, approaching subthreshold region for ultra-low power operation. The results indicate that RF CMOS devices in 90 nm process, operating under the specified biases with FBB can achieve ultra-low power consumption to 0.19 mW for typical condition, and low NF of 2.1 dB. The performance looks very promising in both power and noise. As for the fast corner conditions (FF), the power dissipation is increased to 0.56 mW but NF can be improved to 1.8 dB. On the other hand, for slow corner condition (SS), the power consumption is pushed to extremely low to 0.05mW, but paying the penalty of significantly higher NF, up to 4.2 dB. The post-layout simulation indicates similar results with very minor difference from that of pre-layout simulation. The variations of the RF performance parameters between typical (TT) and corner models (FF, SS), under fixed biases condition can be eliminated by using tunable biases adapted to corner models. The principle of biases tuning is lowering VG and VG2 for fast corner (FF) while raising those for slow corner (SS). Tables 4.3 and table 4.4 present the pre-layout and post-layout simulation results, under tunable biases exactly adapted to FF and SS. In this way, the RF performance, particularly the power dissipation and NF of major concern, can be tuned to be similar for all three conditions (TT, FF, SS). The ultra-low power to sub-0.2 mW can be realized for TT and corner models.
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Fig. 4. 5 Circuit schematic of the ULP LNA with three core circuit blocks in which the active and passive devices dimensions are provided
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Fig. 4. 6 Chip layout of the designed ULP LNA
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Fig. 4. 7 Pre-layout simulation for ULP LNA (a) power gain (S21), input return loss (S11), output return loss (S22), reverse isolation (S22) (b) noise figure (NF) (c) stability (d) third-order intercept point (IIP3), two tones space=10MHz, center frequency
=1.4GHz. VDD=0.18V, VG=0.45V, VG2=0.8V, VB1=0.4V, VB2=0.
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89
90
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Fig. 4. 8 Comparison between pre-layout and post-layout simulation results for the ULP LAN (a) power gain(S21) (b) input return loss (S11) (c)output return loss (S22) (d) reverse isolation (S21) (e) noise figure (NF) (f) stability (g) third-order intercept point (IIP3). VDD=0.18V, VG=0.45V, VG2=0.8V, VB1=0.4V, VB2=0.
Table 4. 1 Pre-layout simulation for ULP LNA under fixed biases condition for typical (TT) and corner cases (FF, SS). VDD=0.18V, VG=0.45V, VG2=0.8V. VB1=0.4V, and
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Table 4. 2 Post-layout simulation for ULP LNA under fixed biases condition for typical (TT) and corner cases (FF, SS). VDD=0.18V, VG=0.45V, VG2=0.8V. VB1=0.4V, and VB2=0V.
RF CORNER UNIT TT FF SS
Process technology nm 90 90 90
Frequency GHz 1.4 1.4 1.4
VDD V 0.18 0.18 0.18 VG V 0.45 0.45 0.45 VG2 V 0.80 0.80 0.80 VB1 V 0.40 0.40 0.40 VB2 V 0 0 0
Power dissipation mW 0.19 0.54 0.05
Bias current mA 1.05 2.98 0.26
Gain (S21) dB 10.3 11.3 1.1
NF dB 2.3 1.9 4.3
IIP3 dBm -13.3 -17.5 -16.0
Pin,-1dB dBm -28.0 -30.0 -28.0
Input Return Loss (S11) dB -12.1 -14.9 -4.2
Output Return Loss (S22) dB -10.6 -5.6 -18.1
Reverse isolation (S12) dB -15.6 -18.5 -15.7
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Table 4. 3 Pre-layout simulation for ULP LNA under tunable biases condition for typical (TT) and corner cases (FF, SS).
RF CORNER UNIT TT FF SS
Process technology nm 90 90 90
Frequency GHz 1.4 1.4 1.4
VDD V 0.18 0.18 0.18
VG V 0.45 0.38 0.52
VG2 V 0.80 0.74 0.85
VB1 V 0.40 0.40 0.40 VB2 V 0 0 0
Power dissipation mW 0.19 0.20 0.19
Bias current mA 1.06 1.09 1.03
Gain (S21) dB 11.0 10.9 11.0
NF dB 2.1 2.1 2.1
IIP3 dBm -14.1 -14.2 -14.3
Pin,-1dB dBm -29.0 -29.0 -29.0
Input Return Loss (S11) dB -10.4 -9.3 -11.0
Output Return Loss (S22) dB -10.5 -10.8 -11.2
Reverse isolation (S12) dB -15.2 -14.3 -16.1
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Table 4. 4 Post-layout simulation for ULP LNA under tunable biases condition for typical (TT) and corner cases (FF, SS).
RF CORNER UNIT TT FF SS
Power dissipation mW 0.19 0.19 0.18
Bias current mA 1.05 1.07 1.01
For this ULP LNA design, the test chip characterization will be performed through on-wafer measurement. To meet this purpose, the probing pads layout must follow the rule issued by NDL RF Lab. to match the RF probe station configuration. This LNA chip needs two 3-pin DC PGP probes and two RF GSG probes for on-wafer measurement. The measurement setup is shown in Fig. 4.9, where two DC PGP probes are located at the top and bottom, and two RF GSG probes are place at two sides, in parallel to each other. Note that the DC PGP probe is used to provide the DC supply voltages to the drain and biasing voltage to the gate.
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Fig. 4. 9 On-wafer measurement of LNA test diagram
The measurement equipments to support this LNA chip test include a network analyzer (Agilent PNA-X N5242A), a spectrum analyzer (Agilent E4448A) with options for NF measurement, and dc power supply (Agilent 6623A & Keithley Model 236 Source-Measure Unit). The measurement setups are shown in Fig.4.10(a) for S-parameter, IIP3, and 1-dB compression point (P1dB), and Fig.4.10(b) for noise figure. In the following, we will present the ULP LNA chip characterization results for the key performance parameters and a comparison with what predicted by post-layout simulation.
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Agilent PNA-X N5242A Agilent E4448A
Agilent 6623A Keithley Model 236 Source-Measure Unit
(a) (b)
Fig. 4. 10 Measurement setups for (a) S-parameter & IIP3 & P1dB (b) noise figure
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4.5.2 Measurement Results and Discussion
Fig. 4.11 presents the performance measured from this ULP LNA fabricated in 90nm 1.2V RF CMOS process. The results are demonstrated for power gain (S21), input return loss (S11), output return loss (S22), reverse isolation (S12), and noise figure (NF), shown in Fig.
4.11(a)~(c). As compared to post-layout simulation shown previously, the measured performance reveals a distinct difference from the prediction by simulation under ultra-low VDD (0.18V) and VG=0.45V to subthreshold region. The first problem is that the power gain (S21) measured from the real chips under the specified biases is abnormally low. It was considered that the on-chip inductors performance may deviate from the ideal values predicted by simulation, assuming thick top metal (3.25μm). Thus, on-wafer S-parameters measurement was carried to explore the root causes responsible for this unexpected degradation. Table 4.5 makes a comparison between the measured and simulated characteristics and reveals a close match in inductance but distinct deviation in series resistance RS=Re(1/Y11). The measured RS is around 3~5 times larger than the simulated values for larger inductors with L=10~22 nH. The deviation becomes even worse to more than one order for the smallest inductor with L=0.8~0.9 nH. Through this analysis, it is identified that extra-ordinarily high RS due to thin metal for the spiral conductors is the major reason responsible for inductor performance degradation like extremely low Q. To verify if the abnormal inductor performance drift is the primary reason responsible for the LNA performance degradation, the measured inductor S-parameters were imported to replace the original model for LNA simulation using ADS. The comparison as shown in Fig. 4.12 indicates a close match between the measurement and simulation using measured inductor parameters. The results match the theorectal analysis and suggest that that the power gain (S21) measured from the real chips is abnormally low, due to poor inductors performance and the resulted severe deviation in input and output matching. The origin comes from the fact that
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UMC 90nm Logic & Mixed-Mode 1P9M Low-K Process doesn’t support the thick metal module for on-chip inductors. The thick metal required for on-chip spiral inductors is 3.25um but the thin metal supported by UMC 90nm standard logic process is 0.8um. The inappropriately thin metal is just the root cause responsible for the substantial increase of series resistance RS and then Q degradation. A potential solution for improvement is increasing biases to modify input matching and to raise power gain. Fig. 4.13 demonstrates the LNA performance measured by increasing VDD and VG. When increasing VDD to 0.5V and VG to 0.55V, the problem of performance degradation can be solved and promisingly good results can be realized. The power gain (S21) can reach 5.5 dB at 1.4GHz but power consumption increases to 1.75mW from 0.5V. S11 is –12.1dB, S22 is –14.8dB, and S12 is as low as –23.5 dB. Table 4.6 summarizes the measured LNA performance, under various biases.
The results indicate that increasing VDD and VG can effectively improve power gain but paying the penalty of higher power dissipation. Finally, an extensive performance benchmark with the state-of-the-art techniques in latest publications [45, 47-50] has been done and summarized in Table 4.7. This benchmark indicates that our designed ULP LNA from simulation with thick metal inductors, demonstrates the advantages of lower power and lower NF under comparable gain. However, lacking thick metal inductors in current 90 nm process makes input and output matching difficult and leads to dramatic degradation of power gain.
Increasing VDD and VG is can partially recover power gain but pay the penalty of increasing power consumption.
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0.8 1.0 1.2 1.4 1.6 1.8 2.0 -30
-25 -20 -15 -10 -5 0
Frequency (GHz)
S21_m S12_m
S2 1 , S 1 2 (d B)
(a)
0.8 1.0 1.2 1.4 1.6 1.8 2.0 -20
-15 -10 -5 0
Frequency (GHz)
S11_m S22_m
S1 1, S 2 2 (dB )
(b)
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0.8 1.0 1.2 1.4 1.6 1.8 2.0 4
6 8 10 12 14 16
Frequency (GHz)
NF_m
NF ( d B )
(c)
Fig. 4. 11 ULP LNA chip measured results for (a) power gain (S21) and reverse isolation (S12) (b) input return loss (S11) and output return loss (S22) (c) noise figure. VDD=0.18V, VG=0.45V, VG2=0.8V, VB1=0.4V, and VB2=0.
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Table 4. 5 Spiral inductor characteristics measured from the test devices on a single chip with ULP LNA
Lg od=250um , w=2.2u , s=2.3um , nt=7.5 Metal
thickness
L @1.4G Q @1.4G Qpeak Rs=Re(1/Y11)@1.4G Simulation 3.25um 22.6 nH 9.3 9.3 21.5
Measured 0.8um 20.8 nH 1.8 2.4 100.7 Ld od=250um , w=3u , s=2.5um , nt=7.5 Metal
thickness
L @1.4G Q @1.4G Qpeak Rs=Re(1/Y11)@1.4G Simulation 3.25um 20 nH 10.4 10.4 17
Measured 0.8um 18.6 nH 2.7 3.5 60.4 Lo od=250um , w=8u , s=2.5um , nt=7.5 Metal
thickness
L @1.4G Q @1.4G Qpeak Rs=Re(1/Y11)@1.4G Simulation 3.25um 10.5 nH 11.2 11.5 8.3
Measured 0.8um 10.2 nH 4.4 5.5 20.2 Ls od=75um , w=3.5u , s=2.3um , nt=3.5 Metal
thickness
L @1.4G Q @1.4G Qpeak Rs=Re(1/Y11)@1.4G Simulation 3.25um 0.8 nH 4.6 20.5 1.5
Measured 0.8um 0.9 nH 0.3 6.3 24.3
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0.8 1.0 1.2 1.4 1.6 1.8 2.0 -30
-25 -20 -15 -10 -5 0
Frequency (GHz)
S21_s S21_m S12_s S12_m
S2 1 , S 1 2 (d B)
(a)
0.8 1.0 1.2 1.4 1.6 1.8 2.0 -20
-15 -10 -5 0
Frequency (GHz)
S11_s S11_m S22_s S22_m
S1 1 , S2 2 ( d B)
(b)
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Fig. 4. 12 The comparison between measurement and ADS simulation by using measured inductor S-parameters, rather than inductor model (a) power gain (S21) and reverse isolation (S21) (b) input return loss (S11), output return loss (S22), (c) noise figure
104 isolation (S12), input return loss (S11) and output return loss (S22) (b) noise figure.
VDD=0.5V, VG=0.55V, VG2=0.8V.
Table 4. 6 Simulated and measured performance for 1.4GHz LNA under varying VDD and VG
Sim Mea Mea Mea
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Table 4. 7 ULP LNA Performance Benchmark
This LNA Published LNAs
Publication Ref. [45] [45] [47] [48] [49] [50]
Process technology um 0.09 0.09 0.13 0.13 0.13 0.13 0.18 0.09 Power dissipation mW 1.75 0.19 0.16 0.4 1.03 0.64 0.9 1 Supply Volatge (VDD) V 0.50 0.18 0.6 0.6 0.4 0.4 0.6 0.6
Bias current mA 3.50 1.05 0.26 0.67 2.58 1.6 1.5 1.67
Frequency GHz 1.4 1.4 3 3 5.1 5 5 5.5
Gain (S21) dB 5.5 10.3 4.5 9.1 10.3 14.3 9.2 9.2
NF dB 4.1 2.3 6.3 4.7 5.3 2.93 4.5 3.6
IIP3 dBm -8.0 -13.3 -10.5 -11 - -16 -15 -7.25
Pin,-1dB dBm -17.0 -28.0 -19.5 -25 -22 -26.7 -27 -15.8
Input Return Loss (S11) dB -12.1 -12.1 -17.7 -17.7 -17.7 -20 -12 -10 Output Return Loss (S22) dB -14.8 -10.6 -11.4 -11.4 -11.4 -31 -20.9 -14
measure/simulate m s m m m s m m
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Chapter 5
Conclusion and Future Work
5.1 Conclusion
This thesis includes two topics. One is UWB low-power LNA, and the other is sub-0.2mW ultra-low power (ULP) LNA. The first topic have demonstrated a low-power approach for the design of UWB LNA in the 3.1~10.6GHz band. The design employs a three-section reactive input network to realize the UWB matching and FBB scheme in the cascade amplifying stage for achieving low supply voltage to VDD=0.9V and gate bias to subthreshold region of VG=0.4V. The effectiveness of our approach has been proven by experiments carried out on LNA test chip fabricated in 0.13um RF CMOS technology. The power consumption can be reduced to 8.4 mW for a whole chip operating over ultra-wide band of frequencies in 3.1~ 10.6 GHz.
The second topic presents an ultra-low power (ULP) LNA), which was fabricated using 90nm low leakage (LL) CMOS process and applied with forward body biases (FBB). The adoption of FBB scheme in the transconductance stage MOSFET enables ultra-low supply voltage to VDD=0.18V and gate bias to subthreshold region, that is VG=0.45V. The aggressive voltages scaling driven by FBB can effectively push the chip power consumption to extremely low, such as sub-0.2 mW. Unfortunately, the power gain (S21) measured from the real chips under 0.18V is abnormally low, due to poor inductors performance and the resulted severe deviation in input and output matching. In Chapter 4, we have demonstrated that the abnormally large series resistance RS appearing in the on-chip inductors lacking thick metal is the primary factor responsible the performance degradation in this LNA. The origin comes from the fact that UMC 90nm logic and mixed-Mode process doesn’t support the thick top metal module for on-chip inductors. The standard top metal offered by UMC 90nm logic
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process is 0.8um, which is much thinner than that required for on-chip spiral inductors, that is 3.25um. The inappropriately thin metal is just the root cause responsible for the substantial increase of RS and then Q degradation. Thus, if we want to meet the target performance, we are forced to increase the supply voltage and then the power consumption. In this study, we learn that on-chip inductors with sufficient Q play a key role in input and output matching, and determined the LNA performance in terms of gain, power, and noise. In future work, new matching methods without resort to area consuming and cost added spiral inductors become one of interesting topics. Active inductors may be an appropriate candidate for achieving the desired performance with small chip area and without need for RF specific back-end process.
In summary, the fabricated UWB and ULP LNAs proven on Si chip may become candidates for 3.1~10.6GHz wireless system applications and wireless sensor networks, respectively.
5.2 Future Work
The achievements realized in this thesis, such as low-power UWB and ULP single-chip LNA justify the proposed circuit topologies and low power RF circuit design methods. More importantly, several challenging issues arising from in this thesis become interesting topics worthy of continuous research effort in the future work.
In the following, the research topics of most critical importance are remarked for future effort. The first topic is regarding a broadband matching method with the bandwidth extended beyond the conventional UWB (3.1~10.6 GHz) to millimeter (mm) wave regime. The second topic is with a special focus on broadband matching methods for simultaneous optimization of power gain and noise. The third challenging topic is developing noise shielding methods for mm-wave chip, targeting ultra-low power and low noise. The fourth topic of interest is novel matching circuits without need of inductors for chip area saving and cost reduction, due to full compatibility with standard logic process. The final one is the extended applications of FBB
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technique in RF front-end circuits like mixers and VCOs for realizing an ULP single-chip RF front-end.
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