Comparison of the Demonstrated 2.4-GHz Direct-Conversion Receivers 157

DCRs using passive mixer (in Section 6.3) and V-NPN BJT Gilbert mixer with inductive peaking technique (in Section 6.4.1) and a V-NPN BJT sub-harmonic Gilbert mixer (in Section 6.4.2).

Similar conversion gain of around 50 dB, NF of around 3dB, and flicker noise corner of below 100 kHz are achieved by the three implementations at similar dc power dissipation of below 9 mW. The fundamental V-NPN BJT Gilbert mixer with inductive peaking technique requires only −3 dBm LO power even though the fLO>fT. Besides, the passive mixer with off-overlap biasing has lower flicker noise contribution at the cost of higher LO power. However, the design of the input impedance of the TIA can improve the conversion gain and also the flicker noise

performance. On the other hand, even though the LO power of the BJT SHM requires 8 dBm, which is the same as that of the passive mixer.

The passive mixer has lower toleration of LO amplitude imbalance. Thus, any amplitude/phase imbalance degrades the isolation property, output I/Q accuracy and also the dc offset due to LO self-mixing. Thus, the passive mixer has relative higher dc offset due to self-mixing (if no additional offset cancellation circuit is applied). The DCR with SHMs has the lowest noise figure and the flicker noise corner of the three implementations at the cost of a large LO power and a narrower I/Q tolerable RF bandwidth.

TABLE. 6.4 PERFORMANCE COMPARISON OF DEMONSTRATED 2.4-GHZ DCRS

Topology Fundamental Passive Mixer

Technology 0.18μm CMOS 0.18μm CMOS 0.18μm CMOS

6.5 S

UB

-H

ARMONIC

R

ECEIVER

W

ITH

T

UNABLE

-B

AND

RF LNA

AND

W

IDEBAND

LO G

ENERATOR AT

U-NII B

ANDS

In this section, a low-power tunable-band SH-DCR is demonstrated using 0.18-μm CMOS technology. Our application is focused on the U-NII radio band, consisting of three frequency bands of 100 MHz each in the 5 GHz band: 5.15-5.25 GHz (for indoor use only), 5.25-5.35 GHz and 5.725-5.825 GHz. Although the LNA has a low transconductance gain (gm) due to its low dc current, its high load resistance (high quality factor Q) provides sufficient voltage gain for a better NF of the whole receiver at the cost of the RF bandwidth. In addition, a narrower RF bandwidth results in little received noise and interference from other channels or other communication systems. Thus, a tunable/switchable narrow-band LNA has better gain/noise performance than an LNA with a wideband design at a given power consumption. As a result, a two-stage LNA with tunable loads, including the first-stage LC tank and the second-stage transformer load, is employed.

A DCR is still chosen in this work. The dc offset, 1/f noise and IIP2 problems are the primary issues for such systems instead of the image and spurious problems of non-zero-IF architectures. An SHM is chosen for a low output dc offset due to LO self-mixing because of the additional LO rejection [41]. In addition, MOS switching cores are directly replaced by V-NPN BJTs, available in a standard 0.18-μm CMOS process and have the 1/f noise corner of below 1 kHz [49]-[50]. Further, an LC filter is applied at the common emitter node to greatly improve the IIP2 performance [108].

Moreover, to overcome the low fT of V-NPN BJTs, using both resonance inductors (at mixer LO port and the LC filter) and sub-harmonic mixing structure, the proposed SHM successfully operates at over three times the transistor fT. On the other hand, a wideband LO octet-phase signal generator is chosen to avoid tuning both RF and LO

bands simultaneously in practical use.

Fig. 6-50 Block diagram of the I/Q SH-DCR with a tunable narrow-band LNA and a wideband LO generator using 0.18-μm CMOS technology.

Since the RF LNA is a tunable-band structure while the mixer and the LO generator are wideband topologies, a tunable narrow-band SH-DCR is proposed to cover whole U-NII bands when the 1-dB RF bandwidth is around 200 MHz. Fig. 6-50 shows the block diagram of the proposed SH-DCR, including a two-stage tunable-band LNA, I/Q SHMs with V-NPN BJT switching core, I/Q VGAs and a wideband LO octet-phase generator.

1) Tunable Band LNA

The impedance of a parallel LC tank with lossy inductor (sL+Rs) is

( ) 2

1

s s

R sL Z s sCR s LC

 

  . (6.34)

Typically, the series resistance Rs can be assumed as

R

 (

Q L

)   , where α

L

is close to a constant, only relating to the geometrical shape (including width, spacing and thickness).

Thus,

2 2

max 1 ( 0) (1 ) _{s p}

Z      L Q R R , (6.35)

when(  ²₀ ²)

LC

 as proved in Appendix E. That is why an LC tank with a lossy 1 inductor is widely approximated as an RLC parallel tank, as shown in Fig. 6-51.

Fig. 6-51 Schematic of an LC tank with a lossy inductor.

Further, in Appendix E, a more general case, n stages of RLC tanks in cascade with the same Q, is considered for bandwidth. Thus, an m-dB bandwidth can be calculated as kω0/Q, where k= 10^m10n  , which is defined in Appendix E. If the 1 target bandwidth boundaries are ωL and ωH, the required Q can be obtained by

0 H L

H L

Q k k  

 

    , (6.36)

where the center frequency is ^{ }_{H L} , as also shown in Appendix E.

By Eqn. (6.36), to achieve a 3-dB bandwidth covering the whole U-NII band (5.15-5.825 GHz), the Q should be lower than 8.11. More strictly, if the gain flatness is required to be within 1 dB covering the whole band, the Q should be reduced to below 4.13. On the other hand, if multiple tanks are in cascade and located at the same frequency, the greater number of stages in cascade results in a smaller k and thus a narrower bandwidth as also described in Fig. 6-52(a). Either a Q value reduction or a separation of resonance frequencies can fulfill the original bandwidth requirement as illustrated in Fig. 6-52(b) and Fig. 6-52(c), respectively. However, the gain

degrades when using either method.

Fig. 6-52 (a)Frequency response of the single/two stage(s) of LC resonator(s) (b) Q reduction for each tank (c) wideband response with separation of tanks (d) tunable narrow-band response.

For the requirements of low power, high gain, low noise and RF bandwidth of 5.15-5.825 GHz in this work, a two-stage cascode LNA with a tunable RF band is chosen. A two-stage LNA is required for a sufficient gain to suppress the NF of the following SHMs at a low dc current consumption. The center frequencies of the two stages are set the same and vary together as described in Fig. 6-52(d). Thus, a higher gain is obtained when compared with the wideband solutions, especially in a low-power condition. Since the IF bandwidth is much lower than the RF bandwidth, the frequency response of the narrow RF tank is still nearly constant within the IF bandwidth (<50 MHz).

Fig. 6-53 Two-stage LNA with a tunable first-stage LC tank and a tunable second-stage transformer

The schematic of a two-stage cascode LNA is shown in Fig. 6-53. An LC tank is used at the load of the first stage and a transformer at the second stage. A series inductor Lg is sufficient for an input matching covering 5-6 GHz. Further, a gain tuning transistor (MT) is in parallel with the cascode transistor in the second stage to reduce the gain when a large RF signal is applied.

The frequency tuning capability of both an LC tank and a transformer load with a varactor are fully discussed as follows.

Assume the higher/lower RF bandwidth boundaries (ωH/ωL) are 5.825/5.15 GHz, respectively. Thus, the first-stage LC tank follows

2 9 2 including device and substrate capacitances, and CV(V) is a capacitance of a varactor

ranging from CV,min to CV,max. Typically, in CMOS process, a MOS varactor CV(V) operating in an accumulation mode has a tuning ratio (CV,max/CV,min) of around 2.5.

Moreover, if the varactor capacitance ratio Cr is defined as CV,min/Cconst,

max ,max

can be changed by modifying the size of the cascode transistor, the following common-source transistor, and the dc blocking capacitance. Thus, in this work, Cconst

is tuned to 0.4 pF and Cr=0.3 and Cmax/Cmin are around 0.7/0.52 pF, respectively. Thus, the calculated Ld is around 1.44 nH. Finally, the used inductor in the first-stage LNA has an inductance of 1.42 nH, Q of 11, and fQmax/fres of 13.5/30 GHz, respectively.

On the other hand, when considering a transformer, if varactors are employed at both nodes, and L1

C

1(V)=L2

C

2(V) is still fulfilled, i.e., which is the same as the result of a parallel LC tank because the peak frequency ωpk is proportional to tank resonance frequency ω0 (_pk  0 1 ).

k

which is derived in Appendix F.

That is, the tuning capability of a transformer with only one varactor on either side is half of a parallel LC tank or a transformer with varactor loads at both sides.

Thus, a higher Cr should be applied to cover the desired frequency range.

Fig. 6-54 Schematic of the LNA transformer with an input varactor and output pure capacitance load.

As shown in Fig. 6-54, C1 mainly consists of the varactor and the Cgd of the cascode device in the second-stage LNA. On the other hand, at the output stage, the differential capacitances of the transconductance stage of the mixers are in series but I and Q mixers are in parallel. Therefore, the differential load capacitance C2 is approximately equal to Cgs of a single transistor.

Similar to an LC tank, the decision of the varactor value can also be applied.

Thus,

1,max 1, 1,max

1,min 1, 1,min

1 2.5

1.637 1

const V r

const V r

C C C C

C C C C

  

  

  . (6.43)

Thus,

C

r should be larger than 0.417 and is set to 0.5 in this work. If C1,const is set to 0.3 pF, the C1,max/ C1,min=1.05/0.45 pF, respectively. C1,center=(C1,max×C1,min)^1/2= 0.687 pF while C2=Cgs =0.3 pF. The best transformer turn ratio n is (0.3/0.687)^1/2

0.66 2 3

  . Thus, a 2:3 planar single-to- differential transformer is chosen. The applied 2:3 transformer load has a line width of 9 μm, a line spacing of 2 μm and an outer diameter of 190 μm.

2) Sub-Harmonic Mixer

An SHM has better dc-offset output than a fundamental mixer because of the additional LO rejection, inherently [41]. A top-LO SHM is applied because of a lower voltage headroom requirement and a better isolation when compared with a stacked-LO SHM at the cost of a larger LO power requirement. Additionally, parasitic V-NPN BJTs, obtained in deep-n-well CMOS process without extra mask [50], is applied at the mixer switching core to directly eliminate the 1/f noise problem, as shown in Fig. 6. Since the V-NPN BJT has a low fT of around 2 GHz, a receiver covering U-NII bands is rarely achievable originally. However, using both resonance inductors (at LO differential base nodes and common emitter nodes) and the sub-harmonic operation, an SHM operated at three times the transistor fT is achieved in this work. Four differential inductors are in parallel with the base nodes of the switching core of the I/Q mixers and the output nodes of the LO generator to reduce both the conversion loss of the switching operation and the LO loss of the LO generator simultaneously. The details about the LO loss reduction will be discussed later.

Fig. 6-55 Top-LO sub-harmonic Gilbert mixer with vertical-NPN BJT in the switching core while an LC network is applied for an IM2 improvement.

On the other hand, self-mixing, transconductor nonlinearity, switching pair nonlinearity, and mismatch in load resistors are the main reasons for the IIP2

degradation in downconversion mixers [109]. Self-mixing of RF signals due to coupling into the LO port can be significantly reduced by means of layout concerns,

e.g., metal lines carrying RF and LO signals should never cross each other, or at a

minimum, should be kept orthogonal. Further, employing highly linear polysilicon resistors makes the effect of load resistors negligible. Device nonlinearity of RF transconductor generates the second-order inter-modulation distortion (IM2) components. A perfectly matched switching stage upconverts the input differential baseband spectrum at mixer output. However, the RF IM2 components leak into the IF output by the low-frequency gain of the switching pairs if mismatches in the switching stage devices are considered. In principle, low-frequency RF IM2

components can be filtered out by AC coupling the switching stage. However, the additional power consumption of separately biasing the input stage and mixer core is not desirable in our low-power application.

In this work, an LC filter (LSW-CFAT-LSW) is applied to filter out the IM2 current in RF transconductor [108], as shown in Fig. 6-55, since the shunt inductor LSW has a relatively low impedance at low frequencies and the IM2 current can be directly shorted to ground by the by-pass capacitor (CFAT) applied at the center-tapped node of the symmetric inductor. It is noteworthy that CFAT should be large enough for an IIP2

improvement. In this work, CFAT is 15 pF. When compared to the tens of MHz RF applications, the IIP2 value drops dramatically due to the parasitic capacitance Cpar at high frequencies [108]. The LSW in the LC filter can also resonate out the parasitic

C

par. Thus, both the high-frequency gain and the IIP2 performance of the Gilbert mixer can be improved.

For a chip area concern, a 3D symmetric inductor realization is used, as described in Section 6.4.1. The symmetrical 3D inductors (effectively 6 turns from metal 6 to metal 1) with 8-μm line width, 2-μm line spacing and 70-μm outer diameter are applied at the LC filters in I/Q mixers and have the differential inductance of 2.4 nH and Q=3.6 at around 5-6 GHz.

3) Wideband LO Octet-Phase Generator

The proposed wideband octet-phase signal generator used at the LO port of the SHM, shown in Fig. 6-56, consists of a differential-type wideband 45° phase shifter [41], [110], two differential buffer amplifiers and two PPFs with symmetrical inductor loads.

Fig. 6-56 Block diagram of an LC octet-phase generator including a wideband 45° phase shifter, cross-coupled buffer amplifiers and single-stage PPF with resonance inductors.

The LO amplitude/phase should be very accurate covering around 2.5-3 GHz (half of U-NII band frequency). A first-order RC phase shifter has the perfect 45°

phase shift only at a single frequency. Further, a tunable version of the phase shifter using varactors is applicable but tunable narrow-band structures of both RF and LO parts lead to much inconvenience in controlling both ends under precise conditions in practical use. Thus, a second-order RC phase shifter is employed to cover a given

bandwidth without tuning.

Fig. 6-57 (a) Schematic of a differential-type wideband 45° phase shifter (b) phase difference shifter with respect to frequency.

The schematic of the phase shifter is shown in Fig. 6-57(a) and the RC relations are summarized as follows.

1 1 2 2 3 3 1

The output voltage of the phase shifter can be expressed as

2

To obtain balanced amplitudes of all nodes at all frequencies, b=4(a+1)/a² should be chosen and the voltage loss can be re-expressed as

2

According to Eqn. (6.47), the voltage loss only depends on the coefficient a, and is independent of frequency. A smaller a results in lower loss; thus, a=1 (b=8) is chosen in this work to achieve a voltage loss of 6 dB. Besides, the phase error varies as the two center frequencies f1 and f2. Thus, f1/f2 are set at 1.566/4.85 GHz, respectively, for the perfect 45° LO phase difference achieved at around 2.55 and 2.95 GHz, as shown in Fig. 6-57(b). Thus, ideally phase error of below ±0.1° is achieved covering the LO frequency from 2.5 to 3 GHz (i.e., 2LO frequency of 5-6 GHz).

The amplitude/phase relationships derived above hold only when the load impedance is infinity. Thus, when a PPF is cascaded after the phase shifter for quadrature signal generation, the low input impedance of the PPF results in a significant phase error. Conversely, if the resistance is set high (e.g., over kΩ), i.e., the capacitance of the PPF should be small because ωLO=1/RC, meaning that the voltage loss due the output capacitance loadings will be unacceptable [95]. As a result, an

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