Chapter 6 Low-Power Low-Noise Direct-Conversion Receiver
6.2 Low-Power Design Optimization
6.2.1 Low-Noise Amplifier Design Optimization With On-Chip Inductors at a Fixed
Z in
Fig. 6-1 Schematic of a cascode LNA with a single-to-differential transformer connecting to the transconductance stage of the following I/Q Gilbert mixers.
The schematic of a widely used cascode LNA with a source degeneration inductor (Ls) is shown in Fig. 6-1. The Ls is used to make the optimal noise impedance and input impedance almost equal. The cascode structure provide better reverse isolation than a common-source structure, avoiding the LO leakage leaking back to the RF input and even to the antenna.
At a high operating frequency, the intrinsic device NFmin and fT are not good
enough due to the technology limitation. Besides, the matching inductor Lg (and its accompanying series resistance RLg) is relatively small as will be shown in Egn. (6.5).
In this case, the intrinsic device NFmin dominates the overall LNA NF, not the extrinsic thermal noise of the series resistance RLg. A higher current density results in a better performance at the cost of high dc power consumption. However, over 200 μA/μm JD, the mobility degradation occurs and results in lower gm and thus lower fT
and also the increase of NFmin. As a result, for a well-known high-frequency CMOS LNA design, a device with approximately 150-μA/μm current density (JD) is generally used for a minimum NF and high fT, and thus, a maximum gain [79]. Note that using an advanced technology can lead to better NFmin, fT, and also less power consumption at a higher cost.
At a low operating frequency, the intrinsic device NFmin, fT and the resulting gain are sufficiently good, and thus, a power-constrained noise optimization design (PCNO), proposed by Shaeffer and Lee [80], is more practical for a low-power design.
However, a small device size with a high JD results in an incredibly large Lg. The extrinsic thermal noise of RLg instead of the intrinsic device NFmin dominates the overall NF and there exists an optimal device size for the best noise performance [81].
Recently, Nguyen et al. proposed a power-constrained simultaneous noise and input matching (PCSNIM) by adding a parallel capacitance Cp in Fig. 6-1 for LNA design.
The NF of the resulting LNA approaches the intrinsic device NFmin and impedance matching is achieved at the same time for every transistor size at a fixed ID when wire-bonding is employed for Lg and thus the RLg is negligible [82]. There is no discussion on the effect of lossy matched inductor for PCSNIM in this literature yet.
Here, the effect of RLg is discussed and the benefit of the parallel Cp for a significant reduction of extrinsic thermal noise of RLg is highlighted by clear and detailed graphic
analysis. There also exists an optimal device size for the best NF and the resulting NF is better than the NF obtained by PCNO method [81].
A. SNIM Method
The simultaneous noise and input matching (SNIM) is achieved by adopting a reactive degeneration inductor Ls. The input impedance and noise matching are discussed as follows.
1) Input Matching with the Effect of Low-Q Inductors
The input impedance of a cascode LNA, shown in Fig. 6-1, can be expressed as
( ) ( ) 1 ( ) ( )
in g Lg s Ls t m s Ls t
Z sL R sL R sC g sL R sC (6.1) where RLg/RLs represent the series resistance of the inductance Lg/Ls. Typically, RLs is much smaller than RLg and can be neglected.
C
t C
gs C
p when a parallel capacitance Cp is applied.Since an on-chip planar inductor can be modeled as an inductor L in series with a resistor R when the operating frequency is lower than fQmax. Here, QL
of an inductor is
defined as ω0L/R. Generally speaking, the series resistance is proportional to the
geometric length and thus proportional to the series inductance. That is,0 0
( )
R
Q L
, where αL
0 is close to a constant, only relating to the geometricalshape (including metal width, spacing and metal thickness). Thus, the
Z in (1) can be
in modified as0( ) ( ) (1 0 )
in g s m s t g s m s t
Z L L g L C s L L g L sC . (6.2) To achieve impedance matching at a target resonance frequency (ω0) and the target matching impedance RS=50Ω when the device size (Cgs) (or Ct) and bias (gm) are decided,
0 Note that, if no series resistance RLg is considered (i.e., α0=0), the well-known results for impedance matching are
L
s R C g
S t m andLg 1 (20Ct)Ls.Besides, the transconductance gain of the input transistor M1 at resonance can be expressed as other words, a smaller Ls results in a higher gain.
2) Noise Matching
In this part, we consider the equations for the lossless matching condition (without RLg) because the mathematical expressions will be complicated and the insight is lost when considering the effect of lossy inductors. Later in the following sections, a graphical analysis is adopted for a clear view of the noise optimization.
The general formula of the optimal noise impedance (Zopt) of the common-source configuration with Ls and a parallel capacitance Cp can be expressed as
2
where α=gm/gd0, γ is a constant for the channel thermal noise current, δ is a constant for the gate induced noise current, and c is a correlation coefficient of the gate-induced noise current and the channel noise current [82], [84]. If no Cp is applied, an optimal device size (or Cgs) can be determined by fulfilling Re{Zopt}=Re{ZS} by setting Ct=Cgs in Eqn. (6.7). Then, the size of Ls is determined by Im{Zopt}=−Im{ZS}.
For the given values Cgs and Ls, the value of Vgs (or the dc current consumption ID) can then be determined from Re{Zin}=Re{ZS}. Thus, under lossless matching condition, the minimum noise factor (Fmin) can be expressed as
2
B. PCNO Method with the Effect of Low-Q Inductors
0 5 10 15 20 25 30 35 40
Fig. 6-2 Simulated device minimum noise figure (NFmin) at 2.4 GHz and cut-off frequency (fT) of a 0.18-μm RF NMOS as a function of current density (JD=ID/W).
When the operating frequency is low (such as 2.4 GHz in this paper), the optimal transistor size is very large because Re{Zopt} is inverse proportional to ωCgs by Eqn.
(6.7). Thus, the Fmin can only be reached at a high ID. Fig. 6-2 shows the simulated NFmin at 2.4 GHz and fT of a single RF NMOS device (W/L=240μm/0.18μm). Thus, if the ID is fixed, a larger transistor size (i.e., a lower JD) results in a lower fT and a higher NFmin. It reveals that even though a perfect noise matching is achieved using a large device, the NF may be even higher than the NF using a small device because of the limited fT and the higher device NFmin at a fixed ID.
As a result, the PCNO method [80] is preferred to achieve a sub-optimal NFmin,P
at a fixed dc current criterion ID. The ID is set by the requirements on gain, NF and linearity of the LNA. However, NFmin,P≥NFmin because of the mismatch between ZS
and Zopt. Eventually, NFmin,P tends to approach NFmin as the ID increases.
Here, a cascode LNA with a parallel RLC resonance load (=400 at resonance) as shown in Fig. 6-1 is simulated for different transistor size (W1) of M1, series inductance Lg/Ls and Cp, while the gate width (W2) of M2 is 240 μm and the RLC tank is resonated at 2.4 GHz. All of the device gate lengths are kept at 0.18 μm. The device model is BSIM3v3.24 provided by the foundry. Here, α0=0, 1, and 2 Ω/nH are simulated for both Lg and Ls and the corresponding QL=ω0/α0=∞, 15, and 7.5 at 2.4 GHz. α0=2 Ω/nH is especially addressed because it is the typical value of an on-chip spiral inductor using ultra-thick metal (UTM) and metal width is 6 μm while the fQmax
is still higher than the operating frequency.
Following the PCNO concept, Fig. 6-3(a) shows the required Lg
and L
sof the
LNA while the IDis fixed at 2.5 mA. The corresponding NF and A
V of the LNA are indicated in Fig. 6-3(b) and (c), respectively. The Ls should be smaller when a larger α0 is applied, as shown in Fig. 6-3(a) and can also predicted in Eqn. (6.4). Note that, the difference in Ls due to different α0 is less than 0.4 nH. Lg is typically the same for different α0, because Cgs remains the same and Lg is much larger than Ls. Asmentioned above, the NF (α0=0) of a large device is higher than that the NF of a small device at a fixed ID, The NFmin,P of a cascode LNA has the same trend of a pure device.
200 300 400 500 600 700
0
200 300 400 500 600 700 0.0
200 300 400 500 600 700 25
Fig. 6-3 (a) Lg and Ls for power-constrained noise optimization at 2.4 GHz and the corresponding. The required Lg for different α0 is very similar due to the same Cgs and a small Ls (b) noise figure and (c) voltage gain of the cascode LNA without Cp while the supply current is 2.5 mA. The unit for α0 is Ω/nH.
In this case, a smaller device with lower device NFmin and higher fT is preferable except for the input matching bandwidth because the input impedance matching
bandwidth
f
10 dB(for |S11|<−10 dB) is ω0/(6πQin), where Qin=ω0(Lg+Ls)/(R +R
in S)=QS/2 in this paper because
R
in R
S is designed [85]. However, when considering the extrinsic RLg(i.e., α
0≠0), the noise factor (F) has one additional term of (RLg+RLs)/RSTherefore, the series resistances of on-chip low-Q inductors make the NF increase dramatically and even dominate the overall NF. As shown in Fig. 6-3(b), the phenomenon is serious especially when a small device is chosen or at a low operating frequency because the required large Lg accompanies enormously large RLg. That is, the NF optimization suffers from severe trade-offs between the thermal noise of extrinsic RLg and the intrinsic device NFmin. For an extreme case, a series on-chip low-Q inductor may directly used for lossy impedance matching without the need of
L
s. However, the NF is always larger than 3 dB, theoretically, because of the 50-Ω input series resistor [86]. For the case of α0=2 /nH, the minimum achievable NF is around 2.03 dB with 450-μm W1 (i.e., JD=5.6 μA/μm) although the NF is still higher than the NFmin.Note that, a smaller α0 always leads to a lower NF. Thus, external wire-bonding and off-chip matching network are sometimes employed for input matching [80], [82]
because of the very low series resistance in an inductor (i.e., α0). However, these have significant percentage error and are time-consuming and difficult to mass produce. On the other hand, for an on-chip low-Q inductor, a wider line width results in a smaller series resistance (i.e., a smaller α0) but a lower fQmax. If the fQmax is near or
even lower than the operating frequency, the simple inductor model (R=α0
L) fails and
the overall NF of the LNA increases, too. Thus, the passive component layout optimization is required for a sufficiently low α0.
100 200 300 400 500 600 0.0
100 200 300 400 500 600 0
100 200 300 400 500 600 0.0
100 200 300 400 500 600 25
Fig. 6-4 (a) Cp (b) Lg and Ls for power-constrained simultaneous noise and impedance matching at 2.4 GHz and the corresponding (c) noise figure and (d) voltage gain of the cascode LNA with Cp while the supply current is 2.5 mA. The unit for α0 is Ω/nH.
C. PCSNIM Method with the Effect of Low-Q Inductors
For the PCSNIM method in reference [82], a Cp is applied to modify the Re{Zopt} without changing the NFmin described by Eqn. (6.8) and makes the noise and
impedance matching achieved at the same time for every transistor size at a fixed ID
when RLg is negligible. A graphical method is employed here for the PCSNIM method with the effect of low-Q inductors.
Fig. 6-4 shows the simulation results of the cascode LNA w/ Cp following a PCSNIM method while ID=2.5 mA. The Cp chosen for optimal noise performance and the Ct=Cgs+Cp are drawn in Fig. 6-4(a). However, no Cp is required to achieve noise matching when W1 is larger than 600 μm. The corresponding Ls and Lg are drawn in Fig. 6-4(b). Fig. 6-4(c) and (d) show the corresponding achievable NF and AV (voltage gain), respectively. The line with square symbols in Fig. 6-4(c) clearly shows the results using PCSNIM but without RLg. When considering low-Q (high-α0) inductors, a higher α0 of an inductor requires a larger Cp to reduce the required Lg and the corresponding RLg for an optimal overall NF, as shown in Fig. 6-4(a) and Fig. 6-4(b).
This advantage is much more significant than the reduction of the device noise. As a result, when considering the RLg, the minimum achievable NF w/ Cp [in Fig. 6-4(b)] is lower than the NF w/o Cp [in Fig. 6-3(b)] for a given α0. Note that, when α0≠0, the AV
using PCNO decreases progressively when W1 increases as shown in Fig. 6-3(c).
However, when using PCSNIM with low-Q inductors, the applied Cp degrades the overall Gm of the LNA as shown in Eqn. (6.6) while the device NFmin remains the same especially for a small transistor size. Thus, not only the NF but also AV has an optimal device size when RLg is considered. Besides, the optimal width increases if a larger α0
is applied as shown in Fig. 6-4(c) and Fig. 6-4(d). As a result, the Cp for minimum achievable NF is around 0.2~0.3 pF when α0=2 Ω/nH. The corresponding Lg is around 6~7 nH, which is implementable and occupies a small die area. The minimum NF is below 2 dB and AV is above 33 dB when W1 ranges from 200 to 400 μm (JD=6.5~12.5 μA/μm).
Further, if the matching condition is not limited to a perfect 50 Ω, a smaller chosen of matching impedance RS is selected, the AV also increases, as predicted in Eqn. (6.6) and NF slightly decreases due to the smaller RLg at the cost of the matching bandwidth. Thus, changing the matched impedance to around 35~40 Ω by decreasing the Ls results in a higher AV, a lower NF and allowable matching bandwidth. Finally, the W1=240 μm (4-μm unit width×60 fingers) is chosen to achieve both optimal NF and AV.