Variable-Gain Amplifier With Linear-in-dB Tuning Scheme

Chapter 6 Low-Power Low-Noise Direct-Conversion Receiver

6.2 Low-Power Design Optimization

6.2.4 Variable-Gain Amplifier With Linear-in-dB Tuning Scheme

V-NPN BJTs are also used at the input gm stage of the IF amplifier to eliminate the flicker noise problem. Besides, the gm of a BJT transistor is much larger than that of a MOS transistor for the same bias current. Thus, the voltage gain of the VGA is improved using V-NPN BJTs. Conventionally, the quasi-exponential function was realized by an R-r attenuation load with a combination of the constant resistance R of the rigid resistance and the variable resistance r implemented by a MOS transistor in the triode region as shown in Fig. 6-11 [88]-[89]. The impedance of the R-r attenuator can be expressed as R/(1+R×gds), and has an approximate exponential characteristic in a certain region [88]. It is well known that gds is proportional to VOV

(=V

−V

T) in the triode region. Thus, we can control the impedance of the attenuation load with the R-r exponential function. The R-r attenuation load is typically implemented at the load of the VGA. However, the output 1-dB compression point (OP1dB) degrades in low-gain mode due to the limited input linear range, especially for a BJT input gm cell.

Therefore, both loading and emitter R-r attenuators are applied to maintain the OP1dB

of the VGA, especially in low-gain mode. The equivalent two-section R-r attenuation results in a wider linear-in-dB tuning range (~20 dB) while typically a one-section R-r attenuator has a linear-in-dB tuning region of 10 dB approximately.

The schematic of the VGA with both loading/emitter R-r attenuators is shown in Fig. 6-11. A PMOS is employed at the drain node and an NMOS is chosen for the emitter degeneration. The drain-source resistance (Rds=1/gds) of the NMOS/PMOS transistor in the triode region decreases/increases as the IF tuning voltage, VTIF, increases. Thus, the voltage gain has a positive gain slope with respect to the VTIF.

Fig. 6-11 VGA with a modified R−r attenuation method. with different locations of transitions (c) the corresponding AV as a function of VTIF.

The differential voltage gain of the VGA can be easily formulated as

1 2

m C

m E

A g R

 g R

 (6.13) where RE=RPE || rPE and RC=RPC || rop || ron || rPC ≈ RPC || rPC while assuming rop, ron

>>RPC. RPE,C is the rigid resistor and rPE,C is the NMOS/PMOS drain-source resistance in the triode region.

Fig. 6-12(a) shows the calculated numerator gm×RC and the inverse of the denominator, 1/(1+gm×RE/2), as a function of the IF tuning voltage (VTIF). On the curve of gm×RC, the transition (T1C) occurs when rPC becomes larger than RPC. The curve of 1/(1+gm

R

E/2) has two transitions, T1E and T2E. T1E transition occurs as rPE

becomes smaller than RPE while T2E occurs as gm

R

E/2 becomes less than 1 (i.e.,

R

E<2/gm). Typically, two tuning voltages should be used to control the two tuning operations. However, after proper design of bias points by transistor sizes, one tuning voltage can be adopted by properly overlapping the two constituent tuning curves.

Because AV is the multiplication of both curves, different sequences of transitions result in different composite tuning curves. Fig. 6-12(b) shows the calculated AV for two sequences (1) T1C<T1E<T2E and (2) T1E<T1C<T2E, respectively. For the former sequence, there is a certain region with a constant voltage gain which is not permissible for real applications as shown in Fig. 6-12(b). On the contrary, a smooth tuning curve can be obtained by the latter sequence of T1E<T1C<T2E.

6.3 2.4 GH

R

ECEIVER

W

ITH

P

ASSIVE

M

IXER

R

EALIZATION

A 2.4-GHz 0.18-μm CMOS DCR is demonstrated using passive mixers to avoid the flicker noise problem in this section. The block diagram of the proposed 2.4-GHz DCR is shown in Fig. 6-13, including an LNA with a single-to-differential transformer load, I/Q passive mixers and IF TIAs and VGAs. Besides, the quadrature

LO signal is generated by a two-stage PPF with the center frequency of 2.4 GHz.

Fig. 6-13 Block diagram of the 0.18-μm CMOS 2.4-GHz DCR using passive mixers.

(a) (b)

(c)

Fig. 6-14 Schematic of (a) single-balanced passive mixer (b) double-balanced passive mixer with single-ended RF input (c) double-balanced mixer with differential RF input.

A cascode LNA with a parallel capacitance Cp is shown in Fig. 6-1. The parallel

C

p can be used to reduce the noise impedance under a low power dissipation,

especially at such a low operating frequency of 2.4 GHz, as fully discussed in Section 6.2.1.

Fig. 6-14(a) shows a single-balanced mixer structure which can downconvert the RF sign al but has large amount of LO-to-IF leakage, which can only be suppressed by the following low-pass circuits. Besides, the RF-to-IF leakage is typically a common-mode leakage, which can be cancelled if the following circuits are fully differential. On the other hand, for the double-balanced structure, shown in Fig.

6-14(b) and (c), the large LO signal is cancelled at the IF port. However, the latter structure with fully differential RF inputs performs better RF-to-IF isolation even if the IF output is taken at each signal end. Hence, a single-to-differential transformer is used between the LNA and the passive mixer.

Fig. 6-15 Schematic of a single-stage OP-amp with V-NPN transconductance stage.

The TIA cascaded after the passive mixer consists of a single-stage operational amplifier (OP-amp) with parallel R/C feedback paths. When compared with a common-gate amplifier, which is another widely used structure, the lower input impedance results in better mixer current gain and also better noise performance [74].

Besides, the V-NPN BJT is employed as the gm stage of the OP-amp, as shown in Fig.

6-15 because of the free of flicker noise and a high gain at a low current, as emphasized in Section 6.2.3. On the other hand, the R-r attenuation method is applied

at the IF VGA to achieve a linear-in-dB tuning scheme while the V-NPNs are also used at the gm stage as shown in Fig. 6-11 described in Section 6.2.4.

Fig. 6-16 Die photo.

1.8 2.0 2.2 2.4 2.6 2.8 3.0

40 42 44 46 48 50 52

Noise Figure (dB)

CG IF=100 kHz

Conversion Gain (dB)

RF Frequency (GHz)

2 3 4 5 6 7 8 9 10

DSB NF

Fig. 6-17 Conversion gain and double-sideband noise figure.

The die photo of the 2.4-GHz DCR is shown in Fig. 6-16 and the die size is 1.3×1.25 mm². On-wafer measurement facilitates the RF performance. Fig. 6-17 shows the conversion gain and double-sideband noise figure as a function of the RF frequency. The conversion gain is around 49 dB from 2.1 to 2.4 GHz when LO power is 10 dBm. The minimum noise figure is 3.7 dB and less than 4 dB within 2.2-2.4 GHz. The flicker corner is around 100 kHz when LO frequency is 2.4 GHz, as shown

in Fig. 6-18. Fig. 6-19 indicates the conversion gain with respect to VGA tuning voltage (Vtune). An over 20 dB tuning range is achieved.

100k 1M 10M

0 2 4 6 8 10

Noise Figure (dB)

IF Frequency (Hz)

DSB NF LO=2.4 GHz

Fig. 6-18 Noise figure with respect to IF frequency.

0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4

10 20 30 40 50 60

Conversion Gain IF=100 kHz

Conversion Gain (dB)

Vctrl (V) Fig. 6-19 Conversion gain with respect to IF VGA tuning voltage.

The I/Q output waveforms are shown in Fig. 6-20 with 0.13 dB gain difference and 1.03º phase error when RF =2.4001 GHz and LO=2.4 GHz. Fig. 6-21 shows the gain difference < 0.3 dB and I/Q phase error < 2° when LO frequency ranges from 2 to 3 GHz. The input return loss is lower than 10 dB covering 2.1-2.8 GHz as shown in Fig. 6-22.

Fig. 6-20 Output I/Q waveforms.

Fig. 6-21 I/Q amplitude mismatch and phase error.

1 2 3 4 5 Fig. 6-22 Input return loss.

Moreover, the LO-to-RF/LO-to-IF/RF-to-IF isolation are around 90/50/50 dB,

respectively, when LO frequency is near 2.4 GHz, as shown in Fig. 6-23. The circuit performance is summarized and compared with state-of-the-art DCRs in TABLE. 6.1.

1.8 2.0 2.2 2.4 2.6 2.8 3.0 Fig. 6-23 LO-to-RF/IF isolation.

TABLE.6.1PERFORMANCE COMPARISON OF DCRS USING PASSIVE MIXERS

Technology 65 nm digital CMOS 0.13μm CMOS

a off-chip input matching

b excluding off-chip baseband circuits

c w/o LNA

6.4 2.4 GH

L

-N

OISE

R

ECEIVER

W

ITH

V

ERTICAL

-NPN BJT

6.4.1 2.4 GHz Receiver With Vertical-NPN BJT Operating at Near Cut-Off Frequency

A 2.4-GHz low-power low-noise DCR is demonstrated using parasitic V-NPN BJTs in a standard 0.18-μm CMOS process. The current switching operation of a Gilbert mixer with finite transistor fT is thoroughly analyzed and discussed in this section. When the mixer operates near or higher than the transistor fT, the loss of the PPF due to the capacitive loading of the mixer is a main issue. Thus, BJT devices with smaller base resistance and an inductive peaking technique with symmetric 3D realization are employed in this paper to reduce LO power by 4.5 dB.

Fig. 6-24 Block diagram of the DCR including LNA, I/Q mixers, I/Q VGAs and an LO quadrature generator.

Fig. 6-24 shows the block diagram of the DCR consisting of a single-in-differential-out LNA, I/Q Gilbert mixers with the V-NPN BJT switching core, I/Q VGAs and an LO quadrature generator. The schematic of the LNA is shown in Fig. 6-1. The noise-impedance-matched LNA under power constraint with the effect on lossy inductors is fully discussed in Section 6.2.1. A tuning transistor (MT) is used to achieve gain reduction and avoid signal compression when a large RF signal is applied. The transistor MT acts as a current switch that reduces the output signal by

shunting the RF current away from the inductive load, as shown in Fig. 6-1. In addition, a 5:4 transformer is employed at the load of the cascode LNA to transform the single-ended input current to differential output voltage. The gate dc voltage of the

g

m stage in I/Q mixers is fed from the center-tap of the secondary coil in the transformer. On the other hand, an IF VGA with 20-dB linear-in-dB tuning range is implemented using an R-r attenuation method, as shown in Fig. 6-11 in Section 6.2.4.

1 0

1 _LO T  f

 1

( ) ( ) s t s t 

(a) (b)

Fig. 6-25 (a) Schematic of the Gilbert mixer with V-NPN BJT in LO switching core (b) LO switching function with infinite/finite fT in large LO region.

The V-NPN BJT has only around 200-Hz flicker noise corner, while the advanced 0.18-μm NMOS device has around several-MHz corner frequency under the same dc current of 250 μA, as shown in Fig. 6-9 in Section 6.2.3. Thus, V-NPN BJTs are used in the LO switching core to guarantee a low flicker corner as shown in Fig.

6-25(a). Instead of a pure resistive load (without flicker noise contribution), PMOS devices with a 2-μm gate length are applied for a more constant dc bias against process variation and still have allowable flicker noise performance. On the contrary, the high-performance but high flicker corner NMOS device can be used in the RF LNA and the RF gm stage of the mixers because the low-frequency noise at the RF stage will be upconverted to the odd harmonics of the LO signals, not baseband, after the switching operation.

Although the V-NPN BJT in the mixer core has a 200-Hz flicker noise corner, it has a relatively low fT. Here, we stress the effect of the transistor fT on the switching function. The BJT-based Gilbert cell has an exact mathematical expression of current switching function [3]

The small-signal conversion gain of the current switching function can be computed as the mean dc output current when the input signal is

cos( )

The current switching function can be simplified for two extreme cases:

sgn( ), 1 (large LO)

That is, the switching function of the mixing core in the large-LO (fully-switching) region can be approximated as a square-wave, drawn by the dotted line in Fig.

6-25(b).

Therefore, the

CG of the switching function s(t) in the large-LO region is 2/π

[94]. On the other hand, when the LO power is small, the CG can be calculated as

0 That is, the CG is proportional to the LO voltage swing (VLO).

-20 -15 -10 -5 0 5 10

Fig. 6-26 Conversion gain with respect to LO power at different for different fT when (a) LO voltage signals are directly fed to the base nodes of the switching core (b) LO signals are generated from a two-stage PPF (c) conversion gain degradation as a function of relative cut-off frequency ( f_T  f_T f_LO ).

The simulated

CG of a Gilbert mixer [Fig. 6-25 (a)] is shown in Fig. 6-26(a) with

different fT of the BJT switching core, while the differential LO voltage signals are fed from the base nodes of the switching core. Fig. 6-26(a) clearly shows that the CG increases as the LO power increases when the LO power is small. Gradually, the CG reaches a wide flat gain response (i.e., in the large-LO region). The wide LO power range with a flat-gain response covers typically more than 10 dB. However, when the LO signals are generated by a two-stage PPF, the conversion gain with respect to the LO power can be re-drawn as Fig. 6-26(b). Comparing Fig. 6-26(a) and (b), the required LO power increases when adopting a PPF. Further, at a higher frequency, the required LO power is also larger and thus the flat-gain region becomes narrower.

On the other hand, the conversion gain at the flat-gain region is the same in two figures at a given frequency. In the large-LO region, the switching function s'(t) replaces s(t) as indicated by a solid line in Fig. 6-25(b) when a finite fT is considered and can be expressed as LO period while Cπ2 and Cπ3 are charged in the negative LO period. Thus, after the detailed derivations summarized in Appendix B, the CG of s'(t) is

where

f

_T 

f

_LO represents the relative cut-off frequency. It is evident that a lower fT results in a lower CG as shown in Fig. 6-26(a).

As a result, the gain degradation of the mixer (GDMIX) due to the finite transistor

f

T can be represented as

In fact, the low fT of the switching transistors also results in an LO voltage loss because of the loading effect of the LO PPF [95]. The flat gain region corresponding to the fully switching function becomes smaller for a lower fT as shown in Fig.

6-26(a). Thus, the LO voltage loss is tolerable in the large-LO region.

On the other hand, the CG degrades much more seriously in the small-LO region than in the large-LO region as shown in Fig. 6-26(b). Because the CG is proportional to VLO when the Gilbert mixer operates in the small-LO region, the degradation of the LO voltage directly leads to CG degradation. As a result, the GD due to LO loss (GDLO) should be included and the overall GD can be approximated as

GD

total= GDMIX×GDLO. (6.21) where gm is the transconductance of the switching device and Rn is the resistance at the nth stage (last stage) of the PPF. The complete derivation is also summarized in Appendix B.

For a more clear observation of the GD, Fig. 6(c) shows the GD with respect to the relative cut-off frequency ( f _T ) at different LO power levels and the data is directly taken from Fig. 6-26(b). The line with the square symbol represents the calculated GD in the large-LO switching function (i.e., GDMIX) while the GD with small LO input is indicated by triangular symbols (i.e., GDMIX×GDLO). Two lines

successfully represent the upper and lower bounds of the GD at different LO power levels while the solid lines represent the simulated GD at different LO power and are thoroughly located within the two calculated boundaries.

It is noteworthy that, this phenomenon is also suitable for an MOS switching core. However, a larger LO power is required to commute the tail current from one side to the other because a MOS differential pair requires a 2

V LO voltage swing

_ov while only around 4VT (~0.1 V) is required for a BJT core. As a result, the fully-switching region of the LO power range is relatively narrow and even disappears if a low-supply voltage is applied.

A multi-stage PPF is widely used as a quadrature generator in single-sideband upconverters, image-rejection downconverters and I/Q downconverters [26], [95].

Since the quadrature phase error of the n-stage PPF can be expressed as

1 0 0

2 tan [(^ ) ( )]ⁿ

      where ω0 is the designed center frequency. In other words, for a given tolerable phase error  , the ratio bandwidth becomes ₀

[(1+εn)/(1−εn)]² where εn=tan¹ⁿ(₀ 2). That is, more stages of the PPF results in a less phase error within the target bandwidth or a wider tolerable bandwidth for a given phase error. In addition, the phase accuracy is independent of loading, but the loadings affect the overall voltage loss, as mentioned in [95]. The PPF has a certain voltage loss due to both the inter-stages and the loading stages. In this work, we are especially concerned with the loss due to the output loading (i.e., the mixers) because it is the sole term related to the mixer transistor fT. As proposed in [95], the voltage division (VD) at the output node can be expressed as

0 0

( )

|| (1 )

L n n

VD Z

Z R j C

    (6.23) where  ₀ (R C_{n n}).

(a)

Fig. 6-27 (a) Schematic of the two-stage PPF with original capacitive load and additional inductive load (b) calculated optimal voltage division (VD) as a function of inductor quality factor (Q) for different capacitive loadings.

Conventionally, ZL is typically a capacitive load (CL) due to an active/passive mixer. Thus, A large loading capacitance results in an incredible loss. In this work, parallel inductors are employed to optimize the LO voltage loss, as shown in Fig. 6-27(a). A

simple model of a real inductor consists of a series resistor (RS) and an inductor (LS) with a quality factor (Q) defined as0 S

L R

S . Generally, the RS is proportional to the geometric length and thus also proportional to the LS. In fact, the parasitic capacitance

C

par should be included for each inductor, which can be merged to CL for simplicity.

After detailed derivations summarized in Appendix C, the maximum |VD(ω0)|

and its corresponding Lopt are

|VD| without peaking inductors is also indicated in the same figure. It reveals that when the loading capacitance is small, an inductive peaking technique has no improvement. Further, when Q reaches infinity, the |VD|opt=+3 dB, which is the same as the result in an open-load situation. However, in practice |VD|opt degrades due to a finite Q. For the double-balanced structure of a Gilbert mixer, the peaking inductor parallel between the PPF and mixer core should be also symmetric to maintain a fully differential performance. Besides, the differential inductor can provide size reduction and a better Q than separate inductors [96].

In this work, a 3D symmetric inductor realization is employed for further area saving. Fig. 6-28(a) shows the multi-layer structure of a pseudo-two-turn symmetric 3D inductor proposed in [97]. The top view and cross-section view of this 3D inductor are shown in Fig. 6-28(b).

(a) (b)

(c)

0 1 2 3 4 5 6 7 8 9

-10 -5 0 5 10 15 20

4.6

Simulated Inductance

Inductance (nH)

RF Frequency (GHz)

3.7

-2 0 2 4 6 8 10 12

EM Simulated Q

Fitted Q (w/ CP and substrate effects) Fitted Q w/ only series L and R

Quality Factor

(d)

Fig. 6-28 (a) 3D view and (b) top view of the pseudo-two-turn layout of the fully symmetric stacked inductor (c) top view and (d) simulated inductance and quality factor of the proposed pseudo-four-turn (equivalent eleven turns) fully symmetric stacked inductor.

A pseudo-two-turn layout can provide at most six turns of an inductor in a 1P6M 0.18-µm CMOS process. However, the inductance is not enough. Using the basic idea of interleaving the inner and outer turns, this structure can be extended to a pseudo-four-turn formation as illustrated in Fig. 6-28(c). As a result, a 3D inductor with eleven turns is achieved with 8-μm line width, 2-μm line spacing and an outer diameter of only 100 μm. The EM simulated differential inductance and quality factor are 7.2 nH and Qmax=4.5 with fQmax/fres of 3.6/8.2 GHz as shown in Fig. 6-28(d). Here, we emphasize that the Q of the inductor degrades by the parasitic capacitance but this is not included in the Q used in (13). In fact, after extraction, the 3D inductor has a differential inductance of 7.2 nH and a series resistance of 23.6 Ω. That is

Q=ω

L/R=4.6, not 3.7, as indicated in Fig. 6-28(d). Moreover, additional parasitic

capacitance should be added to CL when calculating Eqn. (6.25).

In this work, Cn=0.444 pF (Rn=150 Ω), CL=0.945 pF, and Qind=4.6. As a result, the loss due to the pure capacitive load CL (i.e., without inductive peaking) is around 4.31 dB. Around 3-dB improvement is obtained when using the inductive peaking technique, as shown in Fig. 6-27(b).

Further, all the above discussions are concerned about the pure capacitive mixer load. However, it is noteworthy that the series RB of the V-NPN BJT is important for the LO power loss, especially for the parasitic devices even though the current switching mechanism is dominated by the transistor fT. As indicated in Fig. 6-29, the RB not only decreases the load impedance (at resonance) of the PPF (i.e., increases the voltage loss due to the PPF loading) but also reduces the voltage delivered to Vπ by a factor of 1/(1+sRBCπ). The simulated CG with respect to LO power for different RBis shown in Fig. 6-30. Thus, a small RB results in a lower LO power requirement but the

在文檔中應用於解決CMOS閃爍雜訊之低中頻接收機架構和深N型井雙極性接面電晶體直接降頻接收機 (頁 149-187)