Chapter 3 KA BAND LNA USING 0.18μm CMOS
3.5 Conclusion
Recent works have shown CMOS as a promising means for building RF circuits in the low-gigahertz range. However, a high-performance CMOS front-end for applications above 20GHz has been reported and the performance of these CMOS circuits show CMOS process has potential for building RF systems above 20GHz.[34]~[36]. In this work, a 24-GHz low noise amplifier is designed, and the measured results shows the LNA achieves 12 dB gain at 30-GHz. By the CMOS 0.18um technology, this work presents the highest operating frequency compared with the reported literatures. The best matching point of the measured input return loss does not locate at 30-GHz, however it achieves -21 dB at 35-GHz. This deviation not only causes the gain lower than the desired one but also influences the noise figure performance. The frequency shift in this project is about 3-GHz form 27-GHz to 30-GHz. This phenomenon is observed in our simulation. The T-junction and the RF-pad are the issue in the EM simulation. The transmission lines as well as inductors in this project are simulated precisely. But the T-junction does not take into account. If the T-junctions are simulated, the frequency shift phenomenon appears. The RF pad and the input matching network are critical issues to the noise figure performance. The realistic RF pad and passive components contribute about 1.5 dB noise figure than the ideal passive components. These two problems are needed to overcome, and different EM simulators will be necessary to the high frequency simulation in the future for coupling affection.
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Chapter 4
K B AND F REQUENCY S OURCE W ITH X B AND L OW P HASE N OISE Q UADRATURE C MOS V CO
4.1 Introduction
Using standard CMOS process to implement millimeter-wave frequency sources had garnered more and more attention and became a tendency by the reason of low cost and high integration ability with other analog and digital circuits. The on-chip inductors with low-Q are the main defect for Si substrate and influence the phase noise directly. However, many recently published literatures of Si-based VCOs had demonstrated their competition with the GaAs process [39]~[44].
Above X band, a CMOS VCO with high performances is difficult to design. With a little increment of power consumption, frequency doubling scheme is the reasonable and effective approach to improving performance. There are several reasons to use a lower frequency oscillator with a frequency doubler instead of an oscillator operating at a higher frequency.
Generally, the phase noise of the latter is higher than that of the former. Furthermore, the usage of a frequency doubler mitigates the design difficulty of a high-frequency phase-locked loop (PLL). In general, a VCO has an oscillation frequency up to ~ fmax and a frequency divider operates approximately up to 1/4~1/2 of fT. It is very difficult to increase the operating frequency of a frequency divider up to the output of a high-frequency VCO.
A pair of differential signals of 2 f× 0 can be realized by a balanced doubling method.
To get a high-quality signal of a frequency doubler, accurate quadrature signals with low phase noises are required. A simple method to obtain accurate quadrature signals with low
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phase noises is to couple two symmetric LC-tank VCOs [41]. Several quadrature VCOs had been implemented and demonstrated in the X-band [39]~[44]. Hence, a K band CMOS frequency source with X band low phase noise quadrature VCO will be presented.
4.2 Circuit Design
4.2.1 Quadrature Signal
in+
in-out+
out-in+
in-out+
out-0° 90°
180° 270°
(a) (b) Fig. 4-1 Quadrature VCO architecture (a) connection of blocks (b) Transfer characteristic
Fig. 4-1 (a)(b) show the quadrature VCO architecture. The quadrature phase VCO comprises two mutually-coupled fixed frequency LC-oscillators. Frequency tuning is achieved by varying the coupling coefficient (β) between two oscillators. Oscillation frequency is adjusted along with loop gain compensation (α). This mechanism ensures that current injected into LC tank remains constant regardless of frequency tuning. Thus AM-to-PM phase noise conversion can be suppressed [41]
Consider two fixed-frequency LC oscillators whose outputs are coupled to their inputs with the coupling coefficients β and -β, as shown in Fig. 4-1. Each oscillator is modeled by a
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positive feedback loop with open loop gain H(jω). In steady-state, and if the two oscillators synchronize to a single oscillation frequency, ω, the output of each oscillator must satisfy the following equations:
This proves that the oscillatory system of Fig. 4-1 indeed provides quadrature outputs X and Y. By substituting equation (4.3) into equation (4.2), equation (4.4) can be derived.
1 ) ( )
(α ± jβ H jω = (4.4)
Equation (4.4) governs the frequency transfer characteristic of the quadrature phase VCO.
As the close loop phase response of these oscillators is varied by adjusting α/β, VCO's output frequency can be changed accordingly.
4.2.2 Frequency Doubler
4.2.2.1 Harmonics of Quadrature Signals
A VCO exhibits a strong nonlinear effect by the reason of the large output swing in the resonator. Since the nonlinear effect is related to many different physical phenomena, it cannot be modeled easily [39]. The output of a VCO now is modeled simply as a polynomial
...
where the A ’s are the harmonic coefficients and X is the input signal. If X is substituted by n )
If the four quadrature signals with the different phases of a quadrature VCO are inserted into
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(4.6), and fundamental frequency components are canceled out by adding two output signals with an input phase difference of 180°. A frequency-doubled differential signals are obtained and it follows:
.... The results show that a set of quadrature signals can create a pair of differential output with doubled-frequency, 2 f× . 0
4.2.2.2 Pinch-off Clipping
Fig. 4-2 Output signal of a pinchoff clipper derived by an input sinusoidal signal with low dc bias.
The device nonlinearity of a negative conductance cell mainly influences harmonics.
Since a MOSFET has high linearity and low fT, the harmonics of a MOS VCO are too small to use as a signal source, even though output power is increased by the push–push method.
Thus, some nonlinearity operation must be introduced to increase the nonlinear terms.
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Pinch-off clipping is a common method to increase harmonic power and the waveform of nonlinear operation is shown in Fig. 4-2. The output power can be thought of multiplying a square wave and a cosine wave. And this phenomenon can be represented as follows:
⎥⎦
If the driven signals have 180° phase difference and we combine these according two outputs, the output summation can be derived as follow:
∑
∞The results show that a pinch-off clipping can create a signal with doubled-frequency, 2 f× . 0
Fig. 4-3 The pinch-off clipping circuit used as a doubler in this project
The pinch-off clipping method is generally realized by driving a MOSFET with large signals. Fig. 4-3 shows the balanced pinch-off clipping circuits used in this project. Four PMOS transistors and two load inductors compose this clipper. And these PMOS transistors
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are driven by a set of quadrature signal form QVCO illustrated in next section. Two inductors are served as loading of the summation signal. Buffers are required for the consideration of measurement. Two bias-T networks are also used at the output of MQ7 and MI7. By the simulation results, these two balanced clippers consume totally about 4.9mW.
4.2.3 Proposed K Band VCO Architecture
Fig. 4-4 Block diagram of the K band frequency source
Fig. 4-5 The proposed quadrature voltage controlled oscillator.
Fig. 4-4 shows block diagrams of a balanced frequency doubler and quadrature VCO.
The pinch off clipper is requested to increase the power of harmonics. The pinch off clipper in this project is constructed by PMOS transistors. Thus, the input of a pinch off clipper should
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be biased at a higher dc level. However, the dc level of a VCO output is equal to the zero or half of that in a P-type or PN-type VCO. Dc level shifters are combined with the conventional P-type VCO to shift the output dc level of a QVCO at higher level. The quadrature VCO combining with dc shifter is shown Fig. 4-5.
The phase noise is a major consideration in a VCO design. The phase noise estimation has been widely discussed. For a single LC-oscillator, its phase noise can be expressed as below:
gm, is the transconductance of the current source MOSFET, R is the equal impedance eff of the LC tank, V is the amplitude of the oscillator [45]. o
The oscillation frequency can be roughly estimated by (4.13) [47].
) transistor, and the varactor capacitance, respectively.
The proposed VCO has low noise due to three noise-reduction mechanisms. The negative resistance cells are all constructed by cross-coupled PMOS transistors first to lower the phase noise contributing from the flicker noise of MOSFETs.
The second is that only those cross-coupled transistors are biased in the saturation region.
The transistor in the triode region exhibits low gain and low noise, while the transistor in the saturation region exhibits high gain and high noise [39]. In our proposed QVCO, MQ1 (MI1) and MQ2 (MI2) are quadratre coupling transistors and they do not need high gain. Therefore, the coupling transistors are all biased at deep triode region and their contributed noise is
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negligible.
The last is the improvement of loaded Q. The biases of cross-coupled transistors in a VCO are all in a saturation region to provide negative resistance. However, these transistors are pushed into a triode region by the large output swing of a resonator for part of a period.
The low output resistance of a transistor in a triode region decreases the loaded Q and hence depresses the phase noise performance. The coupling transistors are serves as current sources in this project. Even though they are not good current sources because they are biased in deep triode region. The improvement of the phase noise is similar or superior due to the absence of noise contributed from current source.
All the parameters are simulated by eldoRF and ADS2004, and the EM simulator (sonnet 9.52) is also used for post-simulation. The simulated results are shown and discussed in next section.
4.3 Simulation Results
All the simulations are based on the TSMC 0.18um CMOS technology. Fig. 4-6 shows that the proposed K band oscillator operating at 19.1-GHz, and the fundamental signal is suppressed about 45 dBc. In addition, the simulated tuning range of the VCO is 700-MHz and it is shown in Fig. 4-7. Fig. 4-8 shows the simulated phase noise, and the simulated result reveals that a phase noise of -112dBc/Hz is achieved in K band. Otherwise, the phase noise of the X band quadrature signal is also plotted, and it performs 6 dB lower than the K band. The core circuit of quadrature VCO and balanced doubler consume 10.92mW and 4.89mW, respectively. The power supply voltage is designed to be 1.5V for measurement consideration.
The buffer consumes 31.679mW and the spectrum output power is about -3.5dBm. Finally, the transient waveform of K band signal source and X band quadrature signal in time domain are shown in Fig. 4-9 and Fig. 4-10, respectively. Table 15 summarizes the performance of our proposed K band VCO.
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Fig. 4-6 The simulated result of output spectrum
Fig. 4-7 The simulated result of tuning range
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Fig. 4-8 The simulated phase noise of X band and K band signal
Fig. 4-9 The simulated transient result of K band signal source
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Fig. 4-10 The simulated transient result of X band quadrature signal
Fig. 4-11 Layout of the proposed K band VCO
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Specification Post Simulation
Process CMOS 0.18um
Supply Voltage(Volt) 1.5
Frequency Range(GHz) 18.8~19.5
Output Power(dBm) -3.21dBm
Tuning Range(MHz) 700 (3.655%)
Phase Noise(dBc/Hz)@1MHz -112
Tuning Senstivity(MHz/V) 350
FOM(dB) 185.63
Table 15 Performance summary of the proposed K band VCO
4.4 Comparisons
Process CMOS 0.18um CMOS 0.18um CMOS 0.18um
Supply Voltage(V) 1.8 1.8 1.5
Frequency
Range(GHz) 19.84~22.01 9.3~10.4 18.8~19.5 9.4~9.75 Output
Power(dBm) -6.83 N/A -3.21dBm N/A
Tuning
Range(MHz) 2170 1100 700 350
Phase Noise
(dBc/Hz) -111.67@1MHz -91@100kHz -112@1MHz -87.5@100kHz
-118@1MHz -93.5@100kHz
FOM(dB) 182.03 165 185.63 187.24
Core Circuit Power
Consumption(mW) 40.32 14.4 15.81
Table 16 Comparison with K band and X band VCO
Table 16 shows the comparison with K band and X band VCOs. In order to compare the performance with other recently proposed works in terms of center frequency, phase noise
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and power consumption, the figure-of-merit (FoM) characteristic is expressed as [40]:
⎥⎥ power consumption and L(λ) is the phase noise at the oscillation frequency. The low phase noise and low power consumption result in high FOM in this work, and the calculated FoM of each work are listed in Table 16.
4.5 Conclusions
In this future work, we simulated a K band frequency with X band CMOS QVCO. Low phase noise and high FoM is the main design goal in this K band VCO. The power supply is designed as 1.5V for measurement consideration, and the buffers operating at K band consume large power. The simulation results reveal that low power consumption (15.81mW) and low phase noise (-112 dBc/Hz @ 1-MHz) is accomplished in K band. However, some prototypes such as transformers still benefit the performance of a VCO [40]. These prototypes will be the feature study for us.
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