Chapter 2 SWITCHED DUAL-BAND LNA WITH FOUR GAIN MODES
2.5 Measurement Consideration and Results
2.5.2.2 Measurement Results
By the measurement setups illustrated above, the measured results are listed below. The RF and LO measurement was performed on-wafer. The biases were fed with bonding wires. A quadratue LO signal source at 2.62-GHz was used. This new sub-harmonic mixer consumes no dc power while there is no LO signal input. The buffer consumes 12.42mA dc current from 1.8V power supply. Unfortunately, the measured current indicates that the process condition now falls at the vicinity of SS-corner. Therefore, the following measured results are compared with the SS-corner simulation. As shown in Fig. 2-36, the measured RF and LO input return loss are -17.2 dB at 5.25-GHz and -18.0 dB at 2.62-GHz. The input return losses are well matched to system impedance in both RF and LO inputs. In this work, a high differential conversion power gain, 12.8 dB is achieved (see Fig. 2-37). As can be seen, the maximum differential conversion power gain is happened at the LO power of 4 dBm..
Fig. 2-38 shows the DSB noise figure against the IF frequency. The LO signal is fixed to 2.62GHz, and RF signal sweep from 5.25GHz to 5.32GHz. The IF frequency we choose is 10-MHz for system integration and cost consideration [1]. The DSB noise figure is 14 dB at 10-MHz.
Finally, Fig. 2-39 shows the input 3rd order intercept point (IIP3) of -1.8 dBm. The linearity of the sub-harmonic mixer is well performed especially the mixer achieves high conversion gain.
The port to port isolation is also taken into consideration in the proposed sub-harmonic mixer. The isolation of the fundamental LO signals (2.62-GHz) to RF port and IF port are higher than 40 dB and 31 dB respectively. The more important is the second harmonic of the LO signal (5.24-GHz), and it performs higher than 67 dB and 52 dB for RF port and IF port respectively.
44
Fig. 2-36 The simulated and measured RF and LO return loss
Fig. 2-37 The simulated and measured conversion power gain against the LO power
45
Fig. 2-38 The simulated and measured DSB noise figure
Fig. 2-39 The simulated and measured third order intercept point (IIP3)
46
Specification Measurement Post Simulation
(SS corner)
Supply Voltage(Volt) 1.8 1.8
LO Power(dBm) 4 4
RF Return Loss(dB) @5.25GHz -17.22 -14.9
LO Return Loss(dB) @2.62GHz -16.45 -7.39
2LO-to-RF Isolation(dB) >67 -65
Conversion Power Gain(dB) 12.8 13.8
IIP3(dBm) -1.8 -4
Noise Figure(dB) 14.0 14.7
Buffer Power Consumption(mW) 22.36 23.956
Table 7 Summary of the measured results and post-simulation in SS-corner
2.5.2.3 Comparison with Other Literatures
Three sub-harmonic mixers operating at 5.2GHz band are listed and compared with our work, and they are shown in Table 8. The proposed sub-harmonic mixer achieves high conversion gain and still remains high linearity by the switched Gm prototype and the PMOS active load. In addition, it consumes no dc power while there is no LO input. The noise figure at 10MHz is 14.0dB, and this noise drawback can be alleviated by a high gain LNA in front of this sub-harmonic mixer. Comparing with the listed literatures, the measured noise figure performs well.
47 Table 8 The summary of this work and comparison with other literatures
48
Chapter 3
K A B AND L NA U SING 0.18 μm CMOS
3.1 Introduction
The growing demand for wider bandwidth motivates integrated circuits to move toward higher frequencies. In the past, GaAs-based HEMT and HBT technology dominate most of the applications due to lossless substrate in these processes. But the more attractive process, CMOS, has resulted in a strong motivation to implement these high-frequency and high-performance RF systems. The loss of the Si-based substrate is a serious issue on building these high frequency circuits. For instance, the Si-based substrate caused the on-chip inductors or on-chip transmission lines to be loss and hence caused them to be low Q.
However, a high performance CMOS front-end for applications above 20GHz has been reported and the performance of these CMOS circuits show CMOS process has potential for building RF systems above 20GHz [34]~[37]. Although the SOI CMOS process has demonstrated excellent performance in LNA designs, the standard bulk CMOS process still attractive due to the cost and the integration consideration. Here we use the TSMC 0.18um CMOS technology to implement the K-band low noise amplifier. The technology offers polysilicon resistor, MIM capacitance, and six metallization layers. The substrate resistivity is 15~25Ω-cm [35]. To operate upper K-band, low loss inductors with small inductance and high self-resonance frequency are required. As shown in Fig. 3-1, to minimize the resistive loss, the transmission lines which are used as inductors are placed on the top most layer with 2um thickness. Ideally the wide transmission lines are preferred to lower resistive loss, but wide transmission lines lead to more substrate loss by parasitic capacitance. Here the width of
49
the transmission line is optimized to have higher quality factor. All the transmission lines are simulated by the EM simulator, sonnet 9.52, to consider the radiation loss and parasitic effects.
Fig. 3-1 Using top metal as the transmission line
3.2 System Application
Fig. 3-2 Simplified block diagram of a 24-GHz Receiver
Fig. 3-2 shows the simplified block diagram of a typical receiver. In this architecture, the RF amplification and down conversion stage are the most challenging to implement in CMOS.
In this work, a 24-GHz LNA is designed and validated by the standard 0.18um CMOS process.
A system application, LMDS, is introduced in this section and Table 9 summarizes some
50
features of this system [38]. LMDS is a broadband wireless point-to-point or point-to-multipoint communication system operating above 20 GHz (depending on country of licensing) that can be used to provide digital two-way voice, data, Internet, and video services.
This system provides network service to area with poor or nonexistent wired infrastructure.
Comparing to wire-line, lower infrastructure costs are required by LMDS.
LMDS point-to-point wireless applications include connections between cell phone towers and central offices, or trunk connections between metropolitan buildings at data rates between 150 Mbps and 620 Mbps over a range of 2 km. Point-to-multipoint products can transmit packets at 150 Mbps omnidirectionally over a distance of 1 to 3 km. LMDS operates in 24 GHz, 28 GHz, and 39 GHz frequencies achieving data rates of 100Mbps with 45 Mbps being more typical rates
System LMDS
Frequency Range 24GHz 28GHz 39GHz
Application Point-to-point Point-to-multipoint
Distance 2km 1~3km
Data Rate 150~620 Mbps 150 Mbps
Modulation Method TDMA FDMA CDMA
Target Market Large & Medium Enterprise
Table 9 Summary of the LMDS system
3.3 Circuit Design
There are several prototypes to construct the 24GHz LNA. Since the transistor’s gain is not sufficient in such high frequency, three cascaded common source stages are applied to build the proposed LNA. The choices of the MOSFET in each stage dominate the performance of the designed LNA. Taking the transistor into simulator and analyzing the major characteristic of the transistor is the first step in our design flow. To connect each stage by the transmission lines bring the problem of inter-stage matching networks. And the
51
inter-stage matching networks should be designed carefully to have maximum power transfer.
Properly choosing the Γ locating between constant NF circle and constant available gain s circle, and these circles help us to analyze the behavior and characteristic of the LNA.
3.3.1 Proper Device Size Choice
Fig. 3-3 Simulation results of f versus VGS t
Fig. 3-4 Simulation results of fmax versus VGS
52
The TSMC 0.18um MOSFET have been demonstrated with the cut-off frequency and the maximum oscillation frequency of 70GHz and 58GHz, respectively [34]. We take the MOSFET with width 35um and length 0.18um for simulation. The modified MOSFET model for simulation is based on the BSIMv3 SPICE model, with some passive components added to take into account of the parasitic effects in the microwave. The simulated results for f t and fmax versus VGS are shown in Fig. 3-3 and Fig. 3-4, respectively. And it confirms our quote from [34].
The first stage of the proposed LNA should be low noise to suppress the noise figure of the LNA. Properly choosing the transistor size and the source degeneration inductor makes the minimum noise and available gain to simultaneously attain. Finally, constructing each common source stage step by step, we can illustrate the designed LNA perform gain and noise figure as expected.
Fig. 3-5 Simulation of IDS, NFmin , and Gm versus VGS and VDS
To have insight into the characteristic of the MOSFET, the transistor has been simulated the NFmin, Gm, and current consumption against both VDS and VGS. As shown in Fig. 3-5, the length and width of the selected transistor is 0.18um and 80um, respectively. To perform low
53
power consumption, the VDS of each stage are fixed to 1V. We choose VGS=0.7V to get better minimal noise figure. As indicated in Fig. 3-5, the selected transistor performs current consumption of 4mA form 1V power supply, minimal noise figure of 1.67155dB, and transconductance of 30.1814mA/V.
3.3.2 Stability Circle
The stability of an amplifier is a very important consideration in a design and can be determined by the S parameter, the matching networks, and the terminations. Input and output stability circle is plotted to determine the stable region. The input and output stability circles can be plotted on Smith chart by the S-parameter of a selected transistor at one frequency point:
(Output Stability Circle)
| |
(Input Stability Circle)
| |
(3.1) and (3.2) show the radius and center of the output stability circle. Meanwhile, (3.3) and (3.4) shows the radius and center of the input stability circle. Applying the simulated S-parameters into (3.1) ~ (3.5), we can plot the input and output stability circles. Fig. 3-6 and Fig. 3-7 show the plotted input and output stability circles at 24-GHz. We can observe that the selected MOSFET at fixed bias condition exhibits potentially unstable. If there are some variations due to CMOS process, it causes the selected Γ or s Γ to be inside the unstable L
54
region. Hence, we need to use the source degeneration to stabilize the MOSEFET.
Fig. 3-6 Plot the input stability circle on smith chart without source degeneration
Fig. 3-7 Plot the output stability circle on smith chart without source degeneration
There is also one notice that simultaneously conjugated match implies that the two port device is unconditional stable. The simultaneously conjugated match causes the device to perform maximum available gain, and the input VSWR will be 1. However, input return loss
55
is often sacrificed to obtain noise matching. Hence, the source degeneration here not only keeps the MOSFET to be unconditional stable, but also makes the input impedance and noise figure match simultaneously.
Fig. 3-8 Plot the input stability circle on smith chart with source inductor of 0.1nH
Fig. 3-9 Plot the output stability circle on smith chart with source inductor of 0.1nH
In addition, the additional source inductance doesn’t seriously degrade the noise
56
performance. The size of the source degeneration inductor must be selected carefully, since increasing the inductance reduces amplifier gain. Here a source degeneration inductor of 0.1nH is selected, and the stability circle is plotted in Fig. 3-8 and Fig. 3-9. The MOSFET is unconditional stable now.
3.3.3 Available Gain Circle
The power gain of the proposed LNA can be estimated by plotting the constant available gain circle. (3.6) and (3.7) indicate the center and radius of the available gain circle, respectively. The g , K , and a C1 in (3.6) and (3.7) are listed in (3.9), (3.10), and (3.11) [1].
The C and a r are both functions of a
[ ]
S and Γ . By determining the needed available s gain, Γ must locate at the constant available gain circle. The power gain design goal of our s proposed LNA is about 15 dB, this means 6 dB power gain is required for each common source stage. The selected source inductor is 0.1nH, this produces the power gain about 6.95 dB for maximum power transfer. Fig. 3-10 shows the constant available gain circles from 6.953 dB to 3.953 dB.57
Fig. 3-10 Plot the available power gain circle on smith chart with source inductor of 0.1nH
3.3.4 Noise Circle
The noise figure is a major performance measure in a low noise amplifier design. If the MOSFET is selected and biased at a fixed voltage, the noise figure performance is dominated by the selection of Γ . Selection of s Γ equal to s Γ always sacrifices the available power opt gain and input VSWR. Constant noise figure circles are needed to recognize the trade off between gain and noise. Eq. (3.12) shows the noise figure indication, and it depends on Fmin,
r and n Γ . These quantities are known as the noise parameters and are given by the opt manufacturer of the transistor or can be determined experimentally. Hence, giving a constant noise figure, F , (3.12) is a function of i Γ . (3.12) can be rewritten to a spherical form of s (3.13) and N also can be identified by a given i F . Therefore, a constant noise figure circle i can be plotted on Γ plane. The center and radius of a constant noise figure circle can be s determined obviously and they are listed in (3.15) and (3.16) respectively. Fig. 3-11 shows the constant noise figure circles from Fminof 1.508dB to NF of 2.108dB.
58
Fig. 3-11 Plot the constant noise figure circle on smith chart with source inductor of 0.1nH
Using the constant circles illustrated above and plotting these circles on a Γ plane, a s clear inspection can be obtained. As shown in Fig. 3-12, Γ is selected for input VSWR s consideration. If the selected Γ equal to s Γ , the input VSWR must be poor. opt
59
Fig. 3-12 Plot constant GA, NF circles and input stability circle on Γ plane s
Otherwise, if the Γ is selected for maximum power transfer, the noise figure s performance must be sacrificed. Hence, using source degeneration inductor makes these tradeoffs possible. The single stage performance of the selected Γ is shown in Table 10. s The output matching network of each stage is designed for maximum power transfer, that is
* out L =Γ
Γ .
Noise Figure (dB) with source impedance at marker GammaS
Source impedance at marker
GammaS
Optimal load impedance for power transfer when source impedance at marker GammaS is presented to input
Transducer power gain (dB) when these source and load impedances are used
2.154 12.548+j37.103 20.701+j53.987 6.878
Table 10 Single stage performance of the selected Γ s
Once the Γ is selected, the input matching network can be obtained. Fig. 3-13 shows s the input matching network for selected Γ . The matching network is accomplished by the s
60
Ansoft Designer SV. First, we need to assume all the lump components to be idea. After finding out all the desired values for matching network, the practical components are implemented and simulated to fit them.
Fig. 3-13 Input matching network by the selected Γ s
Fig. 3-14 Matching behavior form 50Ω to Γ s
Fig. 3-14 shows the matching behavior for the consideration of bias and dc block, and the passive components are ideal. By the number of steps denoted on graphic, clearly the 50Ω
61
source impedance is shifted to the desired Γ . s
The matching network has to consider the parasitic pad capacitance and any connected lines. For the size of 100umΧ100um,the pad capacitance is estimated of 60fF between metal 6 and metal 1 [35]. All the inductors in such high frequency must be simulated by the EM simulator, and each inductor in the circuits must be separated at least 50um to reduce unwanted coupling effects. The series connected inductors in the input matching network are added for keeping inductors 50um away [36]. The transmission lines as well as inductors are implemented on the top metal layer made of 2-um-think AlCu.
The capacitors in the designed LNA all are shield type. For circuits operating upper than 20-GHz, the shield capacitor is expected to isolate unwanted substrate noise. The equivalent RLC model for the shield and w/o shield capacitor is shown in Fig. 3-15 and Fig. 3-16, respectively. In these two equivalent circuits, the inter-metal dielectric Cmim is the main element of the capacitor. Rtop and Ltop are the parasites existing in the electrode connected to port1, and Rbot and Lbot are the parasites existing in the electrode connected to port2. Cox of MIM without shield represents the capacitance between port2 bottom plate metal and substrate. Csub and Rsub are parasitic that presents the substrate capacitance and resistance.
Cox of MIM with shield represents the capacitance between port2 bottom metal plate to metal shield. It is obvious that the MIM capacitor with metal4 shield has higher quality factor than the one without metal shield. The shield type capacitor also set the substrate noise apart that higher noise performance can be achieved. Fig. 3-17 and Fig. 3-18 show the geometric inspection of the MIM capacitor w/i and w/o shield respectively. Both of these capacitors are formed with metal6, via56, CTM5 and metal5. But one more shield plate, metal4, is below metal5 to construct of shield capacitor.
62
Fig. 3-15 The equivalent RLC circuit for MIM w/i shield structure
Fig. 3-16 The equivalent RLC circuit for MIM w/o shield structure
Fig. 3-17 3-D view for MIM with metal4 shield
63
Fig. 3-18 3-D view for MIM without metal4 shield
3.3.5 Inter Stage Matching Network
Fig. 3-19 Inter stage matching networks are needed to design
After accomplishing the input matching network for selected Γ , the output matching s network of 1st stage and input matching network of 2nd stage must be designed simultaneously.
Achieving maximum power transfer is the design goal of inter stage matching networks. This means that the output matching network of 1st stage must be complex conjugated with the input matching network of 2nd stage. Fig. 3-19 shows the inter stage networks between each stages. The matching networks should be designed to suit the bias condition and the uncomplicated consideration. The compact matching network reduces the resistive loss produced by the passive components, and achieves higher gain and lower noise contribution.
By this reason, the inter stage system impedance is no longer 50Ω. The complex conjugated impedances are required for inter stage matching networks. In Fig. 3-20, ‘A’ and ‘B’ are so
64
called system impedances in the inter stage matching network. The impedance “A” and “B”
are fixed to 10.57+j28.3. The input matching network of 2nd stage is designed first.
Fig. 3-20 The complex conjugated impedances are required in the proposed LNA
Fig. 3-21 The matching behavior and circuits from inter stage matching impedance (10.57+j28.3) to the Γ s2
Fig. 3-21 shows the matching behavior on Smith chart. Only a transmission line performing an inductivity of 60pH is required, and this short line indeed reduces the parasitic loss. The output matching network of 1st stage acts as a high pass filter at the drain of the MOSFET, and it also suitable for bias. As shown in Fig. 3-22, an inductor of 164pH and a capacitor of 570fF are required to construct the L-type high pass filter. The inductor and capacitor must be selected in a realizable scale and also designed for a compact layout.
65
Fig. 3-22 The matching behavior and circuits from conjugated inter stage matching impedance (10.57-j28.3) to the ΓL2
The inter-stage between 1st and 2nd stage now had been completed, and the design procedure of the following stages is also identical with this procedure. Because the selected Γ is a little different from the 1s st stage, the 2nd stage output L-type matching network is different from the 1st stage output matching network.
Fig. 3-23 The matching behavior and circuits from inter stage matching impedance (10.57+j28.3) to the Γ s3
66
Fig. 3-23~Fig. 3-26 show the matching behavior on smith chart and the corresponding matching networks. Table 11 lists the input or output reflection coefficient used in each stage.
Finally, the structure of the 24-GHz LNA is presented in Fig. 3-27. The simulation results with ideal passive components and on-chip one are discussed in the next section.
Finally, the structure of the 24-GHz LNA is presented in Fig. 3-27. The simulation results with ideal passive components and on-chip one are discussed in the next section.