Chapter 3 KA BAND LNA USING 0.18μm CMOS
3.3 Circuit Design
3.3.4 Noise Circle
The noise figure is a major performance measure in a low noise amplifier design. If the MOSFET is selected and biased at a fixed voltage, the noise figure performance is dominated by the selection of Γ . Selection of s Γ equal to s Γ always sacrifices the available power opt gain and input VSWR. Constant noise figure circles are needed to recognize the trade off between gain and noise. Eq. (3.12) shows the noise figure indication, and it depends on Fmin,
r and n Γ . These quantities are known as the noise parameters and are given by the opt manufacturer of the transistor or can be determined experimentally. Hence, giving a constant noise figure, F , (3.12) is a function of i Γ . (3.12) can be rewritten to a spherical form of s (3.13) and N also can be identified by a given i F . Therefore, a constant noise figure circle i can be plotted on Γ plane. The center and radius of a constant noise figure circle can be s determined obviously and they are listed in (3.15) and (3.16) respectively. Fig. 3-11 shows the constant noise figure circles from Fminof 1.508dB to NF of 2.108dB.
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Fig. 3-11 Plot the constant noise figure circle on smith chart with source inductor of 0.1nH
Using the constant circles illustrated above and plotting these circles on a Γ plane, a s clear inspection can be obtained. As shown in Fig. 3-12, Γ is selected for input VSWR s consideration. If the selected Γ equal to s Γ , the input VSWR must be poor. opt
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Fig. 3-12 Plot constant GA, NF circles and input stability circle on Γ plane s
Otherwise, if the Γ is selected for maximum power transfer, the noise figure s performance must be sacrificed. Hence, using source degeneration inductor makes these tradeoffs possible. The single stage performance of the selected Γ is shown in Table 10. s The output matching network of each stage is designed for maximum power transfer, that is
* out L =Γ
Γ .
Noise Figure (dB) with source impedance at marker GammaS
Source impedance at marker
GammaS
Optimal load impedance for power transfer when source impedance at marker GammaS is presented to input
Transducer power gain (dB) when these source and load impedances are used
2.154 12.548+j37.103 20.701+j53.987 6.878
Table 10 Single stage performance of the selected Γ s
Once the Γ is selected, the input matching network can be obtained. Fig. 3-13 shows s the input matching network for selected Γ . The matching network is accomplished by the s
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Ansoft Designer SV. First, we need to assume all the lump components to be idea. After finding out all the desired values for matching network, the practical components are implemented and simulated to fit them.
Fig. 3-13 Input matching network by the selected Γ s
Fig. 3-14 Matching behavior form 50Ω to Γ s
Fig. 3-14 shows the matching behavior for the consideration of bias and dc block, and the passive components are ideal. By the number of steps denoted on graphic, clearly the 50Ω
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source impedance is shifted to the desired Γ . s
The matching network has to consider the parasitic pad capacitance and any connected lines. For the size of 100umΧ100um,the pad capacitance is estimated of 60fF between metal 6 and metal 1 [35]. All the inductors in such high frequency must be simulated by the EM simulator, and each inductor in the circuits must be separated at least 50um to reduce unwanted coupling effects. The series connected inductors in the input matching network are added for keeping inductors 50um away [36]. The transmission lines as well as inductors are implemented on the top metal layer made of 2-um-think AlCu.
The capacitors in the designed LNA all are shield type. For circuits operating upper than 20-GHz, the shield capacitor is expected to isolate unwanted substrate noise. The equivalent RLC model for the shield and w/o shield capacitor is shown in Fig. 3-15 and Fig. 3-16, respectively. In these two equivalent circuits, the inter-metal dielectric Cmim is the main element of the capacitor. Rtop and Ltop are the parasites existing in the electrode connected to port1, and Rbot and Lbot are the parasites existing in the electrode connected to port2. Cox of MIM without shield represents the capacitance between port2 bottom plate metal and substrate. Csub and Rsub are parasitic that presents the substrate capacitance and resistance.
Cox of MIM with shield represents the capacitance between port2 bottom metal plate to metal shield. It is obvious that the MIM capacitor with metal4 shield has higher quality factor than the one without metal shield. The shield type capacitor also set the substrate noise apart that higher noise performance can be achieved. Fig. 3-17 and Fig. 3-18 show the geometric inspection of the MIM capacitor w/i and w/o shield respectively. Both of these capacitors are formed with metal6, via56, CTM5 and metal5. But one more shield plate, metal4, is below metal5 to construct of shield capacitor.
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Fig. 3-15 The equivalent RLC circuit for MIM w/i shield structure
Fig. 3-16 The equivalent RLC circuit for MIM w/o shield structure
Fig. 3-17 3-D view for MIM with metal4 shield
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Fig. 3-18 3-D view for MIM without metal4 shield
3.3.5 Inter Stage Matching Network
Fig. 3-19 Inter stage matching networks are needed to design
After accomplishing the input matching network for selected Γ , the output matching s network of 1st stage and input matching network of 2nd stage must be designed simultaneously.
Achieving maximum power transfer is the design goal of inter stage matching networks. This means that the output matching network of 1st stage must be complex conjugated with the input matching network of 2nd stage. Fig. 3-19 shows the inter stage networks between each stages. The matching networks should be designed to suit the bias condition and the uncomplicated consideration. The compact matching network reduces the resistive loss produced by the passive components, and achieves higher gain and lower noise contribution.
By this reason, the inter stage system impedance is no longer 50Ω. The complex conjugated impedances are required for inter stage matching networks. In Fig. 3-20, ‘A’ and ‘B’ are so
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called system impedances in the inter stage matching network. The impedance “A” and “B”
are fixed to 10.57+j28.3. The input matching network of 2nd stage is designed first.
Fig. 3-20 The complex conjugated impedances are required in the proposed LNA
Fig. 3-21 The matching behavior and circuits from inter stage matching impedance (10.57+j28.3) to the Γ s2
Fig. 3-21 shows the matching behavior on Smith chart. Only a transmission line performing an inductivity of 60pH is required, and this short line indeed reduces the parasitic loss. The output matching network of 1st stage acts as a high pass filter at the drain of the MOSFET, and it also suitable for bias. As shown in Fig. 3-22, an inductor of 164pH and a capacitor of 570fF are required to construct the L-type high pass filter. The inductor and capacitor must be selected in a realizable scale and also designed for a compact layout.
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Fig. 3-22 The matching behavior and circuits from conjugated inter stage matching impedance (10.57-j28.3) to the ΓL2
The inter-stage between 1st and 2nd stage now had been completed, and the design procedure of the following stages is also identical with this procedure. Because the selected Γ is a little different from the 1s st stage, the 2nd stage output L-type matching network is different from the 1st stage output matching network.
Fig. 3-23 The matching behavior and circuits from inter stage matching impedance (10.57+j28.3) to the Γ s3
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Fig. 3-23~Fig. 3-26 show the matching behavior on smith chart and the corresponding matching networks. Table 11 lists the input or output reflection coefficient used in each stage.
Finally, the structure of the 24-GHz LNA is presented in Fig. 3-27. The simulation results with ideal passive components and on-chip one are discussed in the next section.
Fig. 3-24 The matching behavior and circuits from inter stage matching impedance (10.57+j28.3) to the Γ s3
Fig. 3-25 Output matching network by the selected Γ L3
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Fig. 3-26 Matching behavior form 50Ω to Γ L3
ΓS1 12.548+j37.103 ΓL1 20.701+j53.987 ΓS2 10.574+j37.688 ΓL2 15.828+j51.017 ΓS3 10.574+j37.688 ΓL3 15.828+j51.017
Table 11 List of each complex reflection coefficient for the designed LNA
Fig. 3-27 The proposed 24-GHz LNA
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3.3.6 The simulation results with ideal and on-chip inductors
The designed architecture above is simulated by the simulator ADS2004A, and the transmission lines as well as inductors are simulated by the EM simulator sonnet9.52. The ideal lump components are used, and the results are so called pre-simulation. Each transmission lines are simulated and the ‘sNp’ files are extracted from the simulation results.
The ideal lump components are replaced with the ‘sNp’ files, and the simulation results are so called post-simulation. Fig. 3-28~Fig. 3-34 show the simulation results of both pre-simulation and post-simulation. The S-parameter of the pre-simulation matches our design condition illustrated above. But the post-simulation shows deviation especially both the T-junctions and the RF pads are used as simulation components. The 24-GHz LNA was designed first in our group, and the EM simulator is first applied to the design. Therefore, the 24-GHz LNA is treated as a test key for further simulation and design in the future. The post-simulation doesn’t meet our desired standards of operating in 24-GHz, however, the confirmation of simulation and measurement results is the other design goal in this project. The simulated data in Fig. 3-28 ~ Fig. 3-31 revels that the best operation point shifts to 27-GHz. Both the input and output return losses of the post-simulation are higher than 10dB, and the power gain is about 13dB. Because the LNA is constructed of three stages, the reverse isolation performs well above 30dB. The noise figure exhibits about 4.5dB. With this simulated low noise figure, this designed LNA has competition with the GaAs-based HEMT and HBT technology. The simulated 1-dB compression point (P1dB) and 3rd order intercept point (IIP3) shows well linearity, and they are -12.8dBm and -4dBm, respectively. The post-simulation results are summarized in Table 12.
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Fig. 3-28 The S11 simulated results of the proposed LNA
Fig. 3-29 The S21 simulated results of the proposed LNA
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Fig. 3-30 The S22 simulated results of the proposed LNA
Fig. 3-31 The S12 simulated results of the proposed LNA
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Fig. 3-32 The Noise Figure simulated results of the proposed LNA
Fig. 3-33 The P1dB simulated results of the proposed LNA
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Fig. 3-34 The IIP3 simulated results of the proposed LNA
(Pre-simulation) (Post-simulation) Technology CMOS 0.18um CMOS 0.18um Center frequency 24GHz 27GHz
Vdd 1V 1V
S21 22.35dB 13.005dB P1dB -18.6dBm -12.8dBm IIP3 -11dBm -4dBm S11/S22(dB) -16.21/-17.23 -10.38/-10.50 power dispassion 11.85mW 11.85mW
NF 2.94dB 4.5dB
Table 12 The pre-simulation and post simulation summary of the proposed LNA
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3.4 Measurement Consideration and Results
3.4.1 Measurement Consideration
The 24-GHz LNA is designed for on-wafer measurement and prepared to test by CIC and Nation Center University. The layout follows the rules of CIC for testing. By the layout shown in Fig. 3-35, the LNA required two 3-pin DC probes for upper and lower side. Tow RF GSG probes are also required for RF signal, and they are posited left and right side. Fig. 3-36 is the fabricated die photo of the proposed 24-GHz LNA. The probing setup for on-wafer measurement is shown in Fig. 3-37.
The environment setups for each parameter are shown in Fig. 3-38 (a~c). The measurement instruments including network analyzer, noise analyzer are provided by CIC, and the linearity parameters are measured in Nation Center University.
Fig. 3-35 The layout view of the proposed 24-GHz LNA
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Fig. 3-36 The micrographic of the proposed 24-GHz LNA
Fig. 3-37 Probing setup for on-wafer measurement
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(a)
(b)
(c)
Fig. 3-38 Measurement setups of (a) S-parameter (b) noise figure (c) IIP3 and P1dB
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3.4.2
Measurement Results and Discussion
The operating frequency of the post-simulation is about 27-GHz, however, the measured results shift to about 32-GHz. To show the deviation between the post-simulation and measured results, each parameter is plotted on the same figure. The calibration of the 2-port network analyzer is difficult for frequency above 30-GHz, therefore, the measured curve is slightly unsettled above 30-GHz. As shown in Fig. 3-39~ Fig. 3-44, the measured S-parameter shows that the 3-stage LNA achieves high power gain of 12.08dB, and a 5.325dB noise figure is accomplished at 32-GHz. The input and output return losses also shifts from 27-GHz to 32-GHz. At 32-GHz, the measured S11 and S22 are -6.3dB and -20.67dB, respectively.
Fig. 3-39 Post-simulation and measurement of S11
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Fig. 3-40 Post-simulation and measurement of S21
Fig. 3-41 Post-simulation and measurement of S22
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Fig. 3-42 Post-simulation and measurement of S12
Fig. 3-43 Post-simulation and measurement of IIP3
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Fig. 3-44 Post-simulation and measurement of Noise Figure
(Measurement) (Post-simulation) Technology 0.18um CMOS 0.18um CMOS
Center frequency 32GHz 27GHz
Vdd 1V 1V
S21 12.08dB 13.005dB
P1dB -11dBm -12.8dBm
IIP3 0.9dBm -4dBm
S11/S22(dB) -6.3/-20.67 -10.38/-10.50 power dispassion 15.58mW 11.85mW
NF 5.325dB 4.5dB
Table 13 Summary of the post-simulation and measurement
The post-simulation results are completed by simulating all transmission lines including
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all T-junction. However, the coupling form line to line is difficult to take into account. The main reason is the restriction of EM simulator (sonnet9.52). Each port of the transmission line must be at the boundary of a rectangle, and this restriction confines the dimension of simulation. This coupling will cause parasitic capacitance and mutual inductance and hence the measured results are different from the post-simulation.
3.4.3 Comparison with Other Literatures
This Work
32GHz 21.8GHz 23.7GHz 24GHz 20GHz
Vdd 1V 1.5V 1.8V 1V 1.5V
S21 12.08dB 15dB 12.86dB 13.1dB 5.8dB S11/S22(dB) -6.3/-20.67 --/-- -11/-22 -15/-20 -20/-20
power dispassion
15.58mW 24mW 54mW 14mW 10mW
NF 5.325dB 6dB 5.6dB 3.9dB 6.4dB
Table 14 Measured results and comparison with other literatures
The comparison with recent published literatures is listed in Table 14. By CMOS 0.18um technology, this measured LNA with highest operating frequency ever reported performs 12.08 dB power gain and consumes 15.58mW from 1V power supply. Comparison shows this work consumes less power and has competition with other works. The well performed noise figure shows the noise matching is realized, however, there are still some improvements
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required for this work. This work also demonstrates that 0.18um CMOS process has potential to implement above 30-GHz LNA. In our feature work, a better device size choice and source degeneration size selection is the main target for above 30-GHz. In addition, different EM simulators are requested to the feature works.
3.5 Conclusion
Recent works have shown CMOS as a promising means for building RF circuits in the low-gigahertz range. However, a high-performance CMOS front-end for applications above 20GHz has been reported and the performance of these CMOS circuits show CMOS process has potential for building RF systems above 20GHz.[34]~[36]. In this work, a 24-GHz low noise amplifier is designed, and the measured results shows the LNA achieves 12 dB gain at 30-GHz. By the CMOS 0.18um technology, this work presents the highest operating frequency compared with the reported literatures. The best matching point of the measured input return loss does not locate at 30-GHz, however it achieves -21 dB at 35-GHz. This deviation not only causes the gain lower than the desired one but also influences the noise figure performance. The frequency shift in this project is about 3-GHz form 27-GHz to 30-GHz. This phenomenon is observed in our simulation. The T-junction and the RF-pad are the issue in the EM simulation. The transmission lines as well as inductors in this project are simulated precisely. But the T-junction does not take into account. If the T-junctions are simulated, the frequency shift phenomenon appears. The RF pad and the input matching network are critical issues to the noise figure performance. The realistic RF pad and passive components contribute about 1.5 dB noise figure than the ideal passive components. These two problems are needed to overcome, and different EM simulators will be necessary to the high frequency simulation in the future for coupling affection.
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Chapter 4
K B AND F REQUENCY S OURCE W ITH X B AND L OW P HASE N OISE Q UADRATURE C MOS V CO
4.1 Introduction
Using standard CMOS process to implement millimeter-wave frequency sources had garnered more and more attention and became a tendency by the reason of low cost and high integration ability with other analog and digital circuits. The on-chip inductors with low-Q are the main defect for Si substrate and influence the phase noise directly. However, many recently published literatures of Si-based VCOs had demonstrated their competition with the GaAs process [39]~[44].
Above X band, a CMOS VCO with high performances is difficult to design. With a little increment of power consumption, frequency doubling scheme is the reasonable and effective approach to improving performance. There are several reasons to use a lower frequency oscillator with a frequency doubler instead of an oscillator operating at a higher frequency.
Generally, the phase noise of the latter is higher than that of the former. Furthermore, the usage of a frequency doubler mitigates the design difficulty of a high-frequency phase-locked loop (PLL). In general, a VCO has an oscillation frequency up to ~ fmax and a frequency divider operates approximately up to 1/4~1/2 of fT. It is very difficult to increase the operating frequency of a frequency divider up to the output of a high-frequency VCO.
A pair of differential signals of 2 f× 0 can be realized by a balanced doubling method.
To get a high-quality signal of a frequency doubler, accurate quadrature signals with low phase noises are required. A simple method to obtain accurate quadrature signals with low
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phase noises is to couple two symmetric LC-tank VCOs [41]. Several quadrature VCOs had been implemented and demonstrated in the X-band [39]~[44]. Hence, a K band CMOS frequency source with X band low phase noise quadrature VCO will be presented.
4.2 Circuit Design
4.2.1 Quadrature Signal
in+
in-out+
out-in+
in-out+
out-0° 90°
180° 270°
(a) (b) Fig. 4-1 Quadrature VCO architecture (a) connection of blocks (b) Transfer characteristic
Fig. 4-1 (a)(b) show the quadrature VCO architecture. The quadrature phase VCO comprises two mutually-coupled fixed frequency LC-oscillators. Frequency tuning is achieved by varying the coupling coefficient (β) between two oscillators. Oscillation frequency is adjusted along with loop gain compensation (α). This mechanism ensures that current injected into LC tank remains constant regardless of frequency tuning. Thus AM-to-PM phase noise conversion can be suppressed [41]
Consider two fixed-frequency LC oscillators whose outputs are coupled to their inputs with the coupling coefficients β and -β, as shown in Fig. 4-1. Each oscillator is modeled by a
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positive feedback loop with open loop gain H(jω). In steady-state, and if the two oscillators synchronize to a single oscillation frequency, ω, the output of each oscillator must satisfy the following equations:
This proves that the oscillatory system of Fig. 4-1 indeed provides quadrature outputs X and Y. By substituting equation (4.3) into equation (4.2), equation (4.4) can be derived.
1 ) ( )
(α ± jβ H jω = (4.4)
Equation (4.4) governs the frequency transfer characteristic of the quadrature phase VCO.
As the close loop phase response of these oscillators is varied by adjusting α/β, VCO's output frequency can be changed accordingly.
4.2.2 Frequency Doubler
4.2.2.1 Harmonics of Quadrature Signals
A VCO exhibits a strong nonlinear effect by the reason of the large output swing in the resonator. Since the nonlinear effect is related to many different physical phenomena, it cannot be modeled easily [39]. The output of a VCO now is modeled simply as a polynomial
...
where the A ’s are the harmonic coefficients and X is the input signal. If X is substituted by n )
If the four quadrature signals with the different phases of a quadrature VCO are inserted into
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(4.6), and fundamental frequency components are canceled out by adding two output signals with an input phase difference of 180°. A frequency-doubled differential signals are obtained and it follows:
.... The results show that a set of quadrature signals can create a pair of differential output with doubled-frequency, 2 f× . 0
4.2.2.2 Pinch-off Clipping
Fig. 4-2 Output signal of a pinchoff clipper derived by an input sinusoidal signal with low dc bias.
The device nonlinearity of a negative conductance cell mainly influences harmonics.
Since a MOSFET has high linearity and low fT, the harmonics of a MOS VCO are too small
Since a MOSFET has high linearity and low fT, the harmonics of a MOS VCO are too small