Current Equations of Thin-Film Transistors

Chapter 2 General Background and Literatures Review

2.7 Current Equations of Thin-Film Transistors

2.7-1 Drain Current Equations in Linear and Saturation Regions

In this section, we formulate a general drain current for thin-film transistor by using gradual channel approximation (GCA) model [93], which the variation of the electrical field along the channel is much less than that along the corresponding variation perpendicular to channel. Hence, the inversion charges density (Q ) could be simplified to the 1-D form of _inv Possion’s equation, as shown in Fig. 2-17 [93]. The current-voltage characteristic of the thin-film transistor could be calculated by estimating the elemental resistance dR and the elemental segment dy of the conducting channel given by

( )

, where W is the channel width and μ_EF is the field-effect mobility. And then, integrating Eq.

(2-2) from source (V=0 at y=0) to drain (V=VDS at y=L), the drain current could be expressed as

Following, we use the charge-sheet approximation model [94], which assumes that the inversion charges (Q ) are located at the silicon surface as a sheet of charges with no _inv potential dropping or band bending across the inversion layer, to derive drain current as

(

)

⁽

⁾

= − = − − − − + +

inv S dep ins GS fb B Si B B

Q Q Q C V V ψ V ε qN ψ V (2-4)

, where Q is the total surface charge density, _S Q_dep is the depletion charge density, V is _fb

the flat band voltage, the surface potential ψ_S is pinned at ψS =²ψB+V y

( )

, Cins is the gate capacitance density of insulator layer, ε_Si is the dielectric constant of silicon, and N is the _B effective channel dpoant in active channel of the thin-film transistor. Substituting Eq. (2-4) into Eq. (2-3) and carrying out the integration, the drain current (I_DS) could be presented by

( )

, where the body-effect coefficient m and the threshold voltage V_TH are 1 / 4

Substituting Eq. (2-7) into Eq. (2-5), the saturation current I_{DS sat}_, could be written as

(

)

μ L for saturation operation, respectively. (2-10)

2.7-2 Drain Current Equations in Subthreshold Region

To derive the subthreshold current, we start at solving Poisson’s equation in the surface region of semiconductor, whose detail band diagram and potential of p-type silicon are summarized in Fig. 2-18 [93]. The Poisson’s equation in this band diagram could be

re-written as

In substhreshold operation, we only consider the inversion charge density (Q ) in channel _inv region, and the last significant terms of Eq. (2-13) could be re-written as

( )

Substituting Q of Eq. (2-14) into Eq. (2-3), and carrying out the integration, the drain _inv current in the subthreshold region (I_{DS SUB}_, ) could be presented by

2 2

2.7-3 Drain Current Equations of Organic Thin-Film Transistors

Most organic thin-film transistors operate in the accumulation region, where the gate voltage is polarized positively (negatively) versus the n-type (p-type) substrate. Because organic thin-film transistor operates in accumulation region, we only take account in the

accumulation charges density (Q_acc) and the free carrier density (Q ) in organic channel layer, ₀

accounted as the drain influence. Because the organic thin-film transistor works in accumulation mode, QS

( )

y and Q , the total charges in channel, have identical sign ₀ neglecting the ohmic drop in channel. Hence, the drain current in linear region (in V_DS <V_GS) could be obtained from gradual channel approximation (GCA) model

( )

However, when V_DS >V_GS, the accumulation layer near drain changes to a depletion layer, as shown in Fig. 2-19 [95]. In depletion region, there is no free carrier at semiconductor/insulator interface. Thus, the integrating term of free carriers Q in Eq. (2-16) ₀ should be modified as

0 0 s

( )

Q =qn ⎡⎣d −W y ⎤⎦ (2-20)

, where ^{W y}

( )

is the depletion width near the drain region. And, the depletion width could be solved by the voltage drop equation as

( ) ( )

( )

Hence, substituting Eq. (2-22) and Eq. (2-20) into Eq. (2-3), and the drain current in saturation region (V_DS >V_GS) could be expressed as

( )

Because the organic thin-film transistor has a thin semiconductor layer, C_Semi >>C_ins, where

CSemi is the depletion capacitance density of ^Semi ds

This formula is the saturation drain current of the organic thin-film transistor.

TFT-Array Substrate

Fig. 2-1. Cross-sectional view of a unit pixel in active-matrix liquid crystal display (AMLCD) [26].

Scan Driver, (Gate Addressing) Nrow

Fig. 2-2. The equivalent circuitry for the addressing matrix of an AMLCD [27].

Fig. 2-3. Schematic diagram of Weimer’s CdS TFT with top-gate staggered structure [28].

Fig. 2-4. Schematic diagram of LeComber’s amorphous silicon (α-Si) TFT structure and its transfer characteristics [30].

Fig. 2-5. Schematic cross section of an α-Si TFT with the “etch-stopper” layer and the in-situ tri-layer [32].

Fig. 2-6. Schematic cross section of a top-gate low-temperature polysilicon TFT with a storage capacitor [34].

Gate Substrate

S D

Gate Substrate

S D

Insulator Insulator

Organic Semi.

(a) (b)

Organic Semi.

Fig. 2-7. Schematic of the geometries frequently used in organic thin-film transistors with (a) inverted-staggered structure, and (b) inverted-coplanar structure [44].

Fig. 2-8. The output characteristic and the transfer characteristic of the pentacene-based organic thin-film transistor with a high saturation mobility of 0.62 cm²/V-s [46].

Conduction Fig. 2-9. The energy levels of oligo-thiophenes and poly-thiophenes as a function of the

number of conjugated units [48].

Pentacene S

Fig. 2-10. Commonly used high-performance organic and polymer semiconductor materials [21].

Fig. 2-11. Schematic of the re-crystallization mechanism for solid phase growth of amorphous silicon (α-Si) [52].

Fig. 2-12. TEM micrographs for amorphous silicon (α-Si) film as a function of annealing time, such as as-deposited, 1HR, 2HR, and 24HR [53].

Fig. 2-13. Summarized alternative high-κ gate dielectric materials reported in VLSI Symposium and IEDM from 1999 to 2005.

0 5 10 15 20 25 30 35

Fig. 2-14. Energy bandgap versus dielectric constant plots for candidate gate insulators [62], [63].

Fig. 2-15. Energy bandgap versus various lanthanide oxides [67], [68].

Fig. 2-16. Dependence of mobility (μ) on gate electric field (E). (b) Dependence of channel mobility (μ) on charge density (QS). Black or white sample correspond to channel mobility (μ) calculated from gate sweep or drain sweep, respectively. 500 nm SiO2

with gate sweeps (o); 120 nm SiO2 with gate sweeps (•); 82 nm BST with drain sweeps (♠); 90 nm BST with gate sweeps (Δ ); 122 nm BZT with drain sweeps ();

128 nm BZT with gate sweeps (□) [25].

Drain

Fig. 2-17. Schematic view of a thin-film transistor (TFT) under gate and drain biases [93].

q ψ

> 0

Fig. 2-18. The energy bandgap diagram of the metal-insulator-semiconductor (MIS) structure under gate bias [93].

Insulator x

Source Drain

Gate

V_GS V_DS

Accumulation V(x)=V_GS

Depletion d_s

Fig. 2-19. Schematic view of an organic thin-film transistor (OTFT) working in accumulation region under high drain bias [95].

SPC TFT with Various Dielectrics

40 nm TEOS [60]

22 nm ONO [82]

21 nm N2O [83] EOT40 nm

50 nm Al2O3 [85]

50 nm LaAlO3 [86]

27.7 nm HfO2 [16] --------20 nm8.7 nm7.3 nm W/L(mm)50/1040/1050/10200/3100/40.1/1 VTH(V)5.144.754.753*1.2 0.3 **

μ

FE(cm2 /V-s)12.44.626.847*4039 ** S.S.(mV/Dec.)1970642410440*310280 ** ION/IOFF(106 )0.240.951.720.3*6.39.7 ** * Si 0.85Ge0 0.15TFT with Al 2O 3dielectric** NH 3plasma passivationfor 30 min

Table 2-1. Comparisonon electricalcharacteristics of SPC poly-Si TFTswith various gate dielectrics, including TEOS oxide, ONO stackoxide, nitrous oxide (N2O), aluminum oxide (Al2O3), lanthanum-aluminum oxide (LaAlO3), and hafnium oxide (HfO2).

D (nm)

C ins (nF/cm2 )

μ

FE,sat (cm2 /V-s)ION/IOFFS.S. (mV/Dec.)VTH(V) Mn-BST [91]2001060.324x102 7000−1 V @ VD= −4 V

TiO 2[90]2806760.153.5x106 170−0.34 V @ VD= −1 V Gd2O3[87]2801250.1103 300−3.5 V @ VD= −8 V Ta 2O 5[88]453340.32104 500−0.8 V @ VD= −5 V

BZT [25]1221250.383x105 300−2 V @ VD= −5 V TiSiO[92]731250.143x106 140−2.9 V @ V D= −10 V

SiO2[25]1006.90.123x105 1785−18 V @ VD= −50 V LaAlO 3[89]3304021.4107 ---−15 V @ VD= −40 V

Table 2-2. Comparison on electrical characteristics of pentacene-based organic TFTswith various gate dielectrics, including silicon oxide (SiO2), barium zirconatetitanate(BZT), gadolinium oxide (Gd2O3), tantalum pentoxide(Ta2O5), lanthanum-aluminum oxide (LaAlO3), titanium oxide (TiO2), Mn-doped barium strontium titanate(Mn-BST), and titanium-silicon oxide (TiSiO).

CHAPTER 3 F ABRICATION AND C HARACTERIZATION M ETHODS

In this chapter, the detail fabrication steps of the low-temperature polysilicon (LTPS) thin-film transistors (TFTs) and the pentacene-based organic thin-film transistors (OTFTs) with high dielectric constant (high-κ) gate insulators are described. The praseodymium oxide (Pr2O3) film is used for LTPS TFTs. Besides, for pentacene-based OTFTs, the lanthanum-yttrium oxide (LaYOX) film is chosen. The physical analysis techniques as well as the electrical measurement methods used to characterize both LTPS TFTs and OTFTs are also included and presented in this chapter.

3.1 F

ABRICATION OF

L

-T

EMPERATURE

P

OLYCRYSTALLINE

S

ILICON

P

RASEODYMIUM

O

XIDE

T

HIN

-F

ILM

T

RANSISTORS

W

ITH

V

ARIOUS

N

ITROGEN

D

OSAGES

The main fabrication steps of the low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) with a praseodymium oxide (Pr2O3) dielectric were summarized below and shown in Fig. 3-1. In modern liquid crystal display (LCD) industry, the amorphous silicon (α-Si) TFTs or the LTPS TFTs were fabricated on glass substrate as the switching devices in array cells. In our study, the 500-nm thermal oxide grown on 6-inch silicon wafer by using a horizontal furnace was used to simulate the glass substrate of active matrix liquid crystal display (AMLCD). And then, an undoped α-Si film with 50-nm thickness was deposited on the 500-nm thermal oxide by using a low-pressure chemical vapor deposition (LPCVD) system in silane (SiH4) ambient with a pressure of 350 mtorr at 560 °C. In addition,

before silicon oxidation, chemical vapor deposition (CVD), and high-κ deposition in this work, all samples were cleaned by using the traditional RCA process to remove any contamination, native oxide, and atomic scale roughness [96].

To explore the nitrogen effect on the re-crystallization, the nitrogen atoms with various dosages of zero (control sample), 5 × 10¹² cm^-2, and 5 × 10¹³ cm^-2, were implanted into the 50-nm α-Si film with an ion implantation energy of 10 keV, as presented in Fig. 3-1(a). The implantation energy of nitrogen atoms was set by 10 keV with a projected range about 25 nm to induce significant influence overall 50-nm α-Si film. After nitrogen implantation, the conventional solid-phase crystallization (SPC) annealing was processed at 600 °C for 24 hrs in nitrogen ambient to crystallize α-Si film into polycrystalline silicon (poly-Si) film. Such as traditional SPC annealing with the maximum process temperature limited at 600 °C was widely used to recrystallize amorphous silicon (α-Si) film due to its low-production cost and good grain-size uniformity.

Subsequently, the active regions of LTPS TFTs were lithographically patterned and then etched by using a transformer-coupled-plasma (TCP) dry etcher with a chlorine-based gas.

The edge of the active region must be formed an inclined and trapezoid shape because the latter high-κ gate insulator was deposited by using a physical vapor deposition (PVD) method, for its consideration to poor step coverage. Therefore, the exposure dosage and the focus offset should be fine trimmed to exposure the photoresist pattern in a trapezoid shape, and afterward the edge of the active region could become in a trapezoid shape during an anisotropic dry etching process. After removing residue photoresist and performing RCA cleaning process on the poly-Si film, the high-κ praseodymium oxide (Pr2O3) was deposited as the gate insulator by using an electron-beam evaporation system. The working pressure and the deposition rate were controlled within 5 × 10^-5 torr and 0.05 nm/sec, respectively. In order to improve the quality of gate insulator, the praseodymium oxide as the gate dielectric was subjected to a rapid thermal annealing (RTA) process at 600 °C for 1 minute in oxygen

ambient, as shown in Fig. 3-1(b).

After the gate dielectric formation, a 200-nm tantalum nitride (TaN) film was deposited in N2/(Ar+N2) = 5 % ambient at 600 mtorr with a DC power of 500 watt by using a reactive sputter system. Such refractory TaN metal with a resistance to acid-and-oxidation was applicable to gate electrode of thin-film transistor. Next, the TaN metal gate with a thickness of 200 nm was also defined by using a transformer-coupled-plasma (TCP) etcher with a chlorine-based gas, and it could be completely etched within 1 minute. However, the etching rates of the praseodymium oxide layer and I-line photoresist were approximate 0.1 nm/sec and 3 nm/sec, respectively, so that the I-line photoresist with 800-nm thickness could not protect the TaN metal gate if the 42-nm Pr2O3 dielectric was completely removed. Therefore, such dry etching process was capable of stopping on the praseodymium oxide layer while the TaN gate was completely removed, and we took account of the other etching process to remove this Pr2O3 dielectric for the following interconnection.

As displayed in Fig. 3-1(c), phosphorus atoms were self-aligned implanted through the praseodymium oxide layer into the 50-nm poly-Si film with the dosage and the energy of 5 × 10¹⁵ cm^-2 and 90 keV, respectively, to form the source and drain regions of LTPS TFTs. And then, the phosphorus dopants in source and drain regions were activated by using a rapid thermal annealing (RTA) process at 600 °C for 1 minute in nitrogen ambient. Afterwards, the 300-nm tetraethoxylsilane (TEOS) oxide film used as an inter-layer dielectric (ILD) layer was deposited by using a plasma-enhanced chemical vapor deposition (PECVD) system at 300 °C.

Because the praseodymium oxide could not be effectively etched by using a dry etching process, the contact holes were opened by a two-step contact etching process for interconnection, as illustrated in Fig. 3-1(d). Firstly, the 300-nm ILD passivation layer on the source and drain regions was removed by using a wet etching process with a buffered oxide etch (BOE) solution or a dry etching process with a fluorine-based gas. Secondly, the mixed solution of H3PO4: HNO3: CH3COOH: H2O = 50: 2: 10: 9 heated to 60 °C was used to

dissolve the praseodymium oxide film with a high etching selectivity to the ILD passivation layer, the TaN gate metal, and the source and drain regions of poly-Si film. Consequently, the praseodymium oxide film could be completely removed by an over etching. In fact, in this wet etching procedure, the lanthanide-series metal oxides, such as terbium oxide (Tb2O3) or dysprosium oxide (Dy2O3), could be removed by this mixed solution with a stable etching rate of 0.4 ~ 0.5 nm/sec, except for lanthanum oxide (La2O3). The etching rate of the lanthanum oxide by using this mixed solution was so quick (larger than 200 nm/sec) that the gate dielectric of the La2O3 film would be etched over through the channel region of the transistor device. Accordingly, this mixed solution should be diluted or changed with the other recipes for etching La2O3 film.

After the contact holes were opened by this two-step wet etching process, the 500-nm aluminum (Al) film was deposited at 600 mtorr with a DC power of 1500 watt by using a reactive sputter system. Finally, the aluminum pads were lithographically patterned, and subsequently etched by using a TCP metal etcher, and then the nitrogenous poly-Si TFTs with the (Pr2O3) gate dielectric were accomplished, as indicated in Fig. 3-1(e). For comparison, the control Pr2O3 poly-Si TFT without nitrogen implantation (DN = 0) was also prepared by the same process flow. In addition, note that all Pr2O3 poly-Si TFTs had no extra plasma treatment to passivate the trap states in active channel [7], [8] in this work. In order to verify the electrical properties of the praseodymium oxide (Pr2O3) film, the Pr2O3 metal-insulator-silicon (MIS) capacitors were also fabricated together with the same LTPS TFTs process, including the deposition and the annealing of the high-κ dielectric. For the Pr2O3 MIS capacitor fabrication, a shadow mask was used to define the top TaN electrode in a circle pattern with a radius of 220 μm. The bottom aluminum electrode was also deposited after the native oxide on the backside substrate was wiped out by using a buffered oxide etching (BOE) solution.

3.2 F

ABRICATION OF

P

ENTACENE

-B

ASED

O

RGANIC

T

HIN

-F

ILM

T

RANSISTORS

W

ITH

L

ANTHANUM

-Y

TTRIUM

O

XIDE

Figs. 3-2(a) and 3-2(b) showed the schematic top view and its cross section along the AA’ line of the fabricated bottom-gate-top-contact pentacene-based organic thin-film transistor (OTFT) with the gate insulator of high-κ lanthanum-yttrium oxide (LaYOX), respectively. In this OTFT work, all pattern regions were defined by the shadow masks, and the process steps corresponding to their shadow masks were shown in Fig. 3-3. In Fig. 3-3(a), the 500-nm thermal oxide was grown on a 4-inch silicon wafer as a buffer layer to simulate a glass substrate or a flexible substrate where OTFT devices were fabricated. And then, the tantalum nitride (TaN) with a 50-nm thickness was deposited on the oxide/silicon substrate as the bottom-gate electrode, through the shadow mask 1, by using a reactive sputtering system.

Here, the sputter condition was the same as that on the metal gate process of LTPS TFT.

Following, the bottom TaN electrode was treated with ammonia (NH3) plasma at 200 mtorr with a RF power of 100 watts for 10 minutes. Because the following high-κ dielectric was directly deposited on the bottom TaN electrode, its surface characteristics could be improved to inhibit oxidation and to reduce leakage current by such ammonia (NH3) plasma treatment [97], [98].

After the gate electrode formation, the shadow mask 2 was aligned to the TaN pattern on substrate, as shown in Fig. 3-3(b), and it defined the region where the gate insulator should be deposited. Therefore, no high-κ dielectric film was deposited on the bottom gate pad, and the extra etching step was unnecessary to open contact for interconnection. The 30-nm lanthanum-yttrium oxide (LaYOX) thin film was deposited as a gate insulator by using an electron-beam evaporation method. The working pressure and the deposition rate were controlled within 5 × 10^-5 torr and 0.06 nm/sec, respectively. Subsequently, the gate insulator

of lanthanum-yttrium oxide was annealed at 300 °C in oxygen ambient for 30 minutes to improve its film quality.

Next, the pentacene provided from Aldrich Chemical Company without purification (nearly 98 % purity) was deposited on the gate insulator through the shadow mask 3 by using a thermal evaporation method, as shown in Fig. 3-3(c). It was well known that the deposition pressure, the deposition rate, and the deposition temperature were three critical parameters to the quality of organic pentacene film [99]-[101]. The substrate was heated to 70 °C during the pentacene deposition at a pressure around 3 × 10⁻⁶ torr. The thickness of the deposited pentacene film was about 50 nm with a deposition rate of 0.05 nm/sec, monitored by a quartz crystal oscillator. Such deposition condition could significantly decrease the thermal dislocation of pentacene molecules. Moreover, no organic/insulator interface modification [22]-[24] was executed on the insulator surface of the bottom-gate OTFT in this work.

In order to form the ohmic contact, the aurum (Au) metal with a high work function about 5.1 eV, near to the valance band of pentacene crystals, was commonly chosen for the top source/drain electrodes of p-type OTFT device to provide a better injection junction [19], [20]. The top source/drain electrodes were also deposited on the pentacene layer by using a thermal evaporation method, and they were defined by the shadow mask 4, as shown in Fig.

3-3(d). The evaporation pressure and the deposition rate of aurum were 3 × 10^-6 torr and 0.05

~ 0.1 nm/sec, respectively. The channel width (W) and the channel length (L) of the pentacene-based OTFT devices defined by the width and the spacing of the top source/drain electrodes were 1000 μm and 120 μm, respectively. Besides, the Au/LaYOX/TaN metal-insulator-metal (MIM) capacitors were in-situ fabricated with the pentacene-based OTFT device to verify the high-κ LaYOx dielectric properties, as shown in Fig. 3-4. The capacitor area was 200 × 200 μm² defined by the top Au electrode, and the bottom TaN electrodes of the OTFT and the MIM capacitor shared together.

3.3 T

HERMAL

E

VAPORATION AND

E

LECTRON

-B

EAM

E

VAPORATION

There are two physical vapor deposition (PVD) ways to deposit the high-κ dielectrics, including evaporation and sputtering methods [102], [103]. Although the sputtering method is a normal processing in industry, the targets of high-κ dielectric and precious materials used in sputter system are too expensive for the consideration to our budget and flexible research.

Therefore, we choose the evaporation method to use cheaper granule sources for depositing our high-κ dielectrics, the pentacene channel film, and the precious metal aurum (Au) in this experiment. The evaporation method is that the granule source in tungsten crucible or boat is heated to its melting point to evaporation and then its evaporating molecules would diffuse onto the deposited substrate in a vacuum chamber, as shown in Fig. 3-5(a). The chamber during evaporation procedure must be controlled at a high vacuum pressure (about 10^-3 ~ 10^-7 torr) to create a long mean free path neglecting the collision among evaporating molecules.

The fine uniformity and quality of the deposition film could be obtained because the scattering of the evaporating molecules is small in a high vacuum condition. There are two evaporation systems in our laboratory, the thermal evaporation system and the electron-beam evaporation system, as shown in Figs. 3-5(a) and 3-5(b), respectively.

The thermal evaporation system directly applies a low voltage with a high current on the tungsten boat, and it heats the evaporated source in a vacuum condition to achieve the deposition process. However, the thermal evaporation method could not effectively control its evaporation rate due to the nonuniform heating of the evaporated source in the tungsten boat with a large heating area. Besides, the thermal evaporation method could not apply for lots of materials with high melting points, either. Consequently, the pentacene and the precious metal aurum Au with low melting points of 300 °C and 1064 °C, respectively [104] so that the

thermal evaporation system is suitable for their thin-film deposition. By the way, the holder where is put the deposited substrates is heated to 70 °C for decreasing the thermal dislocation

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