Properties of Low-Temperature Polycrystalline Silicon Praseodymium Oxide

S

P

O

T

-F

T

W

V

N

D

4.1-1 Characteristics of Pr2O3 MIS Capacitors

Firstly, the thickness of the deposited Pr2O3 gate insulator is determined by the cross-sectional transmission electron microscope (TEM) image of the gate structure of the fabricated LTPS TFT, as shown in the left inset of Fig. 4-1. The thickness of the praseodymium oxide (Pr2O3) gate dielectric is about 42 nm after a rapid-thermal-annealing (RTA) treatment in oxygen ambient, and the thickness of polycrystalline silicon (poly-Si) channel layer is around 50 nm. The current density of the 42-nm Pr2O3 gate dielectric on p-type silicon substrate has a huge increase to 1 μA/cm² under a negative bias over the electric field of 3 MV/cm. Applying the negative bias on the TaN electrode means the electrons injection from the gate to the substrate. When applying a positive bias, which is minority carriers (electrons) injection from the silicon substrate to top metal, the current density was below 1 μA/cm² until the breakdown larger than 7 MV/cm.

Fig. 4-1 shows the typical capacitance-voltage (C−V) characteristic of the praseodymium oxide (Pr2O3) metal-insulator-silicon (MIS) capacitor at 1 MHz from −4 V to 4 V. The accumulation capacitance density (Cacc) is 432 nF/cm² at the applied voltage of VAPP = –4 V.

According to the TEM image of the 42-nm thickness of the Pr2O3 dielectric on the polycrystalline silicon (poly-Si) film, the equivalent-oxide thickness (EOT) and the effective dielectric constant value (κ) extracted are 8 nm and 25, respectively, from the accumulation capacitance density. Here, the praseodymium silicate formed an interfacial layer between the praseodymium oxide film and the poly-Si film has been included into EOT and κ calculation.

By the way, the hysteresis of the C−V curves is about 30 mV after 100-times −4-to-4 V sweeping, and its value could be neglected. The praseodymium oxide seems a good candidate for the gate dielectric application since the Pr2O3 MIS capacitor represents a high capacitance density and a low leakage current. Therefore, it could be expected that the poly-Si TFT with the Pr2O3 gate dielectric has a well gate controllability resulting in better electrical characteristics, compared to that with conventional plasma TEOS oxide as gate dielectric.

The chemical composition of the Pr2O3 gate dielectric film on silicon substrate is determined by an X-ray photoelectron spectroscopy (XPS) analysis. The XPS spectra of Pr 3d and O 1s core level spectral regions are shown in Fig. 4-2. The Pr 3d signals of the Pr2O3 film consist of the binding energy splitting of the 3d3/2 and the 3d5/2 spin-orbit doublets. The main Pr 3d XPS peak is centered at 953.6 eV and its spin-orbit component is also separated at 933.2 eV. The binding energy and the spin-orbit component associated with the present Pr2O3

features are in agreement with the XPS reference book [107]. It reveals that the Pr2O3 phase formation on silicon substrate is the same as that on in-situ fabricated LTPS TFTs. Besides, the shape of O 1s is also shown in the inset of Fig. 4-2. The XPS peak of O 1s core level spectral at higher binding energy of 530.1 eV could be regarded as the Pr-O bonding. A broad signal existed at the lower binding energy of 533 eV is attributed to the overlap of various components associated with oxide and hydroxide on the surface of Pr2O3 film.

4.1-2 Characteristics of Pr2O3 Poly-Si TFTs With Nitrogen Implantation

Fig. 4-3 shows the transfer characteristics (IDS−V_GS) of the Pr2O3 polycrystalline silicon (poly-Si) TFTs with various nitrogen dosages (DN) of zero (control sample), 5 × 10¹² cm^-2, and 5 × 10¹³ cm^-2, measured in linear regime at VDS = 0.1 V. The channel length (L) and the channel width (W) of the Pr2O3 poly-Si TFT are 10 μm and 5 μm, respectively. When the implanted nitrogen dosage increases to 5 × 10¹² cm^-2, the electrical performances of the Pr2O3

poly-Si TFT could be improved, including the decrease of the threshold voltage (VTH) and the increase of the transconductance (Gm), compared to those of the control sample (DN = 0cm^-2).

The subthreshold swings (S.S.) of these Pr2O3 poly-Si TFTs defined by the Eq. (3-8) seem no change with various nitrogen dosages.

As the papers reported on [108]-[110], the interface trap states and the grain boundary trap states dominate the electrical characteristics of poly-Si TFT. The deep trap states in the grain boundaries and in the interface mainly affect on the threshold voltage. Besides, the tail states in the interface states and in the grain boundaries mainly contribute to the degradation of the transconductance. The subthreshold swing mainly depends on the deep interface trap states and on the bulk states in intra-grain defects. These relationships between trap states and device parameters of LTPS TFT are summarized in Table 4-1. Compared with Table 4-1 and Fig. 4-3, such the same subthreshold swings of three TFT devices indicate that their interface trap states at the Pr2O3 gate dielectric/poly-Si channel interface are not changed with various nitrogen dosages. Further, the transconductance and the threshold voltage of three TFT devices are fluctuated with various nitrogen dosages. Therefore, the electrical improvement of the Pr2O3 poly-Si TFT by incorporating nitrogen could be attributed to the reduction of the grain boundary trap states within the poly-Si film during conventional solid-phase crystallization (SPC) annealing. However, when the nitrogen dosage increases to 5 × 10¹³ cm^-2, the electrical characteristics of the Pr2O3 poly-Si TFT would be degraded with larger threshold voltage and smaller transconductance. The overdose of nitrogen implantation (DN = 5 × 10¹³ cm^-2) in amorphous silicon (α-Si) film would obstruct α-Si film crystallized to poly-Si film, compared to that without nitrogen implantation (control sample). Therefore, the drain current of the Pr2O3 poly-Si TFT without large-size poly-Si grains is decreased.

Fig. 4-4 compares the transfer characteristics (IDS−VGS) of the Pr2O3 poly-Si TFTs with the nitrogen dosages of 0 cm^-2 and 5 × 10¹² cm^-2 under VDS = 0.1 V and 1 V. The inserted table summarizes the electrical parameters of these two devices. The electrical characteristics of the

control Pr2O3 poly-Si TFTs without nitrogen dosage is inferior to those with a nitrogen dosage of 5 × 10¹² cm^-2. The threshold voltage (VTH) and the field-effect mobility (μFE) could be significantly improved from 2.15 to 1.9 V and from 34 to 47.4 cm²/V-s, respectively. In addition, both the subthreshold swings (S.S.) and the ON/OFF current ratios of them are almost the same with the values about 242 mV/dec and over the sixth power of ten, respectively. Besides, the gate-induced drain leakage (GIDL) current [111], [112] at VDS = 1 V and VGS = 0 V also could be suppressed by a half-order magnitude by using the nitrogen implantation with a suitable dosage of 5 × 10¹² cm^-2. As well-known, the GIDL current of poly-Si TFTs is an off-state leakage current which is generated from the field-enhanced emission through the trap states and then resulted in the traps assisted band-to-band tunneling current near the drain junction under a high drain field. Implanting a moderate dosage of nitrogen atoms into the amorphous silicon film could effectively passivate the trap states at grain boundaries during SPC annealing. Therefore, the Pr2O3 poly-Si TFT with implanting a moderate nitrogen dosage of 5 × 10¹² cm^-2 has less grain boundary trap states in its poly-Si channel than the control sample so that the GIDL current could be reduced, especially under a high drain-voltage operation.

The output characteristics (IDS−V_DS) of the Pr2O3 poly-Si TFTs with nitrogen dosages of zero and 5 × 10¹² cm^-2 are shown in Fig. 4-5. The driving current of the Pr2O3 poly-Si TFT with a nitrogen dosage of 5 × 10¹² cm^-2 has about 40 % improvement at VGS = 4 V, compared to that of the control sample. The pervious studies [16], [82]-[86] have been reported that the poly-Si TFT with a high-κ gate dielectric exhibited a high gate capacitance density could induce more charge carriers and quickly fill the trap states in poly-Si channel to improve device electrical characteristics due to the well gate controllability. However, in this work, using the nitrogen implantation technique in the Pr2O3 poly-Si TFTs would further passivate these grain boundary trap states in poly-Si channel film and improve the device performance.

The electrical reliability on the Pr2O3 poly-Si TFTs with and without the nitrogen

implantation is investigated in Fig. 4-6. All devices are biased at VGS = VDS = 4 V, under a hot-carrier stress condition. The degradation of the drain current (IDS) is defined as ΔIDS/IDS,0, where the ΔI_DS = I_DS,S− I_DS,0, IDS,0 is the initial drain current, and IDS,S is the drain current for each stress time. The IDS degradation of the Pr2O3 poly-Si TFT with a nitrogen dosages (DN) of 5 × 10¹² cm^-2 is about 5 % after 1000-s hot-carrier stress, which is superior to that without nitrogen implantation (control sample). The IDS degradation of the control sample is saturated to −70 % after 200-s hot-carrier stress. It has been reported that the hot-carrier stress easily breaks the weak Si-Si bonds and Si-H bonds (with the bonding energy of 70 kcal/mol [113]) to generate the interface states and the grain boundary trap states in poly-Si film [108], [109].

If the appropriate nitrogen atoms are implanted into α-Si film during solid phase crystallization (SPC) annealing, the stronger Si-N bonds with a higher bonding energy of 81 kcal/mol [113] would replace the weak Si-Si and Si-H bonds to excellent hot-carrier endurance. It is noted that the Pr2O3 poly-Si TFT with a nitrogen dosage of 5 × 10¹² cm^-2, even under a higher stress current (see Fig. 4-3), has a better hot-carrier stress immunity than that without nitrogen implantation. On the other hand, as to the Pr2O3 poly-Si TFT with a nitrogen dosage of 5 × 10¹³ cm^-2, its ION degradation is saturated at −50 % after 400-s hot-carrier stress, which seems better than that of the control sample (DN = 0 cm^-2). This reason could be attributed to that the overdose of nitrogen implantation would restrict α-Si film crystallization and result in the inferior electrical characteristics of the Pr2O3 poly-Si TFT, as shown in Fig. 4-3. The hot-carrier stress degradation on TFT device with a nitrogen dosage of 5 × 10¹³ cm^-2 is more alleviative than control sample under the same stress bias. In a brief summary, the Pr2O3 poly-Si TFT with applicable nitrogen incorporation in poly-Si channel has a better immunity on the hot-carrier stress, compared to the control sample.

Table 4-2 compares all electrical parameters of the SPC poly-Si TFTs with various gate dielectrics, including TEOS oxide [60], aluminum oxide (Al2O3) [85], lanthanum-aluminum oxide (LaAlO3) [86], and praseodymium oxide (Pr2O3). The subthreshold swing of the poly-Si

TFTs with high-κ dielectrics has a gradual improvement from 1.97 V to 0.24 V, compared to that with the TEOS dielectric [60]. A large gate capacitance density (Cins) could induce more inversion charges to minimize the effect on depletion charges and interface charges, as shown in Eq. 3-8.

The body-effect coefficient m could be smaller by large gate capacitance density (Cins). The better switching characteristic, corresponding to the good threshold swing, makes the smaller threshold voltage at the same turn-on current condition. Besides, the reason why the poly-Si0.85Ge0.15 TFT with an Al2O3 gate dielectric has a higher mobility of 47 cm²/V-s is that the poly-Si0.85Ge0.15 film with a narrow energy bandgap easily induces more carrier charges in its channel [85]. However, the narrow energy bandgap also induces a large leakage current so that the ON/OFF current ratio (ION/IOFF) of the poly-Si0.85Ge0.15 TFT is not large as the other samples. The control sample (DN = 0 cm^-2) in this work has the same characteristics compared to the LaAlO3 poly-Si TFT, expect the threshold voltage. In ref. [86], the authors integrate the aluminum metal gate with a low work function value into their LaAlO3 poly-Si TFT, but the aluminum (Al) metal gate is deposited after the dopant activation is complete. In this work, we use the refractory metal of TaN as the metal gate, which could sustain an activation temperature of 600 °C to achieve the self-align implantation process. However, the work function of the TaN metal is around 4.5 eV higher than that of the Al metal of around 4 eV.

Therefore, our threshold voltage of the control sample is slightly larger than that of the LaAlO3 poly-Si TFT. In this work, the LTPS TFTs with 42-nm Pr2O3 gate dielectric has an equivalent-oxide thickness (EOT) of 8 nm. Because of the roughness of poly-Si and the fast deposition rate of TEOS oxide, the conventional LTPS TFTs with 8-nm TEOS gate dielectric is difficult to fabricate and it would cause large gate leakage current during operation. Finally,

as regards the Pr2O3 poly-Si TFTs with various nitrogen dosages, their threshold swings are controlled within 300 mV, which verify the well gate controllability due to the integration of the high-κ gate dielectric process. The Pr2O3 poly-Si TFT with an overdose nitrogen implantation has a poor crystallization on poly-Si channel film so that its mobility, threshold voltage, and ON/OFF current ratio are inferior to those of the other two devices in this work.

4.1-3 Summary

High-performance low-temperature polycrystalline silicon (LTPS) TFTs integrated nitrogen implantation and praseodymium oxide (Pr2O3) gate dielectric are demonstrated in this section. High gate capacitance density (~ 432 nF/cm²) and high breakdown electrical field (> 3 MV/cm) are introduced by using the MIS capacitor with a 42-nm Pr2O3 gate dielectric and the TaN gate metal. The electrical characteristics of the poly-Si TFT with a Pr2O3 gate dielectric could be improved without additional plasma treatment due to the well gate controllability, for example, over six-order magnitudes of the ON/OFF ratio. Moreover, the threshold voltage (VTH) and the field-effect mobility (μFE) of the Pr2O3 poly-Si TFT with a nitrogen dosage of 5 × 10¹² cm^-2 progress to 1.9 V and 47.4 cm²/V-s, respectively. Based on the hot-carrier stress testing, we know that implanting nitrogen atoms in poly-Si film could form the stronger Si-N bonds during SPC annealing and passivate the trap states in poly grains and in grain boundaries. Therefore, the proposed Pr2O3 poly-Si TFT with suitable nitrogen incorporation would be a promising candidate for matrix devices and high-speed driving circuit applications in the near future.

4.2 P

P

-B

O

T

-F

T

W

L

-Y

O

4.2-1 Characteristics of LaYOX MIM Capacitor

In order to verify the electrical properties of the lanthanum-yttrium oxide (LaYOX) film, the capacitance-voltage (C−V) characteristic and the current density (J−V) curve are measured by using the Au/LaYOX/TaN metal-insulator-metal (MIM) capacitor, as shown in Fig. 4-7.

The area of this MIM capacitor is defined by a shadow mask in a square pattern of 200 × 200 μm². The capacitance density is measured from −5 V to 5 V sweeping at 100 kHz. The MIM capacitor with a 30-nm LaYOX insulator has a high capacitance density of 420 nF/cm² and a low leakage current density of 1 μA/cm² under the applied voltage of 5 V on the aurum (Au) electrode. It also shows a small tunability of 2 % variation from 0 V to −5 V, insuring the voltage independence on capacitance density and making more predictable for organic thin-film transistor (OTFT) operation. In terms of the capacitance-voltage calculation, the equivalent-oxide thickness (EOT) and the effective dielectric constant value (κ) of the 30-nm LaYOX gate dielectric on tantalum nitride (TaN) electrode are around 8.2 nm and 14.2 at the applied voltage of −4 V, respectively. The previous studies have been reported that the 5-nm LaYOX thin film with 40-to-60 % yttrium doped concentration annealed at 600 °C has a high κ value of 29 [80], [81], [105], [106]. The dielectric constant value of our nonstoichiometric LaYOX thin film is lower than that of the previous reports because the high-κ LaYOX film is annealed at a low temperature of 300 °C in this work.

Two distinct behaviors in the J−V plot are observed, where the leakage current density keeps lower than 2 × 10^-8 A/cm² in the low voltage region (below 3 V) but rapidly increases in the high voltage region (above 3 V). It is well known that the former region could be ascribed to the dielectric relaxation [115] and the latter region is to the Poole-Frenkel emission from

the TaN electrode, [116].Therefore, it could be expected that the pentacene-based OTFT with a high-κ dielectric of LaYOX gate insulator has a low gate leakage current and a well gate controllability resulting in better electrical characteristics, compared to that with thermal or sputtering gate oxide [25], [88] without interface modification. Because the work function of TaN electrode with ammonia plasma treatment (~ 4.6 eV) is smaller than that of Au electrode (~ 5 eV), the leakage current density under bottom-injection condition where the positive bias is applied on Au electrode, is higher than that under top-injection condition. Such high capacitance density and low leakage current density of Au/LaYOX/TaN MIM capacitor represent that the high-κ LaYOX thin film, even subjected to a low-temperature annealing at 300 °C, is still a good candidate for gate dielectric application.

4.2-2 Characteristics of Pentacene Layer

Fig. 4-8 provides the information on the crystallinity and the surface morphology of the pentacene channel layer strongly dependent on the surface condition of the substrate material.

These glancing-incidence X-ray diffraction (GI-XRD) peaks of the deposited pentacene layer correspond to (hkl) equal to (001), (002), (003), and (004), respectively [87], [101]. It indicates a well-oriented film with a c-axis perpendicular of the pentacene layer on the lanthanum-yttrium oxide (LaYOX) film. The main XRD peak of the LaYOX film located at 29.7° with a hexagonal phase corresponding to (002) [80] and that of the TaN film located at 35.4° with a face-center cubic phase corresponding to (111) [97] are not shown in Fig. 4-8.

The GIXRD peaks of the pentacene layer present an average crystalline quality of the channel layer deposited on the LaYOX/TaN gate structure without organic/insulator interface modification [22]-[24]. The atomic force microscopy (AFM) image of the pentacene layer deposited on the LaYOX/TaN layers is also shown in the inset of Fig. 4-8. The pentacene layer on the LaYOX film also performs a good surface roughness and a dendrite grains to achieve

an acceptable quality channel in OTFT. As a result, in this work, the crystalline quality and the surface roughness of the deposited pentacene channel layer on the LaYOX/TaN gate structure are compatible with the other reports [87], [101]. Therefore, if there is any electrical improvement on our proposed pentacene-based OTFT, it could be attributed to the benefit by using the high-κ gate dielectric of the lanthanum-yttrium oxide film.

4.2-3 Characteristics of Organic TFTs With LaYOX Gate Insulator

Fig. 4-9 reveals the transfer characteristics (IDS−VGS) and its square root plot (IDS1/2−VGS) of the pentacene-based OTFT with a high-κ dielectric of the lanthanum-yttrium oxide (LaYOX) gate insulator measured at VDS = −2 V. The data points are spaced to 0.01 V to ensure a good accuracy during measurement. The resolution setting and the noise are set 10 pA and smaller than 100 fA, respectively. The curves are typical for the pantacene-based OTFT working in accumulation mode. The threshold voltage (VTH) of the pentacene-based OTFT with a high-κ dielectric of LaYOX gate insulator estimated from the x-axis intercept of the IDS1/2−VGS plot at VGS = −2 V is nearly −1.25 V, which is a dramatically decreased value compared to that with silicon-oxide based insulator [25]. According to the standard OTFT theory in Chapter 3, the field-effect mobility in saturation regime (μFE,sat) could be calculated from the following equation

, where the Cins is the gate capacitance density of the insulator layer. The Cins is 410 nF/cm² obtained from the Au/LaYOX/TaN MIM capacitor measured at the applied voltage of −4 V on Au electrode. The saturation drain current (IDS,sat) of this high-κ LaYOX OTFT with a dimension of W/L = 1000 μm/120 μm is 0.21 μA measured at VGS = VDS = −2 V. Therefore, we figure that the μFE,sat is approximately 0.22 cm²/V-s, which is the hole mobility in the

pentacene channel under saturation operation. By means of the high-κ lanthanum-yttrium oxide (LaYOX) insulator with a large gate capacitance density (Cins), the higher concentration carriers could be accumulated in the pentacene channel at the same gate voltage and the Fermi level moves toward the band edge. The trapping states located in the grain boundaries are filled, and consequently the injection carriers are free to move with the microscopic mobility

pentacene channel under saturation operation. By means of the high-κ lanthanum-yttrium oxide (LaYOX) insulator with a large gate capacitance density (Cins), the higher concentration carriers could be accumulated in the pentacene channel at the same gate voltage and the Fermi level moves toward the band edge. The trapping states located in the grain boundaries are filled, and consequently the injection carriers are free to move with the microscopic mobility