Material Analysis

The X-ray diffraction (XRD) experiments (RU-H3R, Rigaku, Japan) are performed by using a Dmmax-B diffractometer with a 0.02-degree beam divergence at 30 keV and 30 mA with Cu-Kα radiation. The X-ray diffraction is a powerful non-destructive technique for characterizing crystalline materials. It provides information on structures, phases, preferred crystal orientations (textures), and other structural parameters, such as average grain size, crystallinity, strain, and crystal defects. The peaks of X-ray diffraction are produced by the constructive interference of the monochromatic beam scattered from each set of lattice planes at specific angles. The intensity of every peak is determined by the atomic decoration within the lattice planes. Consequently, the X-ray diffraction pattern is the fingerprint of the periodic atomic arrangements in a given material. In this work, we use this XRD system to analyze the crystallinity of the pentacene film deposited on gate insulator.

The cross section of the fabricated samples could be observed by using a transmission electron microscope (TEM). The principle of TEM is similar to that of optical microscope. In TEM, observation is made in an ultra high vacuum condition, where an electron beam is focused onto the sample by using electromagnetic lenses. Because the wavelength of the electron beam is less than that of visible spectra, the resolution of TEM is higher than that of the conventional optical microscope. In this work, the deposited high-κ dielectric is prepared by using a focus ion beam (FIB) system with the model Nova 200 of FEI Company, and then it is transferred to JEOL JME-3000F TEM system for observing its thickness.

The Auger electron spectroscopy (AES) (Microlab 350, Thermal VG Scientific Company, England) is used to analyze the composition of our deposited high-κ dielectrics, praseodymium oxide (Pr2O3) and lanthanum-yttrium oxide (LaYOX). The X-ray photoelectron spectroscopy (XPS), also known as the electron spectroscopy for chemical analysis (ESCA),

is a quantitative spectroscopic technique to measure elemental composition, empirical formula, chemical state, and electronic state of elements existed within a material. Samples would irradiate with X-ray, and their emitted photoelectrons with kinetic energy (KE) are detected. The measured kinetic energy (KE) is given by

= − − _S

KE hv BE φ _(3-13)

, where hv is the photon energy, BE is the binding energy of the atomic orbital where electron generates, and φ_S is the spectrometer work function. The binding energy is the minimum energy to break the chemical bond inherent in each bond of the measured molecule.

Thus, the binding states could be identified by the positions of the binding energies where the peaks appear. In the case that the peak position is different from the expected positions, the chemical bond states are discussed the amount of shifting to the higher or the lower energy side.

Atomic force microscopy (AFM) (Dimension 5000, Veeco, USA) is used to study the surface morphology with a molecular or atomic resolution. The principle could be described as the force acting on the scanning tip via detecting the deflection of the moving cantilever.

The interaction force between the scanning tip and the sample surface is the essential parameter to determine AFM scanning mode. By decreasing the gap between the scanning tip and the sample surface, the interaction force can change from attractive force to repulsive force. With further reducing the gap, the repulsive force can dramatically increase due to the Pauli exclusion principle and become the dominant interaction. With varying the interaction force, the cantilever deflects in different ways to bend upward, downward, or twisted. In this study, we use the tapping mode to explore the surface morphology of the pentacene film on gate insulator.

Si Substrate 500-nm Thermal Oxide

50-nm α-Si Film

10-keV N₂ Implantation + 600 °C SPC

(a) Thermal oxidation, α-Si deposition, nitrogen implantation, and SPC annealing.

600 °C RTA in O₂ for 1 min

Si Substrate 500-nm Thermal Oxide

42-nm Pr₂O₃ Film 50-nm Poly-Si Film

(b) Active region patterning, Pr2O3 deposition, and Pr2O3 annealing.

90-keV P₃₁⁺ Implantation

Si Substrate 500-nm Thermal Oxide

42-nm Pr₂O₃ Film Poly-Si Film

200-nm TaN Gate

N+ N+

(c) TaN gate deposition and patterning, and then self-align implantation and activation.

Si Substrate

(d) ILD deposition and contact hole opening.

Si Substrate

(e) Al deposition and patterning.

Fig. 3-1. The main process steps of the Pr2O3 poly-Si TFT with nitrogen-implanted poly-Si film.

A A’

L W

(a)

500-nm SiO

₂

Si Substrate 70-nm Pentacene

30-nm LaYOx 50-nm TaN

50-nm Au Electrode

(b)

Fig. 3-2. (a) The top view of the fabricated pentacene-based organic thin-film transistor (OTFT). (b) The cross-sectional structure of the pentacene OTFT with high-κ LaYOX gate insulator along AA’ dashed line in (a).

500-nm SiO₂ Si Substrate 50-nm TaN Shadow Mask 1 Alignment Mark

For Gate Definition

(a) Shadow mask 1 for TaN gate deposition.

500-nm SiO₂ Si Substrate 30-nm LaYOx

50-nm TaN Shadow Mask 2 For High-κ Definition

Alignment Mark

(b) Shadow mask 2 with the TaN pattern alignment for high-κ LaYOX deposition.

500-nm SiO₂ Si Substrate 70-nm Pentacene

30-nm LaYOx 50-nm TaN Shadow Mask 3 For Channel Definition

(c) Shadow mask 3 with the TaN pattern alignment for pentacene deposition.

500-nm SiO₂ Si Substrate 70-nm Pentacene

30-nm LaYOx 50-nm TaN 50-nm Au Electrode

Shadow Mask 4

(d) Shadow mask 4 with the TaN pattern alignment for Au electrode deposition.

Fig. 3-3. The schematic view of the shadow masks corresponding to their process for pentacene-based OTFT fabrication.

L

W

OTFT Device MIM Capacitors

Fig. 3-4. The schematic view of the Au/LaYOX/TaN metal-insulator-metal (MIM) capacitors in-situ fabricated with OTFT device.

A

Holder

Shutter

W Boat HV Evaporation Source

Wafer

Holder

Shutter

Evaporation Source

Wafer

W Granule

HV Source B

(a) (b)

Electron Emission

Fig. 3-5. The schematic views of (a) the thermal evaporation system, and (b) the electron-beam evaporation system.

I

_DS,N

= W/L x 100 nA

V

_{GS, N}

= V

_TH

V

_DS

= 0.1 V

S.S. = 1/slope

_(max)

I

_{ON, max}

I

_{OFF, min}

ON/OFF Current Ratio = I

_{ON. max}

/I

_{OFF, min}

Gate-Source Voltage, V

_GS

Dr a in Cu rr e nt, I

DS

(i n Log. S c a le )

Fig. 3-6. The device parameters, including threshold voltage (VTH), subthreshold swing (S.S), and ON/OFF current ratio, extracted from the transfer characteristic plot.

CHAPTER 4

R ESULTS AND D ISCUSSION

This chapter divides into two main categories, which contain the characteristics of the low-temperature polycrystalline silicon (LTPS) praseodymium oxide (Pr2O3) thin-film transistors (TFTs) with various nitrogen dosages and those of the organic thin-film transistor (OTFT) with a lanthanum-yttrium oxide (LaYOX) gate insulator. The quality of the high-κ dielectric films is examined by using the metal-insulator-silicon (MIS) and the metal-insulator-metal (MIM) capacitors, including the measurements of the capacitance-voltage (C-V) curves and the current density-voltage (J-V) curves. The composition of these two high-κ gate dielectrics, Pr2O3 film and LaYOX film, is presented by using the X-ray photoelectron spectroscopy (XPS) analysis. In terms of the analysis on the electrical parameters, for examples on the threshold voltage (VTH), the field-effect mobility (μ_FE), and the subthreshold swing (S.S.), the benefits of integrating high-κ dielectrics into these two kinds of thin-film transistors are discussed. Moreover, the effects on various nitrogen dosages in polycrystalline silicon film subjected to conventional solid phase crystallization (SPC) annealing are also investigated by using the hot-carrier stress testing on the LTPS TFTs with the Pr2O3 gate dielectric.

4.1 P

ROPERTIES OF

L

OW

-T

EMPERATURE

P

OLYCRYSTALLINE

S

ILICON

P

RASEODYMIUM

O

XIDE

T

HIN

-F

ILM

T

RANSISTORS

W

ITH

V

ARIOUS

N

ITROGEN

D

OSAGES

4.1-1 Characteristics of Pr2O3 MIS Capacitors

Firstly, the thickness of the deposited Pr2O3 gate insulator is determined by the cross-sectional transmission electron microscope (TEM) image of the gate structure of the fabricated LTPS TFT, as shown in the left inset of Fig. 4-1. The thickness of the praseodymium oxide (Pr2O3) gate dielectric is about 42 nm after a rapid-thermal-annealing (RTA) treatment in oxygen ambient, and the thickness of polycrystalline silicon (poly-Si) channel layer is around 50 nm. The current density of the 42-nm Pr2O3 gate dielectric on p-type silicon substrate has a huge increase to 1 μA/cm² under a negative bias over the electric field of 3 MV/cm. Applying the negative bias on the TaN electrode means the electrons injection from the gate to the substrate. When applying a positive bias, which is minority carriers (electrons) injection from the silicon substrate to top metal, the current density was below 1 μA/cm² until the breakdown larger than 7 MV/cm.

Fig. 4-1 shows the typical capacitance-voltage (C−V) characteristic of the praseodymium oxide (Pr2O3) metal-insulator-silicon (MIS) capacitor at 1 MHz from −4 V to 4 V. The accumulation capacitance density (Cacc) is 432 nF/cm² at the applied voltage of VAPP = –4 V.

According to the TEM image of the 42-nm thickness of the Pr2O3 dielectric on the polycrystalline silicon (poly-Si) film, the equivalent-oxide thickness (EOT) and the effective dielectric constant value (κ) extracted are 8 nm and 25, respectively, from the accumulation capacitance density. Here, the praseodymium silicate formed an interfacial layer between the praseodymium oxide film and the poly-Si film has been included into EOT and κ calculation.

By the way, the hysteresis of the C−V curves is about 30 mV after 100-times −4-to-4 V sweeping, and its value could be neglected. The praseodymium oxide seems a good candidate for the gate dielectric application since the Pr2O3 MIS capacitor represents a high capacitance density and a low leakage current. Therefore, it could be expected that the poly-Si TFT with the Pr2O3 gate dielectric has a well gate controllability resulting in better electrical characteristics, compared to that with conventional plasma TEOS oxide as gate dielectric.

The chemical composition of the Pr2O3 gate dielectric film on silicon substrate is determined by an X-ray photoelectron spectroscopy (XPS) analysis. The XPS spectra of Pr 3d and O 1s core level spectral regions are shown in Fig. 4-2. The Pr 3d signals of the Pr2O3 film consist of the binding energy splitting of the 3d3/2 and the 3d5/2 spin-orbit doublets. The main Pr 3d XPS peak is centered at 953.6 eV and its spin-orbit component is also separated at 933.2 eV. The binding energy and the spin-orbit component associated with the present Pr2O3

features are in agreement with the XPS reference book [107]. It reveals that the Pr2O3 phase formation on silicon substrate is the same as that on in-situ fabricated LTPS TFTs. Besides, the shape of O 1s is also shown in the inset of Fig. 4-2. The XPS peak of O 1s core level spectral at higher binding energy of 530.1 eV could be regarded as the Pr-O bonding. A broad signal existed at the lower binding energy of 533 eV is attributed to the overlap of various components associated with oxide and hydroxide on the surface of Pr2O3 film.

4.1-2 Characteristics of Pr2O3 Poly-Si TFTs With Nitrogen Implantation

Fig. 4-3 shows the transfer characteristics (IDS−V_GS) of the Pr2O3 polycrystalline silicon (poly-Si) TFTs with various nitrogen dosages (DN) of zero (control sample), 5 × 10¹² cm^-2, and 5 × 10¹³ cm^-2, measured in linear regime at VDS = 0.1 V. The channel length (L) and the channel width (W) of the Pr2O3 poly-Si TFT are 10 μm and 5 μm, respectively. When the implanted nitrogen dosage increases to 5 × 10¹² cm^-2, the electrical performances of the Pr2O3

poly-Si TFT could be improved, including the decrease of the threshold voltage (VTH) and the increase of the transconductance (Gm), compared to those of the control sample (DN = 0cm^-2).

The subthreshold swings (S.S.) of these Pr2O3 poly-Si TFTs defined by the Eq. (3-8) seem no change with various nitrogen dosages.

As the papers reported on [108]-[110], the interface trap states and the grain boundary trap states dominate the electrical characteristics of poly-Si TFT. The deep trap states in the grain boundaries and in the interface mainly affect on the threshold voltage. Besides, the tail states in the interface states and in the grain boundaries mainly contribute to the degradation of the transconductance. The subthreshold swing mainly depends on the deep interface trap states and on the bulk states in intra-grain defects. These relationships between trap states and device parameters of LTPS TFT are summarized in Table 4-1. Compared with Table 4-1 and Fig. 4-3, such the same subthreshold swings of three TFT devices indicate that their interface trap states at the Pr2O3 gate dielectric/poly-Si channel interface are not changed with various nitrogen dosages. Further, the transconductance and the threshold voltage of three TFT devices are fluctuated with various nitrogen dosages. Therefore, the electrical improvement of the Pr2O3 poly-Si TFT by incorporating nitrogen could be attributed to the reduction of the grain boundary trap states within the poly-Si film during conventional solid-phase crystallization (SPC) annealing. However, when the nitrogen dosage increases to 5 × 10¹³ cm^-2, the electrical characteristics of the Pr2O3 poly-Si TFT would be degraded with larger threshold voltage and smaller transconductance. The overdose of nitrogen implantation (DN = 5 × 10¹³ cm^-2) in amorphous silicon (α-Si) film would obstruct α-Si film crystallized to poly-Si film, compared to that without nitrogen implantation (control sample). Therefore, the drain current of the Pr2O3 poly-Si TFT without large-size poly-Si grains is decreased.

Fig. 4-4 compares the transfer characteristics (IDS−VGS) of the Pr2O3 poly-Si TFTs with the nitrogen dosages of 0 cm^-2 and 5 × 10¹² cm^-2 under VDS = 0.1 V and 1 V. The inserted table summarizes the electrical parameters of these two devices. The electrical characteristics of the

control Pr2O3 poly-Si TFTs without nitrogen dosage is inferior to those with a nitrogen dosage of 5 × 10¹² cm^-2. The threshold voltage (VTH) and the field-effect mobility (μFE) could be significantly improved from 2.15 to 1.9 V and from 34 to 47.4 cm²/V-s, respectively. In addition, both the subthreshold swings (S.S.) and the ON/OFF current ratios of them are almost the same with the values about 242 mV/dec and over the sixth power of ten, respectively. Besides, the gate-induced drain leakage (GIDL) current [111], [112] at VDS = 1 V and VGS = 0 V also could be suppressed by a half-order magnitude by using the nitrogen implantation with a suitable dosage of 5 × 10¹² cm^-2. As well-known, the GIDL current of poly-Si TFTs is an off-state leakage current which is generated from the field-enhanced emission through the trap states and then resulted in the traps assisted band-to-band tunneling current near the drain junction under a high drain field. Implanting a moderate dosage of nitrogen atoms into the amorphous silicon film could effectively passivate the trap states at grain boundaries during SPC annealing. Therefore, the Pr2O3 poly-Si TFT with implanting a moderate nitrogen dosage of 5 × 10¹² cm^-2 has less grain boundary trap states in its poly-Si channel than the control sample so that the GIDL current could be reduced, especially under a high drain-voltage operation.

The output characteristics (IDS−V_DS) of the Pr2O3 poly-Si TFTs with nitrogen dosages of zero and 5 × 10¹² cm^-2 are shown in Fig. 4-5. The driving current of the Pr2O3 poly-Si TFT with a nitrogen dosage of 5 × 10¹² cm^-2 has about 40 % improvement at VGS = 4 V, compared to that of the control sample. The pervious studies [16], [82]-[86] have been reported that the poly-Si TFT with a high-κ gate dielectric exhibited a high gate capacitance density could induce more charge carriers and quickly fill the trap states in poly-Si channel to improve device electrical characteristics due to the well gate controllability. However, in this work, using the nitrogen implantation technique in the Pr2O3 poly-Si TFTs would further passivate these grain boundary trap states in poly-Si channel film and improve the device performance.

The electrical reliability on the Pr2O3 poly-Si TFTs with and without the nitrogen

implantation is investigated in Fig. 4-6. All devices are biased at VGS = VDS = 4 V, under a hot-carrier stress condition. The degradation of the drain current (IDS) is defined as ΔIDS/IDS,0, where the ΔI_DS = I_DS,S− I_DS,0, IDS,0 is the initial drain current, and IDS,S is the drain current for each stress time. The IDS degradation of the Pr2O3 poly-Si TFT with a nitrogen dosages (DN) of 5 × 10¹² cm^-2 is about 5 % after 1000-s hot-carrier stress, which is superior to that without nitrogen implantation (control sample). The IDS degradation of the control sample is saturated to −70 % after 200-s hot-carrier stress. It has been reported that the hot-carrier stress easily breaks the weak Si-Si bonds and Si-H bonds (with the bonding energy of 70 kcal/mol [113]) to generate the interface states and the grain boundary trap states in poly-Si film [108], [109].

If the appropriate nitrogen atoms are implanted into α-Si film during solid phase crystallization (SPC) annealing, the stronger Si-N bonds with a higher bonding energy of 81 kcal/mol [113] would replace the weak Si-Si and Si-H bonds to excellent hot-carrier endurance. It is noted that the Pr2O3 poly-Si TFT with a nitrogen dosage of 5 × 10¹² cm^-2, even under a higher stress current (see Fig. 4-3), has a better hot-carrier stress immunity than that without nitrogen implantation. On the other hand, as to the Pr2O3 poly-Si TFT with a nitrogen dosage of 5 × 10¹³ cm^-2, its ION degradation is saturated at −50 % after 400-s hot-carrier stress, which seems better than that of the control sample (DN = 0 cm^-2). This reason could be attributed to that the overdose of nitrogen implantation would restrict α-Si film crystallization and result in the inferior electrical characteristics of the Pr2O3 poly-Si TFT, as shown in Fig. 4-3. The hot-carrier stress degradation on TFT device with a nitrogen dosage of 5 × 10¹³ cm^-2 is more alleviative than control sample under the same stress bias. In a brief summary, the Pr2O3 poly-Si TFT with applicable nitrogen incorporation in poly-Si channel has a better immunity on the hot-carrier stress, compared to the control sample.

Table 4-2 compares all electrical parameters of the SPC poly-Si TFTs with various gate dielectrics, including TEOS oxide [60], aluminum oxide (Al2O3) [85], lanthanum-aluminum oxide (LaAlO3) [86], and praseodymium oxide (Pr2O3). The subthreshold swing of the poly-Si

TFTs with high-κ dielectrics has a gradual improvement from 1.97 V to 0.24 V, compared to that with the TEOS dielectric [60]. A large gate capacitance density (Cins) could induce more inversion charges to minimize the effect on depletion charges and interface charges, as shown in Eq. 3-8.

The body-effect coefficient m could be smaller by large gate capacitance density (Cins). The better switching characteristic, corresponding to the good threshold swing, makes the smaller threshold voltage at the same turn-on current condition. Besides, the reason why the poly-Si0.85Ge0.15 TFT with an Al2O3 gate dielectric has a higher mobility of 47 cm²/V-s is that the poly-Si0.85Ge0.15 film with a narrow energy bandgap easily induces more carrier charges in its channel [85]. However, the narrow energy bandgap also induces a large leakage current so that the ON/OFF current ratio (ION/IOFF) of the poly-Si0.85Ge0.15 TFT is not large as the other samples. The control sample (DN = 0 cm^-2) in this work has the same characteristics compared to the LaAlO3 poly-Si TFT, expect the threshold voltage. In ref. [86], the authors integrate the aluminum metal gate with a low work function value into their LaAlO3 poly-Si TFT, but the aluminum (Al) metal gate is deposited after the dopant activation is complete. In this work, we use the refractory metal of TaN as the metal gate, which could sustain an activation temperature of 600 °C to achieve the self-align implantation process. However, the work function of the TaN metal is around 4.5 eV higher than that of the Al metal of around 4 eV.

Therefore, our threshold voltage of the control sample is slightly larger than that of the LaAlO3 poly-Si TFT. In this work, the LTPS TFTs with 42-nm Pr2O3 gate dielectric has an equivalent-oxide thickness (EOT) of 8 nm. Because of the roughness of poly-Si and the fast deposition rate of TEOS oxide, the conventional LTPS TFTs with 8-nm TEOS gate dielectric is difficult to fabricate and it would cause large gate leakage current during operation. Finally,

as regards the Pr2O3 poly-Si TFTs with various nitrogen dosages, their threshold swings are controlled within 300 mV, which verify the well gate controllability due to the integration of the high-κ gate dielectric process. The Pr2O3 poly-Si TFT with an overdose nitrogen implantation has a poor crystallization on poly-Si channel film so that its mobility, threshold voltage, and ON/OFF current ratio are inferior to those of the other two devices in this work.

4.1-3 Summary

High-performance low-temperature polycrystalline silicon (LTPS) TFTs integrated nitrogen implantation and praseodymium oxide (Pr2O3) gate dielectric are demonstrated in this section. High gate capacitance density (~ 432 nF/cm²) and high breakdown electrical field

High-performance low-temperature polycrystalline silicon (LTPS) TFTs integrated nitrogen implantation and praseodymium oxide (Pr2O3) gate dielectric are demonstrated in this section. High gate capacitance density (~ 432 nF/cm²) and high breakdown electrical field

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