Fabrication of Low-Temperature Polycrystalline silicon Praseodymium Oxide

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The main fabrication steps of the low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) with a praseodymium oxide (Pr2O3) dielectric were summarized below and shown in Fig. 3-1. In modern liquid crystal display (LCD) industry, the amorphous silicon (α-Si) TFTs or the LTPS TFTs were fabricated on glass substrate as the switching devices in array cells. In our study, the 500-nm thermal oxide grown on 6-inch silicon wafer by using a horizontal furnace was used to simulate the glass substrate of active matrix liquid crystal display (AMLCD). And then, an undoped α-Si film with 50-nm thickness was deposited on the 500-nm thermal oxide by using a low-pressure chemical vapor deposition (LPCVD) system in silane (SiH4) ambient with a pressure of 350 mtorr at 560 °C. In addition,

before silicon oxidation, chemical vapor deposition (CVD), and high-κ deposition in this work, all samples were cleaned by using the traditional RCA process to remove any contamination, native oxide, and atomic scale roughness [96].

To explore the nitrogen effect on the re-crystallization, the nitrogen atoms with various dosages of zero (control sample), 5 × 10¹² cm^-2, and 5 × 10¹³ cm^-2, were implanted into the 50-nm α-Si film with an ion implantation energy of 10 keV, as presented in Fig. 3-1(a). The implantation energy of nitrogen atoms was set by 10 keV with a projected range about 25 nm to induce significant influence overall 50-nm α-Si film. After nitrogen implantation, the conventional solid-phase crystallization (SPC) annealing was processed at 600 °C for 24 hrs in nitrogen ambient to crystallize α-Si film into polycrystalline silicon (poly-Si) film. Such as traditional SPC annealing with the maximum process temperature limited at 600 °C was widely used to recrystallize amorphous silicon (α-Si) film due to its low-production cost and good grain-size uniformity.

Subsequently, the active regions of LTPS TFTs were lithographically patterned and then etched by using a transformer-coupled-plasma (TCP) dry etcher with a chlorine-based gas.

The edge of the active region must be formed an inclined and trapezoid shape because the latter high-κ gate insulator was deposited by using a physical vapor deposition (PVD) method, for its consideration to poor step coverage. Therefore, the exposure dosage and the focus offset should be fine trimmed to exposure the photoresist pattern in a trapezoid shape, and afterward the edge of the active region could become in a trapezoid shape during an anisotropic dry etching process. After removing residue photoresist and performing RCA cleaning process on the poly-Si film, the high-κ praseodymium oxide (Pr2O3) was deposited as the gate insulator by using an electron-beam evaporation system. The working pressure and the deposition rate were controlled within 5 × 10^-5 torr and 0.05 nm/sec, respectively. In order to improve the quality of gate insulator, the praseodymium oxide as the gate dielectric was subjected to a rapid thermal annealing (RTA) process at 600 °C for 1 minute in oxygen

ambient, as shown in Fig. 3-1(b).

After the gate dielectric formation, a 200-nm tantalum nitride (TaN) film was deposited in N2/(Ar+N2) = 5 % ambient at 600 mtorr with a DC power of 500 watt by using a reactive sputter system. Such refractory TaN metal with a resistance to acid-and-oxidation was applicable to gate electrode of thin-film transistor. Next, the TaN metal gate with a thickness of 200 nm was also defined by using a transformer-coupled-plasma (TCP) etcher with a chlorine-based gas, and it could be completely etched within 1 minute. However, the etching rates of the praseodymium oxide layer and I-line photoresist were approximate 0.1 nm/sec and 3 nm/sec, respectively, so that the I-line photoresist with 800-nm thickness could not protect the TaN metal gate if the 42-nm Pr2O3 dielectric was completely removed. Therefore, such dry etching process was capable of stopping on the praseodymium oxide layer while the TaN gate was completely removed, and we took account of the other etching process to remove this Pr2O3 dielectric for the following interconnection.

As displayed in Fig. 3-1(c), phosphorus atoms were self-aligned implanted through the praseodymium oxide layer into the 50-nm poly-Si film with the dosage and the energy of 5 × 10¹⁵ cm^-2 and 90 keV, respectively, to form the source and drain regions of LTPS TFTs. And then, the phosphorus dopants in source and drain regions were activated by using a rapid thermal annealing (RTA) process at 600 °C for 1 minute in nitrogen ambient. Afterwards, the 300-nm tetraethoxylsilane (TEOS) oxide film used as an inter-layer dielectric (ILD) layer was deposited by using a plasma-enhanced chemical vapor deposition (PECVD) system at 300 °C.

Because the praseodymium oxide could not be effectively etched by using a dry etching process, the contact holes were opened by a two-step contact etching process for interconnection, as illustrated in Fig. 3-1(d). Firstly, the 300-nm ILD passivation layer on the source and drain regions was removed by using a wet etching process with a buffered oxide etch (BOE) solution or a dry etching process with a fluorine-based gas. Secondly, the mixed solution of H3PO4: HNO3: CH3COOH: H2O = 50: 2: 10: 9 heated to 60 °C was used to

dissolve the praseodymium oxide film with a high etching selectivity to the ILD passivation layer, the TaN gate metal, and the source and drain regions of poly-Si film. Consequently, the praseodymium oxide film could be completely removed by an over etching. In fact, in this wet etching procedure, the lanthanide-series metal oxides, such as terbium oxide (Tb2O3) or dysprosium oxide (Dy2O3), could be removed by this mixed solution with a stable etching rate of 0.4 ~ 0.5 nm/sec, except for lanthanum oxide (La2O3). The etching rate of the lanthanum oxide by using this mixed solution was so quick (larger than 200 nm/sec) that the gate dielectric of the La2O3 film would be etched over through the channel region of the transistor device. Accordingly, this mixed solution should be diluted or changed with the other recipes for etching La2O3 film.

After the contact holes were opened by this two-step wet etching process, the 500-nm aluminum (Al) film was deposited at 600 mtorr with a DC power of 1500 watt by using a reactive sputter system. Finally, the aluminum pads were lithographically patterned, and subsequently etched by using a TCP metal etcher, and then the nitrogenous poly-Si TFTs with the (Pr2O3) gate dielectric were accomplished, as indicated in Fig. 3-1(e). For comparison, the control Pr2O3 poly-Si TFT without nitrogen implantation (DN = 0) was also prepared by the same process flow. In addition, note that all Pr2O3 poly-Si TFTs had no extra plasma treatment to passivate the trap states in active channel [7], [8] in this work. In order to verify the electrical properties of the praseodymium oxide (Pr2O3) film, the Pr2O3 metal-insulator-silicon (MIS) capacitors were also fabricated together with the same LTPS TFTs process, including the deposition and the annealing of the high-κ dielectric. For the Pr2O3 MIS capacitor fabrication, a shadow mask was used to define the top TaN electrode in a circle pattern with a radius of 220 μm. The bottom aluminum electrode was also deposited after the native oxide on the backside substrate was wiped out by using a buffered oxide etching (BOE) solution.