Chapter 5 Conclusion and Future Prospects
5.2 Future Prospects
In this work, we use electron-beam evaporation system to deposit the high-κ gate dielectrics because of our budget and flexible research consideration. But, in flat panel display (FPD) industry, electron-beam evaporation is not a suitable process for large size panel fabrication. The thin-film deposition process of LTPS TFTs in industry is usually unitizing plasma enhanced chemical vapor deposition (PECVD) system or reactive sputter system. The praseodymium (Pr) target with oxygen reaction by sputter system could be used to deposit the high-κ dielectric on active channel layer of LTPS TFT. Furthermore, the praseodymium oxide thin film could be formed by using a thermal decomposition of praseodymium complex, such as Pr2(CO3)3⋅8H2O [122] or Pr(NO3)3⋅6H2O [123]. Such sol-gel process with spin-coating high-κ dielectric layer on active channel layer of LTPS TFT is more suitable for large size panel fabrication. On the other hand, the sol-gel method is also easy applying on OTFT process. The precursor of the LaYOX could be spun on the large area of panel or sprayed in allocated active region of OTFT. The industry usually uses ink-jet method to define device area of OTFT without lithography, which is compatible with sol-gel method of high-κ dielectric. Therefore, no matter LTPS TFT or OTFT, the sol-gel method provides a convenient
way to deposit the high-κ dielectrics, and it is worthy to develop in the industry process.
In this work, we use the LaYOX dielectric with large bandgap (Eg) as the insulator of OTFT device to reduce gate leakage current. Besides, the high-κ LaYOX film has been proposed to solve the moisture absorption problem [80]. The OTFT also need the passivation layer on active channel layer because the organic channel layer is easily affected by environmental condition. Therefore, if the anti-absorbent LaYOX film is use as the passivation layer onto organic active channel to isolate outside moisture; the reliability of OTFT could be improved. The more electrical tests on OTFT could be performed without absorbent limitation.
On the other hand, the LaYOX film with large Eg is also a suitable gate dielectric for n-type and p-type LTPS TFT devices. Because the maximum process temperature is controlled within 600 °C, the LaYOX film has structural phase transformation to increase κ-value to 29 [81]. The thicker physical thickness under the same EOT could be fabricated, and the reliability of LTPS TFT device is also improved.
As the mention in chapter 2, the saturation field-effect mobility (μFE,sat) of OTFT is dependent on the operational voltages (drain and gate voltages). In fact, the 2-V operational voltage for the OTFT with 30-nm LaYOX gate insulator is a safety voltage with a little hysteresis and enough driving current. As the thickness of the high-κ gate insulator is increased, the higher drain voltage could be applied on OTFT without stress degradation and help drain out the accumulation charges in active channel to enhance the saturation field-effect mobility. To maintain the same accumulation charges (Qacc) in active channel, the gate voltage (VGS) must be increased with the decreased gate capacitance density (Cins).
However, the gate and drain voltages could not be increased with the same ratio because the limitation of breakdown voltage at the drain side, which depends on the addition of these two applied voltages. Therefore, the OTFTs with various thickness of the high-κ gate insulator could be fabricated, and the relationships among the saturation field-effect mobility, the drain voltage, and the gate voltage could be established to model the electrical characteristics of
OTFTs.
R
EFERENCES[1] T. Suzuki, “Flat panel display for ubiquitous product applications and related impurity doping technology,” J. Appl. Phys., vol. 99, no. 6, pp. 11101-1-11101-15, June 2006.
[2] G. Gu, G. Parthasarathy, P. E. Burrows, P. Tian, I. G. Hill, A. Kahn, and S. R. Forrest,
“Transparent stacked organic light emitting devices. I. design principles and transparent compound electrodes,” J. Appl. Phys., vol. 86, no. 8, pp. 4067-4075, Oct.
1999.
[3] L. Zhou, A. Wanga, S.-C. Wu, J. Sun, S. Park, and T. N. Jackson, “All-organic active matrix flexible display,” Appl. Phys. Lett., vol. 88, pp. 083502-1-083502-3, 2006.
[4] T. Noguchi, A. T. Tang, J. A. Tsai, and R. Reif, “Comparison of effects between large-area-beam ELA and SPC on TFT characteristics,” IEEE Trans. Electron Devices, vol. 43, no. 9, pp. 1454-1458, Sept. 1996.
[5] M. A. Crowder, P. G. Carey, P. M. Smith, R. S. Sposili, H. S. Cho, and J. S. Im,
“Low-temperature single-crystal Si TFTs fabricated on Si films processed via sequential lateral solidification,” IEEE Electron Device Lett., vol. 19, no. 8, pp.
306-308, Aug. 1998.
[6] M. Tai, M. Hatano, S. Yamaguchi, T. Noda, S.-K. Park, T. Shiba, and M. Ohkura,
“Performance of poly-Si TFTs fabricated by SELAX,” IEEE Trans. Electron Devices, vol. 51, no. 6, pp. 934-939, June 2004.
[7] I.-W. Wu, T.-Y. Huang, W. B. Jackson, A. G. Lewis, and A. Chiang, “Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation,” IEEE Electron Device Lett., vol. 12., no. 4, pp. 181-183, Apr. 1991.
[8] F.-S. Wang, M.-J. Tsai, and H.-C. Cheng, “The effects of NH3 plasma passivation on polysilicon thin-film transistors,” IEEE Electron Device Lett., vol. 16, no. 11, pp.
530-505, Nov. 1995.
[9] H.-L. Chen and C.-Y. Wu, “A new I-V model considering the impact-ionization effect initiated by the DIGBL current for the intrinsic n-channel poly-Si TFTs,” IEEE Trans.
Electron Devices, vol. 46, no. 4, pp. 722-725, Arp. 1999.
[10] K.-F. You and C.-Y. Wu, “A new quasi-2-D model for hot-carrier band-to-band tunneling current,” IEEE Trans. Electron Devices, vol. 46, no. 6, pp. 1174-1197, June 1999.
[11] K. Tanaka, H. Arai, and S. Kohda, “Characteristics of offset-structure polycrystalline-silicon thin-film transistors,” IEEE Electron Device Lett., vol. 9, no. 1, pp. 23-25, Jan. 1988.
[12] A. A. Orouji and M. J. Kumar, “Leakage current reduction techniques in poly-Si TFTs for active matrix liquid crystal displays: a comprehensive study,” IEEE Trans. Device and Mater. Reliabil., vol. 6, no. 2, pp. 315-325, June 2006.
[13] H. Sirringhaus, S. D. Theiss, A. Kahn, and S. Wagner, “Self-passivated copper gates for amorphous silicon thin-film transistors,” IEEE Electron Device Lett., vol. 16, no. 8, pp. 388-390, Aug. 1997.
[14] T.-S. Chang, T.-C. Chang, P.-T. Liu, C.-H. Tu, and F.-S. Yeh, “Improvement of hydrogenated amorphous-silicon TFT performances with low-k siloxane-based hydrogen silsesquioxane (HSQ) passivation layer,” IEEE Electron Device Lett., vol. 27, no. 11, pp. 902-904, Nov. 2006.
[15] M.-D. Ker, C.-K. Deng, and J.-L. Huang, “On-panel output buffer with offset compensation technique for data driver in LTPS technology,” IEEE J. Disp. Tech., vol.
2, no. 2, pp. 153-159, June 2006.
[16] C.-P. Lin, B.-Y. Tsui, M.-J. Yang, R.-H. Huang, and C.-H. Chien, “High-performance poly-silicon TFTs using HfO2 gate dielectric,” IEEE Electron Device Lett., vol. 27, no.
5, pp. 360-362, May 2006.
[17] D. Li, E.-J. Borkent, R. Nortrup, H. Moon, H. Katz, and Z. Baoa, “Humidity effect on electrical performance of organic thin-film transistors,” Appl. Phys. Lett., vol. 86, pp.
042105-1-042105-3, 2005.
[18] S. H. Han, J. H. Kim, J. Janga, S. M. Cho, and M. H. Oh, “Lifetime of organic thin-film transistors with organic passivation layers,” Appl. Phys. Lett., vol. 88, pp.
073519-1-073519-3, 2006.
[19] C.-W. Chu, S.-H. Li, C.-W. Chen, V. Shrotriya, and Y. Yanga, “High-performance organic thin-film transistors with metal oxide/metal bilayer electrode,” Appl. Phys.
Lett., vol. 87, pp. 193508-1-193508-3, 2005.
[20] Y.-J. Lin, Y.-C. Li, T.-C. Wen, L.-M. Huang, Y.-K. Chen, H.-J. Yeh, and Y.-H. Wang,
“Improvement of transparent organic thin film transistor performance by inserting a lithium fluoride buffer layer,” Appl. Phys. Lett., vol. 87, pp. 043305-1-043305-3, 2008.
[21] C. D. Dimitrakopoulos and D. J. Mascaro, “Organic thin-film transistors: a review of recent advances,” IBM J. Res. & Dev., vol. 45, no. 1, pp. 11-27, Jan. 2001.
[22] A. Salleo, M. L. Chabinyc, R. A. Street, M. S. Yang, “Polymer thin-film transistors with chemically modified dielectric interfaces,” Appl. Phys. Lett., vol. 81, no. 23, pp.
4383-4385, 2002.
[23] A. L. Deman and J. Tardy, “PMMA-Ta2O5 bilayer gate dielectric for low operating voltage organic FETs,” Org. Electron., vol. 6, pp. 78-84, 2005.
[24] W.-Y. Chou, C.-W. Kuo, H.-L. Cheng, Y.-R. Chen, F.-C. Tang, F.-Y. Yang, D.-Y. Shu, and C.-C. Liao, “Effect of surface free energy in gate dielectric in pentacene thin-film transistors,” Appl. Phys. Lett., vol, 89, pp. 112126-1-112126-3, 2006.
[25] C. D. Dimitrakopoulos, I. Kymissis, S. Purushothaman, D. A. Neumayer, P. R.
Duncombe, and R. B. Laibowitz, “Low-voltage, high-mobility pentacene transistors with solution-processed high dielectric constant insulators,” Adv. Mater., vol. 11, pp.
1372-1375, 1999.
[26] S. S. Kim, “Fundamentals of active-matrix liquid-crystal displays,” SID01 Short Course (S-2), June 3, 2001.
[27] B. J. Lechner, F. J. Marlowe, E. O. Nester, and J. Tults, “Liquid crystal matrix display,”
Proc. of the IEEE, vol. 59, no. 11, pp. 1566-1597, Nov. 1971.
[28] P. K. Weimer, “The TFT – A new thin-film transistor,” Proc. of the IRE, pp. 1462-1469, June 1962.
[29] P. K. Weimer, “A p-type tellurium thin-film transistor,” Proc. of the IEEE, pp. 608-610, May 1964.
[30] P. G. LeComber, W. E. Spear, and A. Ghaith, “Amorphous silicon field-effect device and possible application,” Electron. Lett., vol. 15, no. 6, pp.179-181, June 1979.
[31] F. Funada, Y. Takafuji, K. Yano, H. Take, and M. Matsuura, “An amorphous-Si TFT addressed 3.2-in. full-color LCD,” in SID, Dig. Tech. Papers, 1986, pp. 293-295.
[32] H. Moriyama, H. Uchida, S. Nishida, H. Nakano, Y. Hirai, S. Kaneko, and C. Tani,
“12-in full-color a-Si:H TFT with pixel electrode buried in gate insulator,” in SID, Dig.
Tech. Papers, 1989, pp. 144-146.
[33] S. W. Depp, A. Juliana, and B. G. Huth, “Polysilicon FET devices for large area input/output applications,” in IEDM Tech. Dig., 1980, pp. 703-706.
[34] Y. Oana, “A 240 × 360 element active matrix LCD with integrated gate-bus drivers using poly-Si TFTs,” in SID, Dig. Tech. Papers, 1984, pp. 312-315.
[35] S. Morozumi, R. Araki, H. Ohshima, M. Matsuo, T. Nakazawa, and T. Sato,
“Low-temperature processed poly-Si TFT and its application to large-area LCD,” in Japan Display 86, 1986, pp. 196-199.
[36] T. W. Little, H. Koike, K. Takahara, T. Nakazawa, and H. Ohshima, “A 9.5-inch 1.3-Megapixel low-temperature poly-Si TFT LCD fabricated by SPC of very thin film and an ECR-CVD gate insulator,” in Conf. Record 1991, Int. Disp. Res. Conf., 1991, pp. 219-222.
[37] Y. Kawazu, H. Kudo, S. Onari, and T. Arai, “Low-temperature crystallization of hydrogenated amorphous silicon induced by nickel silicide formation,” Jpn. J. Appl.
Phys. Part1, vol. 29, no. 12, pp. 2698-2704, Dec. 1990.
[38] Z. Jin, K. Moulding, H. S. Kwok, and M. Wong, “The effect of extended heat treatment on Ni induced lateral crystallization of amorphous silicon thin film,” IEEE Trans.
Electron Devices, vol. 46, no. 1, pp. 78-82, Jan 1999.
[39] Y. F. Tang, S. R. P. Silva, and M. J. Rose, “Super sequential lateral growth of Nd:YAG laser crystallized hydrogenated amorphous silicon,” Appl. Phys. Lett., vol. 78, no. 2, pp.
186-188, Jan. 2001.
[40] A. Hara, F. Takeuchi, M. Takei, K. Suga, K. Yoshino, M. Chida, Y. Sano, and N.
Sasaki,” High-performance polycrystalline silicon thin film transistors on non-alkali glass produced using continuous wave laser lateral crystallization,” Jpn. J. Appl. Phys., vol. 41, no. 3, pp. L311-L313, Mar. 2002.
[41] M. Pope and C. E. Swenberg, Electronic Processes in Organic Crystals, New York:
Oxford University Press, 1982.
[42] C. K. Chiang, C. R. Fincher, Y. W. Park, A. J. Heeger, H. Shirakawa, E. J. Lowis, S. C.
Gau, and A. G. Mecdiarmid, “Electrical conductivity in doped polyacetylene,” Phys.
Rev. Lett., vol. 39, no. 17, pp.1098-1101, Oct. 1977.
[43] F. Ebisawa, T. Kurokawa, and S. Nara, “Electrical prosperities of polyacetylene /polysiloxane interface,” J. Appl. Phys., vol. 54, no. 6, pp. 3255-3259, June 1983.
[44] P. K. Weimer, Physics of Thin Film, New York: Academic Press, 1964, pp. 147-150.
[45] G. Horowitz, “Organic field-effect transistors,” Adv. Matter., vol. 10, no. 5, pp. 365-377, 1998.
[46] D. J. Gundlach, Y. Y. Lin, T. N. Jackson, S. F. Neson, and D. G. Schlom, “Pentacene organic thin film transistor: molecular ordering and mobility,” IEEE Electron Device Lett., vol. 18, no. 3, pp. 87-89, Mar. 1997.
[47] S. F. Nelson, Y. Y. Lin, D. J. Gundlach, and T. N. Jackson, “Temperature-independent transport in high-mobility pentacene,” Appl. Phys. Lett., vol. 72, no. 15, pp. 1854-1857, 1998.
[48] I. G. Hill, A. Rajagopal, A. Kahna, and Y. Hu, “Molecular level alignment at organic semiconductor-metal interfaces,” Appl. Phys. Lett., vol. 73, no. 5, pp. 662-664, 1998.
[49] F. Garnier, “Thin-film transistors based on organic conjugated semiconductors,” Chem.
Phys., vol. 227, pp. 253-262, 1998.
[50] N. C.-C. Lu, L. Gerzberg, C.-Y. Lu, and J. D. Meindl, “A conduction model for semiconductor-grain-boundary-semiconductor barriers in polycrystalline-silicon film,”
IEEE Trans. Electron Devices, vol. 30, no.2, pp. 137-149, Feb. 1983.
[51] A. Mimura, N. Konishi, K. Ono, J. Ohwada, Y. Hosokawa, Y. Ono, T. Suzuki, K.
Miyata, and H. Kawakami, “High performance low-temperature poly-Si n-channel TFTs for LCD,” IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 351-359, Feb. 1989.
[52] A. Nakamura, F. Emoto, E. Fujji, Y. Uemoto, A. Yamamoto, K. Senda, and G. Kano,
“Recrystallization mechanism for solid phase growth of poly-Si films on quartz substrate,” Jpn. J. Appl. Phys., vol. 27, no. 12, pp. L2408-L2410, Dec. 1988.
[53] E. Adachi, T. Aoyama, N. Konishi, T. Suzuki, Y. Okajima, and K. Miyata, “TEM observations of initial crystallization states for LPCVD Si films,” Jpn. J. Appl. Phys., vol. 27, no. 10, pp. L1809-L1811, Oct. 1988.
[54] L. Haji, P. Joubert, J. Stoemenos, and N. A. Economou, “Mode of growth and microstructure of polycrystalline silicon obtained by solid-phase crystallization of an amorphous silicon film,” J. Appl. Phys., vol. 75, no. 8, pp. 3944-3952, Apr. 1994.
[55] E. F. Kennedy, L. Csepregi, J. W. Mayer, and T. W. Sigmon, “Influence of 16O, 12C, 14N, and noble gases on the crystallization of amorphous Si layers,” J. Appl. Phys., vol. 48, no. 10, pp. 4241-4246, Oct. 1977.
[56] I.-W. Wu, A. Chiang, M. Fuse, L. Ovecoglu, and T.-Y. Huang, “Retardation of
nucleation rate for grain size enhancement by deep silicon ion implantation of low-temperature chemical vapor deposited amorphous silicon film,” J. Appl. Phys., vol.
65, no. 10, pp. 4036-4039, May 1989.
[57] I.-W. Wu, W. B. Jackson, T.-Y. Huang, A. G. Lewis, and A. Chiang, “Mechanism of device degradation in n- and p-channel TFT’s by electrical stressing,” IEEE Electron Device Lett., vol. 11, no. 4, pp. 167-170, Apr. 1990.
[58] H.-N. Chern, C.-L. Lee, and T.-F. Lei, “The effects of fluorine passivation on polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 41, no.5, pp.
698-702, May 1994.
[59] S.-D. Wang, W.-H. Lo, and T.-F. Lei, “CF4 plasma treatment for fabricating high-performance and reliable solid-phase-crystallized poly-Si TFTs,” J. Electronchem.
Soc., vol. 152, no. 9, pp. G703-G706, 2005.
[60] C.-W. Lin, M.-Z. Yang, C.-C. Yeh, L.-J. Cheng, T.-Y. Huang, H.-C. Cheng, H.-C. Lin, T.-S. Chao, and C.-Y. Chang, “Effect of plasma treatments, substrate types, and crystallization methods on performance and reliability of low temperature polysilicon TFTs,” in IEDM Tech. Dig., 1999, pp. 305-308.
[61] M.-W. Ma, C.-Y. Chen, C.-J. Su, W.-C. Wu, Y.-H. Wu, T.-Y. Yang, K.-H. Kao, T.-S.
Chao, and T.-F. Lei, “Impacts of fluorine ion implantation with low-temperature with low-temperature solid-phase crystallized activation on high-κ LTPS-TFT,” IEEE Electron Devices Lett., vol. 29, no. 2, pp. 168-170, Feb. 2008.
[62] J. Robertson, “Band offsets of high dielectric constant gate oxides on silicon,” J.
Non-Crystalline Solids, vol. 303, no. 1, pp. 94-100, 2002.
[63] H. Osten, E. Bugiel, and A. Fissel, “Epitaxial praseodymium oxide: a new high-K dielectric,” Solid-State Electron., vol. 47, pp. 2161-2165, 2003.
[64] International Technology Roadmap for Semiconductors, http://public.itrs.net/, 9.1.
2006.
[65] K. J. Hubbard and D. G. Schlom, “Thermodynamic stability of binary oxides in contact with silicon,” Mater. Res., vol. 11, no.11, pp. 2757-2776, Nov. 1996.
[66] Y.-C. Yeo, T.-J. King, and C. Hu, “Direct tunneling leakage current and scalability of alternative gate dielectrics,” Appl. Phys. Lett., vol. 81, no. 11, pp. 2091-2093, Sept.
2002.
[67] G. V. S. Rao, S. Ramdas, P. N. Mehrotra, and C. N. R. Rao, “Electrical transport in rare-earth oxides,” J. Solid State Chem., vol. 2, no. 3, pp. 377-384, Nov. 1970.
[68] A. Prokofiev, A. Sheykh, and B. Melekh, “Periodicity in the band gap variation of Ln2X3 (X=O, S, Se) in the lanthanide series,” J. Alloys and Compounds, vol. 242, pp.
41-44, 1996.
[69] L. Eyring and N. C. Banziger, “On the structure and related properties of the oxide of praseodymium,” J. Appl. Phys., vol. 33, no. 1, pp. 428-433, Jan. 1962.
[70] G. Adachi and N. Imanaka, “The binary rare earth oxides,” Chem. Rev., vol. 98, no. 4, pp. 1479-1514, 1998.
[71] H. J. Osten, J.-P. Lui, P. Gaworzewski, E. Bugiel, and P. Zaumseil, “High-k gate dielectric with ultra-low leakage current based on praseodymium oxide,” in IEDM Tech. Dig., 2000, pp. 653-656.
[72] D. K. Fork, D. B. Fenner, and T. H. Geballe, “Growth of epitaxial PrO2 thin films on hydrogen terminated Si (111) by pulsed laser deposition,” J. Appl. Phys., vol. 68, no. 8, pp. 4316-4318, Oct. 1990.
[73] E. J. Tarsa, J. S. Speck, and M. Robinson, “Pulsed laser deposition of epitaxial silicon/h-Pr2O3/silicon heterostructures,” Appl. Phys. Lett., vol. 63, no. 4, pp. 539-541, July 1993.
[74] R. L. Nigro, R. G. Toro, G. Malandrino, I. L. Fragala, P. Rossi, and P. Dapporto, “Study of the thermal properties of Pr(III) precursors and their implementation in the MOCVD growth of praseodymium oxide films,” J. Electrochem. Soc., vol. 151, no. 9, pp.
F206-F213, 2004.
[75] A. Fissel, J. D. Dabrowski, H. J. H. J. Osten, “Photoemission and ab initio theoretical study of interface and film formation during epitaxial growth and annealing of praseodymium oxide on Si (001),” J. Appl. Phys., vol. 91, no. 11, pp. 8986-8891, June 2002.
[76] H. J. Osten, E. Bugiel, J. Dabrowski, A. Fissel, T. Guminskaya, J.-P. Lui, P.
Gaworzewski, and P. Zaumseil, “Epitaxial praseodymium oxide: A new high-k dielectric,” in Proc. Int. Workshop on Gate Insulator (IWGI) 2001, pp. 100-106.
[77] W. Zhu, T.-P. Ma, T. Tamagawa, Y. Di, J. Kim, R. Carruthers, M. Gibson, and T.
Furukawa, “HfO2 and HfAlO for CMOS: thermal stability and current transport,”
IEDM Tech. Dig., 2001, pp. 463-466.
[78] Y. Yamamoto, K. Kita, and A. Toriumi, “Structural and electrical properties of HfLaOx films for an amorphous high-k gate insulator,” Appl. Phys. Lett., vol. 89, no. 3, pp.
032903-1-032903-3, 2006.
[79] K. Kita, K. Kyuno, and A. Toriumi, “Permittivity increase of yttrium-doped HfO2
through structural phase transformation,” Appl. Phys. Lett., vol. 86, no. 10, pp.
102906-1-102906-3, 2005.
[80] Y. Zhao, K. Kita, K. Kyuno, and A. Toriumi, “Higher-k LaYOx films with strong moisture robustness,” Appl. Phys. Lett., vol. 89, pp. 252905-1-252905-3, 2006.
[81] Y. Zhao, K. Kita, K. Kyuno, and A. Toriumi, “Bandgap enhance and electrical properties of La2O3 film doped with Y2O3 as high-k gate insulator,” Appl. Phys. Lett., vol. 94, pp. 042901-1-042901-3, 2009.
[82] C.-K. Yang, C.-L. Lee, and T.-F. Lei, “Enhanced H2-plasma effects on polysilicon thin-film transistors with thin ONO gate-dielectrics,” IEEE Electron Device Lett., vol.
16, no. 6, pp. 228-229, June 1995.
[83] J.-W. Lee, N.-I. Lee, J.-I. Han, and C.-H. Han, “Characteristics of polysilicon thin-film
transistor with thin-gate dielectric grown by electron cyclotron resonance nitrous oxide plasma,” IEEE Electron Device Lett., vol. 18, no. 5, pp. 172-174, May 1997.
[84] M.-Y. Um, S.-K. Lee, and H.-J. Kim, “Characterization of thin film transistor using Ta2O5 gate dielectric,” in Proc. Int. Workshop AM-LCD, 1998, pp. 45-48.
[85] Z. Jin, H. S. Kwok, and M. Wong, “High-performance polycrystalline SiGe thin-film transistors using Al2O3 gate insulators,” IEEE Electron Device Lett., vol. 19, no. 12, pp.
502-504, Dec. 1998.
[86] B.-F. Hung, K.-C. Chiang, C.-C. Huang, A. Chin, and S. P. McAlister,
“High-performance poly-silicon TFTs incorporating LaAlO3 as the gate dielectric,”
IEEE Electron Device Lett., vol. 26, no. 6, pp. 384-386, June 2005.
[87] S. J. Kang, K. B. Chung, D. S. Park, H. J. Kim, Y. K. Choi, M. H. Jang, M. Noh, and C.
N. Whang, “Fabrication and characterization of the pentacene thin film transistor with a Gd2O3 gate insulator,” Synth. Metals, vol. 146, pp. 351-354, 2004.
[88] Y. Liang, G. Dong, Y. Hu, L. Wang, and Y. Qiu, “Low-voltage pentacene thin-film transistors with Ta2O5 gate insulators and their reversible light-induced threshold voltage shift,” Appl. Phys. Lett., vol. 86, pp. 132101-1-132101-3, 2005.
[89] S. Yagniuma, J. Yamaguchi, K. Itaka, and H. Koinuma, “Pulsed laser deposition of oxide gate dielectrics for pentacene organic field-effect transistors,” Thin Solid Films, vol. 486, pp. 218-221, 2005.
[90] L. A. Majewski, R. Schroeder, and M. Grell, “One volt organic transistor,” Adv. Mater., vol. 17, no. 2, pp. 192-196, Jan. 2005.
[91] K. Kang, M.-H. Lim, H.-G. Kim, Y. Choi, and I.-D. Kim, and J.-M. Hong, “Mn-doped Ba0.6Sr0.4TiO3 high-k gate dielectric gate dielectric for low voltage organic transistor on polymer substrate,” Appl. Phys. Lett., vol. 87, pp. 242908-1-242908-3, 2005.
[92] M. Kitamura and Y. Arakawa, “High-performance pentacene thin-film transistors with high dielectric constant gate insulator,” Appl. Phys. Lett., vol. 89, pp.
223525-1-223525-2, 2006.
[93] H.-C. Pao and C.-T. Sah, “Effects of diffusion current on characteristics of metal-oxide (insulator)–semiconductor transistors,” Solid-State Electron., vol. 9, no. 10, pp.
927-937, May 1966.
[94] J. R. Brews, “A charge sheet model of the MOSFET,” Solid-State Electron., vol. 21, pp.
345-352, 1978.
[95] G. Horowitz, R Hajlaoui, H Bouchriha, R. Bourguiga, and M. Hajlaoui, “The concept of “threshold voltage” in organic field-effect transistors,” Adv. Mater., vol. 10, no. 12, pp. 923-927, Oct. 1998.
[96] S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Vol. 1: Process Technology, Lattice Press; 2rd Ed., 1999.
[97] Y.-K. Jeong, S.-J. Won, D.-K. Jwon, M.-W. Song, W.-H. Kim, O.-H. Park, J.-H. Jeong, H.-S. Oh, H.-K. Kang, and K.-P. Suh, “High quality high-k MIM capacitors by Ta2O5/HfO2/Ta2O5 multilayered dielectric and NH3 plasma interface treatments for mixed-signal/RF applications,” in Symp. VLSI Tech. Dig., 2004, pp. 222-223.
[98] K.-C. Chiang, C.-C. Huang, A. Chin, G.-L. Chen, W.-J. Chen, Y.-H. Wu, and S. P.
McAlister, “High-performance SrTiO3 MIM capacitors for analog applications,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2312-2319, Sept. 2006.
[99] C. D. Dimitrakopoulos, A. R. Brown, and A. Pomp, “Molecular beam deposited thin films of pentacene for organic field effect transistor applications,” J. Appl. Phys., vol.
80, pp. 2501-2508, 1996.
[100] I. V. K. Rao, S. Mandal, and M. Katiyar, “Effect of pentacene deposition rate on device characteristics of top contact organic thin film transistors,” Intl. Workshop on Phys. of Semiconductor Devices (IWPSD), 2007, pp. 625-627.
[101] S. J. Kang, M. Noh, D. S. Park, H. J. Kim, C. N. Whang, C. H. Chang, “Influence of postannealing on polycrystalline pentacene thin film transistor,” J. Appl. Phys., vol. 95,
pp. 2293-2296, 2004.
[102] D. L. Smith, Thin-Film Deposition: Principles and Practice, McGraw-Hill Professional; 1st Ed., 1995.
[103] H. Xiao, Introduction to Semiconductor Manufacturing Technology, Prentice Hall;
United States Ed., 2000.
[104] Material Safety Data Sheet (MSDS) of pentacene provided by Aldrich Chemical Company.
[105] Y. Zhao, K. Kita, K. Kyuno, and A. Toriumi, “Higher-k LaYOx films with strong moisture resistance,” Intl. Conf. on Solid-State and Integrated Circuit Tech. (ICSICT), 2006, pp. 427-429.
[106] A. Toriumi, K. Kita, K. Tomida, Y. Zhao, J. Widiez, T. Nabatame, H. Ota, and M.
Hirose, “Materials science-based device performance engineering for metal gate high-k CMOS,” in IEDM Tech. Dig., 2007, pp. 53-56.
[107] B. V. Crist, Handbook of Monochromatic XPS Spectra, The Elements of Native Oxides, Wiley, 2000.
[108] I.-W. Wu, W. B. Jackson, T.-Y. Haung, A. G. Lewis, and A. Chiang, “Mechanism of device degradation in n- and p-channel polysilicon TFT’s by electrical stressing,” IEEE Electron Device Lett., vol. 11, no. 4, pp. 74-76, Apr. 1990.
[109] M. Hack, A. G. Lewis, and I.-W. Wu, “Physical models for degradation effects in polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 40, no. 5, pp.
890-897, May 1993.
[110] F. V. Farmakis, J. Brini, G. Kamarinos, and C. A. Dimitriadis,“Anomalous turn-on voltage degradation during hot-carrier stress in polycrystalline silicon thin-film transistors,” IEEE Electron Device Lett., vol. 22, no. 2, pp. 74-76, Feb. 2001.
[111] M. Hack, I.-W. Wu, T. J. King, and A. G. Lewis, “Analysis of leakage currents in poly-silicon thin film transistors,” in IEDM Tech. Dig., 1993, pp. 385-388.