Benchmark of the ADC

採用Two-step 的架構以及切換式電容（Switched capacitor）的輸入級來做 電壓比較，這些方式都將使得 ADC 的消耗功率較低，但相對的其可達到 之最快操作頻率較慢，無法符合我們所需要的規格要求。

Table 6.3 Benchmark of state-of-the-art 6-bit ADCs

Type JSSC 02 Process 0.18μm 0.18μm 0.13μm 0.13μm 90nm 0.13μm Resolution 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits Sampling rate 1.6 GHz 2 GHz 4 GHz 1.2 GHz 1 GHz 6 GHz Power 340mW 310mW 990mW 160mW 55mW 655mW Power/GHz 212.5mW 155mW 247.5mW 133.3mW 55mW 109mW

Chapter 7

Conclusion and Future Works

本論文在不使用 time-interleaved 的架構下提出一 5GS/s 6-bit 的 ADC 與DAC 資料轉換器對之設計。在 ADC 的電路設計當中，T/H 電路使用了 turn-off dynamic MOS 的寄生電容來消除 hold-mode feedthrough。而比較器 陣列是利用averaging 和 interpolating 技巧來降低比較器的 offset 及輸入端 的負載寄生電容。其中前置放大器是參考 active-feedback 的架構，可有效 提升其增益頻寬積。數位電路的部分則是採用 CML 的邏輯閘，可在高速 的操作頻率下大幅抑制power-ground bouncing。另外也在 Clock 訊號路徑 上加入intentional timing skew buffers 來做 wave-pipelining，使得 Latch 能 在如此高速的取樣頻率下擷取到正確的資料。至於 DAC 電路設計部份，

Hybrid Thermometer Decoder 的應用可大幅縮減開關及電流源的數目，使其 寄生電容和Layout 複雜度降低。其中電流源是採用疊接方式設計，能擁有 較大的輸出阻抗。最後為了要能在如此高速的情況下對此晶片進行量測，

我們又額外設計一 DfT 電路，提供三種測試模式。其中測試模式三是將 ADC 和 DAC 串接起來，可在全速下進行量測。同時並可透過 ZOH 補償 之運算，推測得知此ADC 在最遭情況下的效能表現。

此組ADC 與 DAC 將應用於晶片系統內之串列傳輸鏈結。雖然我們在 量測時為了測試可行性之考量，是把ADC 串接 DAC；但實際應用上是將 DAC 置於發送端、ADC 置於接收端，所以是 DAC 串接 ADC。此時 DAC 內的輸出阻抗是50Ω，並上 ADC 的輸入阻抗同樣是 50Ω 後，DAC 的輸出 電流源所看到之負載仍為50//50=25Ω，符合我們的設計。

量測結果顯示，此組資料轉換器對的DNL 都小於± 0.2 LSB，INL 也 都小於± 0.5 LSB 以內。在 5GS/s 的取樣頻率下，輸入 0.5GHz 弦波訊號，

可得36.98 dB 的 SNR，但其 SNDR 和 SFDR 分別僅有 20.91 dB 和 24.17 dBc。不過此組資料轉換器對事實上可操作到 6GS/s 的高速取樣頻率。在 6GS/s 時同樣輸入 0.5GHz 的訊號，則輸出的 SNR 同樣可高達 36.977 dB，

SNDR 也只有 21.05 dB，SFDR 為 26.03 dBc。

使用的製程是TSMC 0.13μm CMOS Mixed-Signal RF process，ADC 和 DAC 所佔的面積分別為 0.56×0.7mm²和 0.28×0.2mm²。在 supply 電壓為 1.2V 下，整個晶片總功率消耗 770mW。

此組 ADC 和 DAC 資料轉換器對的 SNDR 和 SFDR 之所以會表現的 不盡理想，是因為我們的T/H 電路會使得如此高速又大擺幅的時脈訊號和 輸入訊號很容易造成Inter-Modulation，因而會在諧波頻率上產生相當大的 失真訊號，嚴重影響到SNDR 和 SFDR 值。所以未來可朝高速的 T/H 電路 進行研究，期望能不需使用 rail-to-rail 的時脈訊號即可驅動其工作，若是 如此能有效抑制調變失真、降低諧波訊號，則此組資料轉換器對之效能將 更加完美。

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