Ground Bounce - Traditional Output Buffer with Slew-Rate Control

Chapter 4 New 2xVDD-Tolerant I/O Buffer with Slew-Rate Control

4.2 Traditional Output Buffer with Slew-Rate Control

4.3.3 Ground Bounce

In order to verify the reduction of ground bounce by slew-rate control, a model for ground bounce effects is shown in Fig. 4.4. The inductance of wire bonds vary from 7nH to 15nH in the simulation for typical cases. Since the switching currents of 2xVDD-tolerant I/O buffer in transmit mode are much larger than that in receive mode, the ground bounce effects are simulated in transmit mode for clear illustration.

The simulation waveforms of ground bounce effects on power lines are shown in Fig.

4.5 and several parameters are defined as follows:

VDDH_ext / VDD_ext / VSS_ext : external power supply;

VDDH_max : maximum value of VDDH power line;

VSS_max : maximum value of VSS power line;

VDDH_min : minimum value of VDDH power line;

VSS_max : minimum value of VSS power line;

VDDH_over : overshot on VDDH power line (VDDH_max- VDDH_ext)

VDDH_under : undershot on VDDH power line (VDDH_ext- VDDH_min)

VSS_over : overshot on VSS power line (VSS_max- VSS_ext)

VSS_under : undershot on VSS power line (VSS_ext- VSS_min)

The VDDH_under and VSS_over among these parameters are the major concerns since these two terms may result in increasing timing delay and even logic errors on transmitted signals.

The simulation waveforms of the new 2xVDD-tolerant I/O buffer with slew-rate control which is operated in transmit mode with an operating speed of 133MHz are shown in Fig 4.6. The signals on I/O PAD are like sine wave with distortion due to the ground bounce effect. The simulation results with variation wire bond inductance on VDDH power line and VSS power line are shown in Fig. 4.7 and Fig. 4.8, respectively. Since the current supplied from VDD is much smaller than that from

VDDH, only ground bounce effect in VDDH is shown. As shown in Fig. 4.7 and Fig.

4.8, the slew-rate control circuit improves the ground bounce effects greatly.

I/O Circuit

LVDDH

LVDD

L^VSS VSS

VDD VDDH

VDDH_ext VDD_ext

Input Output

VSS_ext

Fig 4.4 Simulated model of ground bounce.

(a)

(b)

Fig 4.5 Simulation waveforms of ground bounce effects on (a) VDDH power line and (b) VSS power line.

Fig 4.6 Simulation waveforms of the 2xVDD-tolerant I/O buffer with slew-rate control for ground bounce effect in transmit mode.

Fig 4.7 The relation between ground bounce on VDDH power line and wire bond inductance on the new 2xVDD-tolerant I/O buffer with or without slew-rate control.

(a) The overshoot and (b) the undershoot on VDDH power line.

Fig 4.8 The relation between ground bounce on VSS power line and wire bond inductance on the new 2xVDD-tolerant I/O buffer with or without slew-rate control.

(a) The overshoot and (b) the undershoot on VSS power line.

Chapter 5 New 2xVDD-Tolerant I/O Buffer with PVT Compensation

5.1Introduction

In chapter 4, the new 2xVDD-tolerant I/O buffer with slew-rate control for ground bounce reduction has been discussed. Furthermore, to resist the slew-rate variation, the new 2xVDD-tolerant I/O buffer with PVT compensation will be illustrated in this chapter.

With the recent trend for high-speed interface, the sensitivity of circuits towards process, voltage and temperature (PVT) variation is hampering circuit performance and yield. For example, in the case of I/O pads it is difficult to meet the rise and fall times, current, power and ground bounce specifications across all PVT corners. Driver circuits are oversized to meet timing at slow corners. This causes high current and Simultaneous Switching Noise (SSN) at fast corners. Such effects degrade the reliability of the circuit and require considerable amount of design resources and time to meet circuit performance across PVT variation [18]. Therefore, recent interface specifications like UDMA 100 [19] are not only to limit the minimum or maximum value the timing specification but also require the slew rate keeping in a certain range.

In next section, a method of PVT compensation to make the output slew rate be kept as constant as possible will be illustrated.

5.2New 2xVDD-Tolerant I/O Buffer with PVT Compensation

Fig. 5.1 shows the design concept of the PVT compensation technique to keep the output slew rate of an I/O buffer within in a certain range [20]. As shown in Fig. 5.1, the PVT variation detector detects process, voltage, and temperature variations by sensing the reference clock in different conditions. Then the PVT variation detector will generate the corresponding pre-control signals to the encoder. The encoder using these pre-control signals to generate applicable control signals to the output stage of an I/O buffer. The drive strength of the output driver can be adjusted with these control signals to match the PVT variation. The detail implementation will be illustrated as following.

Fig 5.1 Block diagram of solution for PVT compensation.

5.2.1 PVT Variation Detector

The schematic of the PVT variation detector is shown in Fig. 5.2. First, the reference clock delivers the logic high into the delay chain. Then once the reference clock turns to logic low, the outputs of each delay cells will be load into the register.

Because the propagation delay of a delay cell depends on the process, voltage and temperature, the propagation delay determines how many the signals of logic high

will be load into the register. For example, in the fast condition, the signal of logic high can pass through many delay cells in a reference clock cycle. On the contrast, in the slow condition, most of the delay cells’ outputs will be logic low since the signal logic high has not been delivered to them when the reference clock turns to logic low.

As shown in Fig. 5.3, the register in Fig. 5.2 is implemented with the pulse triggered D flip-flop. Thus, the register loads data in the moment that the reference clock turns to logic low. Next the outputs of this register will be converted to the pre-control signals by several logic gates for convenient application in the output stage. For the new 2xVDD-tolerant I/O buffer with PVT compensation, the 2xVDD power supply variation should be sensed in the PVT variation detector. Therefore, the logic gates should be implemented with the 2xVDD-tolerant logic gates which will be illustrated in section 5.3.

Fig 5.2 The PVT variation detector.

Fig 5.3 The pulse triggered D flip-flop using as the register in the PVT variation detector.

5.2.2 Encoder

In order to control the segmented output driver which will be illustrated in next section conveniently, the pre-control signals from the PVT variation detector have to be encoded appropriately. Table 5.1 shows the truth table of encoder in the PVT compensation circuit. The D0-D7 are the pre-control signals from the PVT variation detector. All the situations that D0-D7 could be are listed in the truth table. In the fastest condition, the signals of D0-D7 are “00000001”. On the contrast, the signals of D0-D7 are “10000000” in the slowest condition. The pre-signals D0-D7 are encoded to the binary codes S0-S2. If signals of S0-S2 are logic high, it means that the corresponding segmented output driver is turned on. The implementation of this 8-to-3 encoder is shown in Fig. 5.4. Since the circuit is implemented with the 2xVDD-tolerant logic gates whose voltage swing is from 0V to 2xVDD, the outputs S0-S2 should be converted to S0H-S2H and S0L-S2L by the level converter for being used correctly in the output stage. The voltage swing of S0H-S2H is from VDD to 2xVDD and voltage swing of S0L-S2L is from 0V to VDD. As shown in Fig. 5.4, the level converter converts 0V-to-2xVDD signals to VDD-to-2xVDD and 0V-to-VDD signals. The detail implementation of this level converter will be illustrated in section 5.3.

Table 5.1

Truth table of Encoder in the PVT compensation circuit.

Fig 5.4 The circuit schematic of encoder.

5.2.3 Output Stage with Control Signals

The schematic of new 2xVDD-tolerant I/O buffer with PVT compensation is shown in Fig. 5.5. S0H-S2H and S0L-S2L are the PVT variation related signals which are generated from the PVT variation detector and the encoder. With the OR gates and AND gates shown in Fig. 5.5, the S0H-S2H and S0L-S2L can be used to determined the segmented output drivers to be turn on or turn off. Because the voltage swing of S0H-S2H is from VDD to 2xVDD, the voltage swing of OR gates is from VDD to 2xVDD. Similarly, because the voltage swing of S0L-S2L is from 0V to VDD, the voltage swing of AND gates is from 0V to VDD. Since S0H-S2H and S0L-S2L are binary codes and their weighting are S2H > S1H > S0H and S2L > S1L > S0L, the size weightings of these segmented output drivers are MPP2 > MPP1 > MPP0 and MNN2

> MNN1 > MNN0. The output transistors MPP and MNN are the basic output driver, so when the binary codes are “000” which happens in the slowest condition, only MPP and MNN will be used. Therefore, the size of MPP and MNN can be determined to match the driving capacity of typical condition in slowest condition. Next, the size of MPP1 and MNN1 can be determined to match the driving capacity of typical condition in the condition whose corresponding codes are “001”, because only MPP, MNN, MPP1 and MNN1 are used in this condition. Following such design strategy, the sizes of all the output drivers can be roughly determined. Note that the driving capacity is precise in the design point like “000” and “001” with such design strategy, but it will be a little oversized or undersized in other conditions like “011” or “101”.

However, the design strategy provides a way to grasp approximate trend of the size change of the output driver. The corresponding size ratios of the output drivers are shown in Table 5.2. Furthermore, the bits of the control signals can be extended to 4 bits or more. The 4-bit control signals example of the 2xVDD-tolerant I/O buffer with PVT compensation is shown in Fig. 5.6.

Fig 5.5 The schematic of new 2xVDD-tolerant I/O buffer with PVT compensation.

Table 5.2

The size ratios of the output driver.

Fig 5.6 The schematic of new 2xVDD-tolerant I/O buffer with PVT compensation of 4-bit control signals.

5.3Proposed 2xVDD-Tolerant Logic gate

In order to detect the 2xVDD power supply variation, the delay chain should be implemented with the 2xVDD-tolerant logic gates. For consistency, all the logic gates in the PVT variation detector are the structure of 2xVDD-tolerant logic gates. Of course, the voltage level of 2xVDD can be also shifted to VDD by a level converter and be dealt with normal logic gates. This paper just proposed a direct way by using the 2xVDD-tolerant logic gates to accomplish this work.

The voltage swing of inputs and outputs of the 2xVDD-tolerant logic gates are from 0V to 2xVDD. Fig. 5.7 shows the schematic of 2xVDD-tolerant inverter. As shown in Fig. 5.7, the signal IN whose voltage swing is from 0 to 2xVDD is converted to INH and INL. The voltage swing of INH is from VDD to 2xVDD and the

voltage swing of INL is from 0V to VDD. The output stage in the 2xVDD-tolerant inverter is the dynamic source structure which is proposed in chapter 3. MP and MN are the stacked structure to prevent the 2xVDD-tolerant inverter suffering gate-oxide overstress. MPP and MNN decide the function of this logic. MPN and MNP are used to bias node A and node B at safe voltage when MPP and MNN are turned off.

Fig 5.7 The 2xVDD-tolerant inverter.

The level converter shown in Fig. 5.8 is used to convert the voltage swing of 0V-to-2xVDD into VDD-to-2xVDD and 0V-to-VDD. As shown in Fig. 5.8, when the IN is 2xVDD, the MP1 is turned on while the MP2 is turned off, so the INH will be 2xVDD. On the other hand, the MN2 is turned on while MN1 is turned off, so the INL

will be VDD. When the IN is 0V, the MP2 is turned on while the MP1 is turned off, so the INH will be VDD. On the other hand, the MN1 is turned on while MN2 is turned off, so the INL will be 0V. Using such level converter can correctly control the dynamic source output stage which is shown in Fig. 5.7 without gate-oxide overstress.

Fig 5.8 The level converter being used in the 2xVDD-tolerant I/O logic gates and the encoder circuit which is shown in Fig. 5.4.

Fig. 5.9 shows the examples of 2-input 2xVDD-tolerant NAND gate and 2-input 2xVDD-tolerant NOR gate. As shown in Fig. 5.9 (a), the input A is converted to AH

and AL, and input B is converted to BH and BL by the level converter shown in Fig. 5.8.

Fig. 5.9 (b) shows the example of 2-input 2xVDD-tolerant NAND gate. MP and MN are the stacked structure to prevent the 2xVDD-tolerant inverter suffering gate-oxide overstress. MPP1 MPP2, MNN1 and MNN2 decide the function of this logic. MPN1 MPN2, MNP1 and MNP2 are used to bias node A and node B at safe voltage when node A and node B are floating. Note that if the function transistors (MNN1 and MNN2) are series structure, the biasing transistors (MNP1 and MNP2) will be the parallel structure. They are complementary structure. As well as if the function transistors (MPP1 and MPP2) are parallel structure, the biasing transistors (MPN1 and MPN2) will be the series structure. Fig. 5.9 (c) shows the example of 2-input 2xVDD-tolerant NOR gate. Similarly, MP and MN are the stacked structure to

prevent the 2xVDD-tolerant inverter suffering gate-oxide overstress. MPP1 MPP2, MNN1 and MNN2 decide the function of this logic. MPN1 MPN2, MNP1 and MNP2 are used to bias node A and node B at safe voltage when node A and node B are floating. Again, their function transistors and biasing transistors are the complementary structure. Basing on this design method, all the 2xVDD-tolerant logic gates can be implemented even the inputs are more than two. The implementations of the 3-input 2xVDD-tolerant NAND gate and NOR gate are shown in Fig. 5.10. As shown in Fig. 5.10 (a), there needs three level converters to convert the inputs A, B, and C. Fig. 5.10 (b) shows the example of 3-input 2xVDD-tolerant NAND gate and Fig. 5.10 (c) shows the example of 3-input 2xVDD-tolerant NOR gate. Using these 2xVDD-tolerant logic gates in the PVT compensation circuit can detect the variation of 2xVDD power line in a mixed-voltage I/O circuit.

(a)

(b) (c)

Fig 5.9 The implementations of 2-input 2xVDD-tolerant logic gates. (a) The inputs (b) NAND gate, and (c) NOR gate.

(a)

(b) (c)

Fig 5.10 The implementations of 3-input 2xVDD-tolerant logic gates. (a) The inputs (b) NAND gate, and (c) NOR gate.

5.4Simulation Results

The new 2xVDD-tolerant I/O buffer with PVT compensation has been verified in a 0.18μm CMOS process by SPICE simulation. In section 5.4.1, the slew rate variation will be compared with or without PVT compensation using 3-bits control signals. Furthermore, the control bits will be extended to 4 bits in order to increase the precision. The corresponding simulation results about the 4-bits control signals will be discussed in section 5.4.2.

5.4.1 Simulation Results with 3-bits control signals

Table 5.4 shows the simulated slew rate of the I/O PAD of the new 2xVDD-tolerant I/O buffer without PVT compensation. The definition of slew rate is

Trise is the rise time which is the time that I/O PAD pulls high from 0.1xVDDH to 0.9xVDDH and Tfall is the fall time which is the time that I/O PAD pulls down from 0.9xVDDH to 0.1xVDDH.

Table 5.3

The slew rate of the I/O PAD of the new 2xVDD-tolerant I/O buffer without PVT compensation.

The process variation in this simulation contains fast, normal and slow corner. The power supplies variations are from 0.9xVDD to 1.1xVDD and 0.9xVDDH to 1.1xVDDH. VDD is 1.5V and VDDH is 3.3V in typical condition. And the

temperature variation is from 0°C to 125°C. As shown in Table 5.3, the maximum SRrise variation is 2.86 V/nS and the maximum SRfall variation is 2.61 V/nS.

Table 5.4 is the shmoo plot of the outputs (S2, S1 and S0) of the 8-to-3 encoder. It can be discovered that when the condition becomes slower, the value of the binary codes will become larger. In the slowest condition, the binary codes is “ 111 ”. It means that the output driver is all turned on to compensate the slowest condition.

Table 5.4

The shmoo plot of the outputs of 8-to-3 encoder.

Table 5.4 shows the simulated slew rate of the I/O PAD of the new 2xVDD-tolerant I/O buffer with PVT compensation using 3-bits control signals. The maximum SRrise variation is 1.59 V/nS and the maximum SRfall variation is 1.48 V/nS. Comparing the simulations with or without PVT compensation, the new

2xVDD-tolerant I/O buffer with PVT compensation using 3-bits control signals has improved the SRrise variation of 44% and the SRfall variation of 43%.

Table 5.5

The slew rate of the I/O PAD of the new 2xVDD-tolerant I/O buffer with PVT compensation using 3-bits control signals.

5.4.2 Simulation Results with 4-bits control signals

In order to increase the compensation precision, the control bits are extended to 4 bits. It means that the pre-control signals D0-D7 in the PVT variation detector becomes D0-D15. And then the pre-control signals will be converted to the 4-bits binary codes by an 16-to-4 encoder. Of course, the output driver will be segmented into 4 parts to match the 4-bits control signals. The 4-bit control signals example of

the 2xVDD-tolerant I/O buffer with PVT compensation is shown in Fig. 5.6.

Table 5.6 is the shmoo plot of the outputs (S3, S2, S1 and S0) of the 16-to-4 encoder. Similarly, it can be discovered that when the condition becomes slower, the value of the binary codes will become larger.

Table 5.7 shows the simulated slew rate of the I/O PAD of the new 2xVDD-tolerant I/O buffer with PVT compensation using 4-bits control signals. The maximum SRrise variation is 1.26 V/nS and the maximum SRfall variation is 1.72 V/nS. Comparing the simulations with or without PVT compensation, the new 2xVDD-tolerant I/O buffer with PVT compensation using 3-bits control signals has improved the SRrise variation of 56% and the SRfall variation of 34%.

Table 5.6

The shmoo plot of the outputs of 16-to-4 encoder.

Table 5.7

The slew rate of the I/O PAD of the new 2xVDD-tolerant I/O buffer with PVT compensation using 4-bits control signals.

Comparing with the PVT compensation using 3-bits control signals, the performance of the new 2xVDD-tolerant I/O buffer with PVT compensation using 4-bits control signals has not improved clearly. The reason is that when the control signal bits number increase, each segmented output driver will become smaller. In such high operating frequency, the compensation of the small size segmented output driver is insignificance, especially for the smallest one. Moreover, the size change of the output driver does not match the PVT variation. Therefore, too much bits of control signal won’t make the performance better.

Chapter 6 Conclusions and Future Works

6.1Conclusions

A new 2xVDD-tolerant I/O buffer against gate-oxide overstress has been successfully designed and fabricated in a 0.18-mm 1.8-V CMOS process with only thin-oxide 1.8-V devices. Moreover, the gate-to-source, gate-to-drain, and drain-to-source voltages of all transistors in the new proposed 2xVDD-tolerant I/O buffer can be kept within the normal operating voltage range (VDD). This new 2xVDD-tolerant I/O buffer can receive 3.3-V input signals or transmit the 3.3-V

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