Simulation Results with 4-bits control signals

In order to increase the compensation precision, the control bits are extended to 4 bits. It means that the pre-control signals D0-D7 in the PVT variation detector becomes D0-D15. And then the pre-control signals will be converted to the 4-bits binary codes by an 16-to-4 encoder. Of course, the output driver will be segmented into 4 parts to match the 4-bits control signals. The 4-bit control signals example of

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the 2xVDD-tolerant I/O buffer with PVT compensation is shown in Fig. 5.6.

Table 5.6 is the shmoo plot of the outputs (S3, S2, S1 and S0) of the 16-to-4 encoder. Similarly, it can be discovered that when the condition becomes slower, the value of the binary codes will become larger.

Table 5.7 shows the simulated slew rate of the I/O PAD of the new 2xVDD-tolerant I/O buffer with PVT compensation using 4-bits control signals. The maximum SRrise variation is 1.26 V/nS and the maximum SRfall variation is 1.72 V/nS. Comparing the simulations with or without PVT compensation, the new 2xVDD-tolerant I/O buffer with PVT compensation using 3-bits control signals has improved the SRrise variation of 56% and the SRfall variation of 34%.

Table 5.6

The shmoo plot of the outputs of 16-to-4 encoder.

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Table 5.7

The slew rate of the I/O PAD of the new 2xVDD-tolerant I/O buffer with PVT compensation using 4-bits control signals.

Comparing with the PVT compensation using 3-bits control signals, the performance of the new 2xVDD-tolerant I/O buffer with PVT compensation using 4-bits control signals has not improved clearly. The reason is that when the control signal bits number increase, each segmented output driver will become smaller. In such high operating frequency, the compensation of the small size segmented output driver is insignificance, especially for the smallest one. Moreover, the size change of the output driver does not match the PVT variation. Therefore, too much bits of control signal won’t make the performance better.

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Chapter 6

Conclusions and Future Works

6.1Conclusions

A new 2xVDD-tolerant I/O buffer against gate-oxide overstress has been successfully designed and fabricated in a 0.18-mm 1.8-V CMOS process with only thin-oxide 1.8-V devices. Moreover, the gate-to-source, gate-to-drain, and drain-to-source voltages of all transistors in the new proposed 2xVDD-tolerant I/O buffer can be kept within the normal operating voltage range (VDD). This new 2xVDD-tolerant I/O buffer can receive 3.3-V input signals or transmit the 3.3-V output signals up to 133 MHz, which is compatible to the I/O specifications of PCI-X in the mixed-voltage I/O interfaces.

Because the advantage of the structure, the new 2xVDD-tolerant I/O buffer can combine with the slew-rate control circuit easily to reduce the ground bounce effect without suffering gate-oxide overstress issue.

In chapter 5, the new 2xVDD-tolerant logic gates which can deal with the 2xVDD signals without gate-oxide overstress have been proposed and can be used in the PVT variation compensation circuit to detect the PVT variation in an I/O buffer. Finally, in order to satisfy recent timing specification, the new 2xVDD-tolerant I/O buffer can combine with the PVT variation compensation circuit successfully to keep the output slew rate as constant as possible.

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6.2Future Works

The new 2xVDD-tolerant I/O buffer with slew-rate control and the new 2xVDD-tolerant I/O buffer with PVT compensation have to be fabricated for verification.

The method for PVT compensation which is mentioned in this thesis compensates only the Fast-Fast, Typical-Typical, and Slow-Slow corner. The compensation for the Slow-Fast and Fast-Slow corner will be uncorrected because the process of PMOS and NMOS cannot be compensated individually. In order to match all the corners, it needs another method that can compensate the process of PMOS and NMOS individually.

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62

VITA

姓 名：林彥良 學 歷：

高雄市立高雄高級中學 (89 年 9 月~92 年 6 月) 國立交通大學電機與控制工程學系 (92 年 9 月~96 年 6 月) 國立交通大學電子研究所碩士班 (96 年 9 月~98 年 8 月)

研究所修習課程：

類比積體電路 吳介琮教授

數位積體電路 周世傑教授

積體電路之靜電放電防護設計特論 柯明道教授

計算機結構 劉志尉教授

功率積體電路設計 陳科宏教授

前瞻類比積體電路 洪浩喬教授

超大型積體電路系統設計 闕河鳴教授

鎖相迴路設計與應用 陳巍仁教授

永久地址：高雄市三民區澄和路146 號

Email：cyco.ee96g@nctu.edu.tw

m9611617@alab.ee.nctu.edu.tw