Prior Design II: The Mixed-Voltage I/O Buffer with Blocking NMOS

Chapter 2 Prior Design

2.2 Prior Design II: The Mixed-Voltage I/O Buffer with Blocking NMOS

The Mixed-Voltage I/O Buffer with Blocking NMOS Technique

Fig 2.2 shows the mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-bias circuit proposed in [7]. The VDDH shown in Fig. 2.2 is a voltage level of 2xVDD which can be generated by a charge pump circuit [8]. Transistor MN1 is the blocking NMOS that can protect the conventional I/O buffer from the high-voltage overstress. The operations of the I/O buffer with blocking NMOS are listed in Table 2.1. When the I/O buffer is operated in the receive mode, the gate terminal of MN1 (node 2) is biased at VDD by the dynamic gate-bias circuit. At the same time, the pull-high PMOS MP0 and the pull-down NMOS MN0 are both turned off by the pre-driver circuit. And then if an input signal of logic low (0V) is received from the I/O PAD, node 1 is discharged to 0V through the transistor MN1, and this input signal can be successfully transferred to the node Din. When a signal of logic high (VDDH) is received at the I/O PAD, the gate terminal of MN1 is still biased at VDD, so the voltage on node 1 will be VDD-Vt. Then, MP1 is used to restore the voltage on node 1 to VDD. With such design, MN1, MP1 and INV can convert the VDDH input signal to VDD signal successfully.

Table 2.1

The operations of the mixed-voltage I/O buffer with blocking NMOS.

In transmit mode, when the I/O buffer transmits the output signal of logic high (VDD), the gate terminal of MN1 (node 2) is biased at VDDH by the dynamic gate-bias circuit, so the VDD signal can be transferred to the I/O PAD successfully.

When the I/O buffer is operated in the transmit mode and transmits the output signal of logic low (0V), the gate terminal of MN1 (node 2) is biased at VDD by the dynamic gate-bias circuit to avoid the MN1 suffering gate-oxide overstress issue.

Fig. 2.2 The mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-bias circuit.

Fig. 2.3 depicts the dynamic gate-bias circuit of the I/O buffer shown in Fig. 2.2.

When the voltage on node 5 is lower than VDD-Vt, MP3 will be turned on to bias node 6 at VDDH. Then, MN2 is turned on to keep the node 5 at VDD. Capacitors C1 and C2 are used to couple the signals from node 3 and 4 to node 5 and 6, respectively.

Since the voltage levels on the top plate and bottom plate of capacitors C1 and C2 are either VDD and 0V or 2xVDD and VDD, the voltage across these capacitors are always VDD. With these capacitors, when node 3 converts the voltage level from

VDD to 0V, the voltage level on node 5 is pulled down to VDD and then the voltage on node 6 is pulled high to 2xVDD by transistor MP3. On the contrary, when node 4 converts the voltage level from VDD to 0V, the voltage level on node 6 is pulled down to VDD and then the voltage on node 5 is pulled high to 2xVDD by transistor MP2. The diode strings DS1 and DS2 are designed to a little higher than VDD by using multiple diodes in stacked configuration, so the voltage across C1 and C2 can be maintained at VDD closely. For example, if node 3 is at 0V and node 4 is VDD initially, the voltage on node 5 is clamped at the turn-on voltage (~VDD) of DS1.

Therefore, MP3 is turned on to pull up the voltage on node 6 to 2xVDD. Thus, the voltage across C1 and C2 are both VDD.

Fig. 2.3 Circuit implementation of the dynamic gate-bias circuit in Fig. 2.2.

The prior designs of the mixed-voltage I/O buffer can receive 2xVDD input signals but only transmit VDD output signals. Therefore, a new 2xVDD-tolerant I/O buffer which can both transmit and receive 2xVDD signals is proposed and illustrated in the next chapter.

Chapter 3 New 2xVDD-Tolerant I/O Buffer

3.1Introduction

With the rapid development of CMOS techniques, the power supply voltage (VDD) is reduced for low-power applications and the thickness of gate oxide has been scaled down to increase circuit operating speed. In the meanwhile, the maximum tolerable voltage across the transistor terminals should be decreased to ensure lifetime.

However, the chips may receive the I/O signals with voltage levels higher than their normal supply voltage (VDD) from the old interface protocols of other CMOS ICs in a microelectronic system with multiple/different power supply voltages. Thus, it becomes more important to prevent the thin gate oxide of the I/O circuits in IC from voltage overstress in such mixed-voltage microelectronic systems. Recently, several mixed-voltage I/O buffers realized with thin oxide devices to receive input signals of higher voltage but only to transmit 1xVDD output signals were reported in [4], [9]-[13]. In this thesis, a 2xVDD-tolerant I/O buffer which can transmit and receive 2xVDD I/O signals without suffering gate-oxide reliability problem is proposed.

3.2 Implementation of Proposed 2xVDD-Tolerant I/O Buffer

3.2.1 Design Concept

Fig. 3.1 and Fig. 3.2 show the design concept of the dynamic source output technique. MP and MN are the transistors of the output stage in an I/O circuit. As shown in Fig. 3.1 (a), when transmitting the signal high (2xVDD), the 2xVDD voltage at I/O PAD must come from the source of transistor MP. The gate voltage of

MP should keep MP on and keep the voltage across gate to source and gate to drain within the normal power supply voltage (VDD), so the gate voltage of MP must be VDD. At the same time, the gate voltage of MN must be also VDD to keep the voltage across gate to drain within VDD, and the source voltage of MN should be VDD to turn MN off. By the similar analysis, when transmitting the signal low (0V), the voltages at each terminal can be derived as shown in Fig. 3.1 (b). Comparing Fig.

3.1 (a) and Fig. 3.1 (b), it can be discovered that no matter transmitting high or low, the gate voltages of transistors MP and MN won’t change but their source voltages would change. Therefore, it provides us an idea to control the transistors MP and MN on or off by changing their source voltage in the transmit mode.

(a) (b)

Fig. 3.1 The operations of the output stage in a 2xVDD-tolerant I/O buffer in transmit mode with (a) transmitting high and (b) transmitting low.

(a) (b)

Fig. 3.2 The operations of the output stage in a 2xVDD-tolerant I/O buffer in receive mode with (a) receiving high and (b) receiving low.

Fig. 3.2 shows the operations of the output stage in the 2xVDD-tolerant I/O buffer during receive mode. In receive mode, the devices of output stage should be kept completely off to avoid any unnecessary circuit leakage path. According to the operations in receive mode, the control signals from pre-driver will make the source voltages of MP and MN at VDD. As shown in Fig. 3.2 (a), when I/O PAD receiving 2xVDD input signal, the gate voltage of transistor MP should be biased at 2xVDD, and the gate of MN should be kept at VDD, to fully turn them off without suffering gate oxide reliability problem. With the same design consideration, the gate voltages of MP and MN can be arranged as that shown in Fig. 3.2 (b) when I/O PAD receiving signal low (0V). Observing the above analysis, it can be discovered that there needs a gate-controlled circuit whose outputs depend on the signals of OE and I/O PAD, where OE is the control signal that decides the I/O circuit operates in transmit mode or receive mode. The implementations of the dynamic source output technique and the gate-controlled circuit are shown in Fig. 3.3 and Fig. 3.4 respectively.

3.2.2 Circuit Scheme and Operation Modes

Fig. 3.3 shows the whole circuit scheme of the proposed 2xVDD-tolerant I/O buffer with the dynamic source output technique and the new gate-controlled circuit to protect the I/O buffer realized with 1xVDD devices against gate oxide reliability during transmitting and receiving 2xVDD signals. In transmit mode, according to the above analysis, the gate-controlled circuit biases the gate voltages TP and TN of transistors MP and MN at VDD, and then the dynamic source output stage controls the transistors MP and MN to be on or off by changing their source voltages. When the I/O buffer transmits 2xVDD output signal, PUH is pulled down to VDD by the level converter which is implemented with all 1xVDD devices. Then, the voltage at node A is 2xVDD due to the conduction of transistor MPP while MPN is off. At the

same time, PD is pulled down to 0V, and the voltage at node B is VDD since transistor MNP is on while MNN is off. Consequently, the I/O PAD is pulled high to 2xVDD. The similar operation for the I/O buffer to transmit 0-V output signal can be derived. In receive mode, the signals from PU and PD will control the voltages at node A and node B to VDD, and then the gate-controlled circuit provides appropriate voltages to TP and TN to completely turn MP and MN off. When the I/O buffer receives 2xVDD input signal, TP is biased at 2xVDD and TN is biased at VDD. When the I/O buffer receives 0-V input signal, TP is biased at VDD and TN is biased at 0V.

Accordingly, MP and MN can be completely turned off. The corresponding circuit operating voltages of the proposed 2xVDD-tolerant I/O buffer in two operating modes are summarized in Table 3.1.

To avoid leakage current of the parasitic pn-junction diode in p-channel transistors, the bulks of transistors MP and MPP which are related to 2xVDD signals are connected to 2xVDD, and the bulks of transistors MNP and MI2 which are only related to VDD signals are connected to VDD for the concern of driving capacity.

Fig. 3.3 The new proposed 2xVDD-tolerant I/O buffer.

Table 3.1

Operation Modes of the new proposed 2xVDD-tolerant I/O buffer.

3.2.3 Gate-Controlled Circuit

Fig. 3.4 shows the implementation of the gate-controlled circuit with 1xVDD devices which can provide appropriate voltages to the gates of MP and MN. The gate-controlled circuit can be divided into an upper part and an under part, which are with the complementary structures. All the voltage swing in the upper part are VDD-to-2xVDD, and all the voltage swing in the under part are 0V-to-VDD, so it can be guaranteed that there are no gate-oxide reliability problems in this gate-controlled circuit. To avoid the leakage current, the bulks of p-channel transistors in the upper part are all connected to 2xVDD, and the bulks of p-channel transistors in the under part are all connected to VDD.

Fig. 3.4 The gate-controlled circuit for the new proposed 2xVDD-tolerant I/O buffer.

In transmit mode, the control signal OE is VDD, so the transistors (MG1 and MG4) are turned on and the switches (SW1 and SW2) are turned off. Therefore, the voltages of TP and TN are VDD. In receive mode, the control signal OE is 0V, so the transistors (MG1 and MG4) are turned off and the switches (SW1 and SW2) are turned on. When the I/O buffer receives 2xVDD at the I/O PAD, MG2 is turned off and MG3 is turned on in the upper part, so TP is 2xVDD. In the under part, the MG5 is turned on to provide VDD to node D, so MG6 is turned off and the voltage of TN will be VDD. As the I/O buffer receives 0-V input signal, the operation concept is similar to that receiving a 2xVDD input signal.

3.2.4 Level Converter

The level converter used in Fig. 3.3 and Fig. 3.4 are the same architecture, which can convert the voltage swing 0V-to-VDD to VDD-to-2xVDD [14]. As shown in Fig.

3.5, the level converter has been modified in this work with increasing the devices, N2A and N2B. Because when the devices, P2A and P2B, are turned off, the node 1

and node 2 are floating at this moment if there are no N2A and N2B in this structure.

This is what we do not want to see in an integrated circuit. The increased n-channel transistors, N2A and N2B, can provide certain voltages (VDD) to node 1 and node 2 when the P2A and P2B are off. Therefore, the increased devices, N2A and N2B can guarantee the transistors related to node 1 and node 2 in a safe state. In Fig. 3.5, the bulks of the p-channel transistors which are related to the 2xVDD signals are connected to 2xVDD to avoid the leakage current producing by the conduction of the parasitic drain-to-well pn-junction diode. The voltage swing of input signals IN is from 0V to VDD. When signal IN is VDD, node 4 is pulled down to 0V, and transistor P5A is turned on. After transistor P5A is turned on, node 3 will be pulled down to VDD, and then P4B and P2B are turned on. Consequently, node OUT and node 5 are 2xVDD. At the same time, node 1 is pulled down to VDD because P2A is off and N2A is on, and then, transistor P1A is turned off.

Since the structure of the level converter is symmetrical, when signal IN is 0V, node 6 will be pulled high to VDD, and the operation is similar to the above. Finally, node OUT will be VDD and node 3 will be 2xVDD.

Fig. 3.5 The modified level converter which represents the level converter shown in Fig. 3.3 and Fig. 3.4.

3.2.5 Discussions

In some condition, the drain-to-bulk voltages of transistors MP, MN, and MPN are 2xVDD, but in general, the drain-to-bulk breakdown voltage is at least twice of the normal operating voltage in the standard CMOS process [15], [16]. Hence, the drain-to-bulk breakdown issue would be ignored in the proposed 2xVDD-tolerant I/O buffer. However, the reverse voltage of 2xVDD across the p-n junction results in larger leakage current in the substrate, it increases the power consumption and the potential that the circuit goes into latch-up. The designer should check the process parameters to make sure that the resulted leakage in the corresponding process is in an acceptable value. To decrease the leakage current, in the circuit’s layout, the distance between PMOS and NMOS should be kept longer to increase the equivalent resistance between the p-n junction of the bulks. Moreover, the transistors can be surrounded the guard ring to absorb the leakage currents.

In this new 2xVDD-tolerant I/O buffer, the bulk of MPN can be set at 0V without gate-oxide reliability problem, even if the gate voltage of MPN may be as high as 2xVDD. The reason is that this NMOS MPN is turned on if its gate voltage is 2xVDD, so the voltage across the gate oxide of MPN is from the gate to conducting channel but not from the gate to its bulk. The gate oxides of all NMOS devices in the new 2xVDD-tolerant I/O buffer are also safe because they are turned on when their gate terminals are pulled to 2xVDD.

3.3 Simulation Results

3.3.1 Function of Proposed 2xVDD-Tolerant I/O Buffer

It has been verified by simulation in a 0.18-µm CMOS process that the maximum voltage across any two terminals (gate, drain, and source) of each transistor in the proposed 2xVDD-tolerant output buffer is kept within VDD. The simulated

waveforms of the proposed I/O buffer to transmit or to receive 133-MHz 2xVDD signals with 10-pF loading and VDD of 1.5V are shown in Fig. 3.6.

As shown in Fig. 3.6 (a), when the I/O buffer is operating in the transmit mode, the nodes TP and TN are 1.5V. If it transmits 3.3-V signals, node A will be 3.3V and node B will be 1.5V. If it transmits 0-V signals, node A will be 1.5V and node B will be 0V. On the other hand, as shown in Fig. 3.6 (b), when the I/O buffer is operating in the receive mode, the nodes A and B are 1.5V. If it receives 3.3-V signals, node TP will be 3.3V and node TN will be 1.5V. If it receives 0-V signals, node TP will be 1.5V and node TN will be 0V.The simulated results are all consistent to this design expectation. The voltage across any two terminals of each transistor in the output stage would not exceed VDD.

(a)

(b)

Fig. 3.6 Simulated waveforms of the proposed 2xVDD-tolerant I/O buffer with 133-MHz signals in (a) transmit mode, and (b) receive mode.

The simulated power consumption is 24.3 mW in transmit mode to drive the 10-pF output loading at the frequency of 133 MHz. And the power consuming on the output loading dominates the total power consumption.

3.3.2 Slew Rate Effects of Input Signal in Receive Mode

The relation between the slew rate of the input signal and the leakage current of MP and MN in receive mode are shown in Fig.3.7. The input rise time/fall time is 0.2-ns in Fig. 3.7 (a) and 1-ns in Fig. 3.7 (b). The peak leakage currents of MP and MN in Fig. 3.7 (a) are larger than Fig. 3.7 (b). And the power consumption is 141 μW in Fig. 3.7 (a) and 113 μW in Fig. 3.7 (b). So, if the slew rate of the input signal is smaller, the leakage currents of MP and MN will be less.

(a)

(b)

Fig. 3.7 The simulation results of the current waveforms for MP and MN in the receive mode with the (a) 0.2-ns input rise time/fall time and (b) 1-ns input rise time/fall time.

The relationship between the slew rate of the input signal and the peak values of the gate-to-source and gate-to-drain voltage waveforms for MN and MP in receive mode are shown in Fig. 3.8. In the transient state, the gate-to-drain voltage would exceed 1.8V slightly for a short period of time. Comparing Fig. 3.8 (a) and Fig. 3.8 (b), it can be discovered that the peak values of the gate-to-drain voltage with 0.2-ns input rise time/fall time is larger than with the 1-ns input rise time/fall time. So, if the slew rate of the input signal is smaller, the performance of reliability will be better.

Besides, the gate-to-source voltages in Fig. 3.8 (a) and Fig. 3.8 (b) are all still kept in 1.8V, so there is no reliability issue upon the gate-to-source voltages of MP and MN in receive mode.

(a)

(b)

Fig. 3.8 The simulation results of the gate-to-source and gate-to-drain voltage waveforms for MP and MN in the receive mode with (a) 0.2-ns input rise time/fall time and (b) 1-ns input rise time/fall time.

3.3.3 Discussion of Propagation Delay with Gate-Controlled Circuit

TABLE 3.2 discusses the leakage currents of MP and MN due to the propagation delays from I/O PAD to TP and from I/O PAD to TN. The propagation delays from I/O PAD to TP and from I/O PAD to TN dominate the turned-on time of MP and MN in the transient. Increasing the driving capability of MG3 and MG6 could make the MP and MN to be turned off more quickly. From TABLE 3.2, it can be discovered that power consumption is less than the original after increasing the size of MG3 and MG6.

Table 3.2

The relation between the propagation delay and the power consumption.

3.4 Experimental Results

3.4.1 Measurement Settings

The layout and die photo of the proposed 2xVDD-tolerant I/O buffer fabricated in a 0.18-μm 1.8-V CMOS process is shown in Fig. 3.9. The active area of the proposed I/O buffer is around 127μm x 785μm. The output stage dominates the major area of this I/O buffer. The area occupied by the control circuitry is about 15% of the I/O cell area. The printed circuit board (PCB) of tested 2xVDD-tolerant I/O buffer is shown in

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