New 2xVDD-Tolerant I/O Buffer with PVT Compensation

Fig. 5.1 shows the design concept of the PVT compensation technique to keep the output slew rate of an I/O buffer within in a certain range [20]. As shown in Fig. 5.1, the PVT variation detector detects process, voltage, and temperature variations by sensing the reference clock in different conditions. Then the PVT variation detector will generate the corresponding pre-control signals to the encoder. The encoder using these pre-control signals to generate applicable control signals to the output stage of an I/O buffer. The drive strength of the output driver can be adjusted with these control signals to match the PVT variation. The detail implementation will be illustrated as following.

Fig 5.1 Block diagram of solution for PVT compensation.

5.2.1 PVT Variation Detector

The schematic of the PVT variation detector is shown in Fig. 5.2. First, the reference clock delivers the logic high into the delay chain. Then once the reference clock turns to logic low, the outputs of each delay cells will be load into the register.

Because the propagation delay of a delay cell depends on the process, voltage and temperature, the propagation delay determines how many the signals of logic high

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will be load into the register. For example, in the fast condition, the signal of logic high can pass through many delay cells in a reference clock cycle. On the contrast, in the slow condition, most of the delay cells’ outputs will be logic low since the signal logic high has not been delivered to them when the reference clock turns to logic low.

As shown in Fig. 5.3, the register in Fig. 5.2 is implemented with the pulse triggered D flip-flop. Thus, the register loads data in the moment that the reference clock turns to logic low. Next the outputs of this register will be converted to the pre-control signals by several logic gates for convenient application in the output stage. For the new 2xVDD-tolerant I/O buffer with PVT compensation, the 2xVDD power supply variation should be sensed in the PVT variation detector. Therefore, the logic gates should be implemented with the 2xVDD-tolerant logic gates which will be illustrated in section 5.3.

Fig 5.2 The PVT variation detector.

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Fig 5.3 The pulse triggered D flip-flop using as the register in the PVT variation detector.

5.2.2 Encoder

In order to control the segmented output driver which will be illustrated in next section conveniently, the pre-control signals from the PVT variation detector have to be encoded appropriately. Table 5.1 shows the truth table of encoder in the PVT compensation circuit. The D0-D7 are the pre-control signals from the PVT variation detector. All the situations that D0-D7 could be are listed in the truth table. In the fastest condition, the signals of D0-D7 are “00000001”. On the contrast, the signals of D0-D7 are “10000000” in the slowest condition. The pre-signals D0-D7 are encoded to the binary codes S0-S2. If signals of S0-S2 are logic high, it means that the corresponding segmented output driver is turned on. The implementation of this 8-to-3 encoder is shown in Fig. 5.4. Since the circuit is implemented with the 2xVDD-tolerant logic gates whose voltage swing is from 0V to 2xVDD, the outputs S0-S2 should be converted to S0H-S2H and S0L-S2L by the level converter for being used correctly in the output stage. The voltage swing of S0H-S2H is from VDD to 2xVDD and voltage swing of S0L-S2L is from 0V to VDD. As shown in Fig. 5.4, the level converter converts 0V-to-2xVDD signals to VDD-to-2xVDD and 0V-to-VDD signals. The detail implementation of this level converter will be illustrated in section 5.3.

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Table 5.1

Truth table of Encoder in the PVT compensation circuit.

Fig 5.4 The circuit schematic of encoder.

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5.2.3 Output Stage with Control Signals

The schematic of new 2xVDD-tolerant I/O buffer with PVT compensation is shown in Fig. 5.5. S0H-S2H and S0L-S2L are the PVT variation related signals which are generated from the PVT variation detector and the encoder. With the OR gates and AND gates shown in Fig. 5.5, the S0H-S2H and S0L-S2L can be used to determined the segmented output drivers to be turn on or turn off. Because the voltage swing of S0H-S2H is from VDD to 2xVDD, the voltage swing of OR gates is from VDD to 2xVDD. Similarly, because the voltage swing of S0L-S2L is from 0V to VDD, the voltage swing of AND gates is from 0V to VDD. Since S0H-S2H and S0L-S2L are binary codes and their weighting are S2H > S1H > S0H and S2L > S1L > S0L, the size weightings of these segmented output drivers are MPP2 > MPP1 > MPP0 and MNN2

> MNN1 > MNN0. The output transistors MPP and MNN are the basic output driver, so when the binary codes are “000” which happens in the slowest condition, only MPP and MNN will be used. Therefore, the size of MPP and MNN can be determined to match the driving capacity of typical condition in slowest condition. Next, the size of MPP1 and MNN1 can be determined to match the driving capacity of typical condition in the condition whose corresponding codes are “001”, because only MPP, MNN, MPP1 and MNN1 are used in this condition. Following such design strategy, the sizes of all the output drivers can be roughly determined. Note that the driving capacity is precise in the design point like “000” and “001” with such design strategy, but it will be a little oversized or undersized in other conditions like “011” or “101”.

However, the design strategy provides a way to grasp approximate trend of the size change of the output driver. The corresponding size ratios of the output drivers are shown in Table 5.2. Furthermore, the bits of the control signals can be extended to 4 bits or more. The 4-bit control signals example of the 2xVDD-tolerant I/O buffer with PVT compensation is shown in Fig. 5.6.

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Fig 5.5 The schematic of new 2xVDD-tolerant I/O buffer with PVT compensation.

Table 5.2

The size ratios of the output driver.

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Fig 5.6 The schematic of new 2xVDD-tolerant I/O buffer with PVT compensation of 4-bit control signals.