Chapter 3 New 2xVDD-Tolerant I/O Buffer
3.4 Experimental Results
3.4.2 Measurement Results
The measured waveforms of the proposed I/O buffer to transmit and receive 3.3-V signals are shown in Fig. 3.12 and Fig. 3.13 with VDD of 1.5V. Fig. 3.12 (a) and Fig.
3.12 (b) show the measured waveforms in transmit mode with respect to 1-MHz and 133-MHz I/O signals. It is noticed that the input Dout is 1.5V and the output voltage at the I/O PAD is 3.3V. Fig. 13 (a) and Fig. 13 (b) show the measured waveforms in receive mode with respect to 1-MHz and 133-MHz I/O signals, where the input voltage at the I/O PAD is 3.3V and the output Din is 1.5V. Due to the limitation of our pulse generator (HP 81110A), the output signal of this instrument operating in 133MHz is not a perfect pulse but a sinusoidal function with 3.3-V amplitude.
Moreover, the threshold voltage of MI1 shown in Fig. 3.3 is about 0.5 V, so the input signal which is larger than 0.5 V will be considered as high signal. This results in the duty cycle being larger than 50%. The duty cycle can be well adjusted by additional duty-cycle adjustment circuit. The experimental results have confirmed that the proposed 2xVDD-tolerant I/O buffer can successfully transmit and receive 2xVDD signals up to 133MHz. The major speed limitation of this buffer is the driving capability of the output stage. It can be operated at a higher frequency if the transistor size of the output stage is increased.
The 2xVDD-tolerant I/O buffer has been successfully designed with dynamic source output technique and realized with 1xVDD CMOS devices in this thesis, which has been fabricated in a 0.18-μm 1.8-V CMOS process to transmit and receive 3.3-V signals without suffering gate-oxide reliability issue. The new proposed 2xVDD-tolerant I/O circuit solution can be implemented in different nanoscale CMOS processes to meet the mixed-voltage applications in microelectronic systems.
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(a)
(b)
Fig. 3.12 The measured waveforms of the proposed I/O buffer in transmit mode with respect to (a) 1-MHz and (b) 133-MHz I/O signals.
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(a)
(b)
Fig. 3.13 The measured waveforms of the proposed I/O buffer in receive mode with respect to (a) 1-MHz and (b) 133-MHz I/O signals.
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Chapter 4
New 2xVDD-Tolerant I/O Buffer with Slew-Rate Control
4.1Introduction
Signal and power integrity are crucial problems in VLSI systems. Modern trends in deep sub-micron circuit designs, such as high operating frequencies, short rise/fall times, and lower supply voltage, exacerbate this problem. The pads of an output buffer on the PCB typically connect to series parasitic inductances produced by the bonding wire. An inductive noise will be induced in this condition. Ground Bounce, also known as simultaneous switching noise (SSN) or delta-I noise, is a voltage glitch induced at power/ground (P/G) distribution connections due to switching currents passing through either wire inductance or package lead inductance associated with power or ground rails. When the current flows through the inductance L, the voltage drop can be expressed as
V L di
= dt
(4-1) The resulting noise voltage can potentially cause spurious transitions at the inputs of devices sharing the same power and ground rails. Therefore, controlling the output voltage variations is generally required to limit the crosstalk and reduce the inductive power supply noise to an acceptable value.In this chapter, the new 2xVDD-tolerant I/O buffer proposed in chapter 3 is redesigned with slew-rate control to decrease the ground bounce effects.
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4.2Traditional Output Buffer with Slew-Rate Control
To reduce the simultaneous switching noise, a simple approach is to slow down the turn-on time of the output switching transistor through an access resister which can be implemented by a transmission gate to the transistor gate. Furthermore, the output driver can be divided into several output drivers and be turned on gradually for ground bounce reduction and slew-rate control. An output buffer with a three-step slew-rate control circuit is shown in Fig. 4.1 [17]. The output transistors are divided into three parts with their corresponding gate-controlled signals generated by slew-rate control circuit. The transistors MNS4 and MPS4 in Fig. 4.2 are used to control CMOS output driver to turn it on. When the output buffer is operating in transmit mode (OE=VDD), the transmission gates S1-S4 are used as resistive elements to turn on each individual output transistor gradually. As the output buffer is operating in tri-state mode, the output transistors are quickly turned off by the transistors MPS1-MPS3 and MNS1-MNS3 since the gate-controlled signals won’t pass through the transmission gates. With such structure of slew-rate control, the short- circuit current can be reduced efficiently for low power design.
The number of parts of an output buffer with slew-rate control can be extended to 4 bits or more. If the output buffer is divided into more parts, the switching current of each part in the output buffer can be decreased, but the propagation delay will be increased and the cost of the circuit is also increased. The designer should adjust the size of transmission gates and the size of each output driver to match the design requirements of the timing and noise specifications.
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Fig 4.1 Conventional output buffer with slew-rate control.
4.3New 2xVDD-Tolerant I/O Buffer with Slew-Rate Control
4.3.1 Circuit Implementation
In section 3.2, a new 2xVDD-tolerant I/O buffer to transmit and receive 2xVDD signals has been proposed. To reduce the effect of ground bounce, the new 2xVDD-tolerant I/O buffer is combined with a three-step slew-rate control circuit as shown in Fig. 4.2. Note that the total sizes of the output transistors in Fig. 4.2 are kept the same with output transistors in Fig. 3.3 for equal driving capacity. The voltage swing of MNS4, S1-S2 and MPS1-MPS3 are from VDD to 2xVDD for correct operating without gate-oxide overstress issue. The sizes of transmission gates affect the timing performance of the buffer. The small size can prolong the turn-on time of
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the output switching transistor to minimize the ground bounce effect, but it also increases the delay time of circuit. The user can optimize the sizes of these transmission gates to match the specification. Because the switching current of the output transistors will result in the ground bounce, a major consideration is to reduce the peak switching current efficiently. A direct method is to let the size of output transistor which is turned on earlier be the smaller one. Because the drain-to-source voltage of the output transistor which is turned on later will be smaller than the earlier one, the equal size will make them have different driving capacity. So in Fig. 4.2, the size arrangements of these output transistors are MPP1 < MPP2 < MPP3 and MNN1
< MNN2 < MNN3. The corresponding size ratios are shown in Table 4.1.
Fig 4.2 New 2xVDD-tolerant I/O buffer with slew-rate control.
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Table 4.1
The size ratio of the output transistors
4.3.2 Simulation Results
The new 2xVDD-tolerant I/O buffer with slew-rate control has been verified in a 0.18-μm CMOS process by SPICE simulation with VDD of 1.5V and VDDH of 3.3V.
The simulation waveforms with an operating speed of 133 MHz in transmit mode are shown in Fig 4.3. The gate-controlled signals MPP1-MPP3, VP1, VP2 and VP3, are pulled to 1.5V one by one as the 2xVDD-tolerant I/O buffer transmits 3.3-V output signal to I/O PAD. On the contrary, when 0-V output signal is transmitted to I/O PAD, the VP1, VP2 and VP3 are quickly pulled up to 3.3V to turn off transistors MPP1-MPP3. Similarly, the gate-controlled signals MNN1-MNN3, VN1, VN2 and VN3, are progressively pulled up to 1.5V in transmitting 0-V output signal and quickly pulled down to 0V to turn off transistors MNN1-MNN3 in transmitting 3.3-V output signal.
Table 4.2 summarizes the simulation results of the new 2xVDD-tolerant I/O buffer with or without slew-rate control. As a result, the switching currents of 2xVDD-tolerant I/O buffer with slew-rate control are smaller than those without slew-rate control. The timing specifications of 2xVDD-tolerant I/O buffer with slew-rate control are larger than those without slew-rate control. As shown in Table 4.2, the power consumption of new 2xVDD-tolerant I/O buffer with slew-rate control is a little less than those without slew-rate control due to the peak switching current reduction.
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Fig 4.3 Simulation waveforms of the new 2xVDD-tolerant I/O buffer with slew-rate control operating at 133 MHz when transmitting 0V-to-1.5V output signals to I/O PAD.
Table 4.2
The simulation results of new 2xVDD-tolerant I/O buffer with or without slew-rate control.
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4.3.3 Ground Bounce
In order to verify the reduction of ground bounce by slew-rate control, a model for ground bounce effects is shown in Fig. 4.4. The inductance of wire bonds vary from 7nH to 15nH in the simulation for typical cases. Since the switching currents of 2xVDD-tolerant I/O buffer in transmit mode are much larger than that in receive mode, the ground bounce effects are simulated in transmit mode for clear illustration.
The simulation waveforms of ground bounce effects on power lines are shown in Fig.
4.5 and several parameters are defined as follows:
VDDH_ext / VDD_ext / VSS_ext : external power supply;
VDDH_max : maximum value of VDDH power line;
VSS_max : maximum value of VSS power line;
VDDH_min : minimum value of VDDH power line;
VSS_max : minimum value of VSS power line;
VDDH_over : overshot on VDDH power line (VDDH_max- VDDH_ext)
VDDH_under : undershot on VDDH power line (VDDH_ext- VDDH_min)
VSS_over : overshot on VSS power line (VSS_max- VSS_ext)
VSS_under : undershot on VSS power line (VSS_ext- VSS_min)
The VDDH_under and VSS_over among these parameters are the major concerns since these two terms may result in increasing timing delay and even logic errors on transmitted signals.
The simulation waveforms of the new 2xVDD-tolerant I/O buffer with slew-rate control which is operated in transmit mode with an operating speed of 133MHz are shown in Fig 4.6. The signals on I/O PAD are like sine wave with distortion due to the ground bounce effect. The simulation results with variation wire bond inductance on VDDH power line and VSS power line are shown in Fig. 4.7 and Fig. 4.8, respectively. Since the current supplied from VDD is much smaller than that from
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VDDH, only ground bounce effect in VDDH is shown. As shown in Fig. 4.7 and Fig.
4.8, the slew-rate control circuit improves the ground bounce effects greatly.
I/O Circuit
LVDDH
LVDD
LVSS VSS
VDD VDDH
VDDH_ext VDD_ext
Input Output
VSS_ext
Fig 4.4 Simulated model of ground bounce.
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(a)
(b)
Fig 4.5 Simulation waveforms of ground bounce effects on (a) VDDH power line and (b) VSS power line.
Fig 4.6 Simulation waveforms of the 2xVDD-tolerant I/O buffer with slew-rate control for ground bounce effect in transmit mode.
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Fig 4.7 The relation between ground bounce on VDDH power line and wire bond inductance on the new 2xVDD-tolerant I/O buffer with or without slew-rate control.
(a) The overshoot and (b) the undershoot on VDDH power line.
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Fig 4.8 The relation between ground bounce on VSS power line and wire bond inductance on the new 2xVDD-tolerant I/O buffer with or without slew-rate control.
(a) The overshoot and (b) the undershoot on VSS power line.
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Chapter 5
New 2xVDD-Tolerant I/O Buffer with PVT Compensation
5.1Introduction
In chapter 4, the new 2xVDD-tolerant I/O buffer with slew-rate control for ground bounce reduction has been discussed. Furthermore, to resist the slew-rate variation, the new 2xVDD-tolerant I/O buffer with PVT compensation will be illustrated in this chapter.
With the recent trend for high-speed interface, the sensitivity of circuits towards process, voltage and temperature (PVT) variation is hampering circuit performance and yield. For example, in the case of I/O pads it is difficult to meet the rise and fall times, current, power and ground bounce specifications across all PVT corners. Driver circuits are oversized to meet timing at slow corners. This causes high current and Simultaneous Switching Noise (SSN) at fast corners. Such effects degrade the reliability of the circuit and require considerable amount of design resources and time to meet circuit performance across PVT variation [18]. Therefore, recent interface specifications like UDMA 100 [19] are not only to limit the minimum or maximum value the timing specification but also require the slew rate keeping in a certain range.
In next section, a method of PVT compensation to make the output slew rate be kept as constant as possible will be illustrated.
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5.2New 2xVDD-Tolerant I/O Buffer with PVT Compensation
Fig. 5.1 shows the design concept of the PVT compensation technique to keep the output slew rate of an I/O buffer within in a certain range [20]. As shown in Fig. 5.1, the PVT variation detector detects process, voltage, and temperature variations by sensing the reference clock in different conditions. Then the PVT variation detector will generate the corresponding pre-control signals to the encoder. The encoder using these pre-control signals to generate applicable control signals to the output stage of an I/O buffer. The drive strength of the output driver can be adjusted with these control signals to match the PVT variation. The detail implementation will be illustrated as following.
Fig 5.1 Block diagram of solution for PVT compensation.
5.2.1 PVT Variation Detector
The schematic of the PVT variation detector is shown in Fig. 5.2. First, the reference clock delivers the logic high into the delay chain. Then once the reference clock turns to logic low, the outputs of each delay cells will be load into the register.
Because the propagation delay of a delay cell depends on the process, voltage and temperature, the propagation delay determines how many the signals of logic high
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will be load into the register. For example, in the fast condition, the signal of logic high can pass through many delay cells in a reference clock cycle. On the contrast, in the slow condition, most of the delay cells’ outputs will be logic low since the signal logic high has not been delivered to them when the reference clock turns to logic low.
As shown in Fig. 5.3, the register in Fig. 5.2 is implemented with the pulse triggered D flip-flop. Thus, the register loads data in the moment that the reference clock turns to logic low. Next the outputs of this register will be converted to the pre-control signals by several logic gates for convenient application in the output stage. For the new 2xVDD-tolerant I/O buffer with PVT compensation, the 2xVDD power supply variation should be sensed in the PVT variation detector. Therefore, the logic gates should be implemented with the 2xVDD-tolerant logic gates which will be illustrated in section 5.3.
Fig 5.2 The PVT variation detector.
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Fig 5.3 The pulse triggered D flip-flop using as the register in the PVT variation detector.
5.2.2 Encoder
In order to control the segmented output driver which will be illustrated in next section conveniently, the pre-control signals from the PVT variation detector have to be encoded appropriately. Table 5.1 shows the truth table of encoder in the PVT compensation circuit. The D0-D7 are the pre-control signals from the PVT variation detector. All the situations that D0-D7 could be are listed in the truth table. In the fastest condition, the signals of D0-D7 are “00000001”. On the contrast, the signals of D0-D7 are “10000000” in the slowest condition. The pre-signals D0-D7 are encoded to the binary codes S0-S2. If signals of S0-S2 are logic high, it means that the corresponding segmented output driver is turned on. The implementation of this 8-to-3 encoder is shown in Fig. 5.4. Since the circuit is implemented with the 2xVDD-tolerant logic gates whose voltage swing is from 0V to 2xVDD, the outputs S0-S2 should be converted to S0H-S2H and S0L-S2L by the level converter for being used correctly in the output stage. The voltage swing of S0H-S2H is from VDD to 2xVDD and voltage swing of S0L-S2L is from 0V to VDD. As shown in Fig. 5.4, the level converter converts 0V-to-2xVDD signals to VDD-to-2xVDD and 0V-to-VDD signals. The detail implementation of this level converter will be illustrated in section 5.3.
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Table 5.1
Truth table of Encoder in the PVT compensation circuit.
Fig 5.4 The circuit schematic of encoder.
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5.2.3 Output Stage with Control Signals
The schematic of new 2xVDD-tolerant I/O buffer with PVT compensation is shown in Fig. 5.5. S0H-S2H and S0L-S2L are the PVT variation related signals which are generated from the PVT variation detector and the encoder. With the OR gates and AND gates shown in Fig. 5.5, the S0H-S2H and S0L-S2L can be used to determined the segmented output drivers to be turn on or turn off. Because the voltage swing of S0H-S2H is from VDD to 2xVDD, the voltage swing of OR gates is from VDD to 2xVDD. Similarly, because the voltage swing of S0L-S2L is from 0V to VDD, the voltage swing of AND gates is from 0V to VDD. Since S0H-S2H and S0L-S2L are binary codes and their weighting are S2H > S1H > S0H and S2L > S1L > S0L, the size weightings of these segmented output drivers are MPP2 > MPP1 > MPP0 and MNN2
> MNN1 > MNN0. The output transistors MPP and MNN are the basic output driver, so when the binary codes are “000” which happens in the slowest condition, only MPP and MNN will be used. Therefore, the size of MPP and MNN can be determined to match the driving capacity of typical condition in slowest condition. Next, the size of MPP1 and MNN1 can be determined to match the driving capacity of typical condition in the condition whose corresponding codes are “001”, because only MPP, MNN, MPP1 and MNN1 are used in this condition. Following such design strategy, the sizes of all the output drivers can be roughly determined. Note that the driving capacity is precise in the design point like “000” and “001” with such design strategy, but it will be a little oversized or undersized in other conditions like “011” or “101”.
However, the design strategy provides a way to grasp approximate trend of the size change of the output driver. The corresponding size ratios of the output drivers are shown in Table 5.2. Furthermore, the bits of the control signals can be extended to 4 bits or more. The 4-bit control signals example of the 2xVDD-tolerant I/O buffer with PVT compensation is shown in Fig. 5.6.
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Fig 5.5 The schematic of new 2xVDD-tolerant I/O buffer with PVT compensation.
Table 5.2
The size ratios of the output driver.
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Fig 5.6 The schematic of new 2xVDD-tolerant I/O buffer with PVT compensation of 4-bit control signals.
5.3Proposed 2xVDD-Tolerant Logic gate
In order to detect the 2xVDD power supply variation, the delay chain should be implemented with the 2xVDD-tolerant logic gates. For consistency, all the logic gates in the PVT variation detector are the structure of 2xVDD-tolerant logic gates. Of course, the voltage level of 2xVDD can be also shifted to VDD by a level converter and be dealt with normal logic gates. This paper just proposed a direct way by using the 2xVDD-tolerant logic gates to accomplish this work.
The voltage swing of inputs and outputs of the 2xVDD-tolerant logic gates are from 0V to 2xVDD. Fig. 5.7 shows the schematic of 2xVDD-tolerant inverter. As shown in Fig. 5.7, the signal IN whose voltage swing is from 0 to 2xVDD is
The voltage swing of inputs and outputs of the 2xVDD-tolerant logic gates are from 0V to 2xVDD. Fig. 5.7 shows the schematic of 2xVDD-tolerant inverter. As shown in Fig. 5.7, the signal IN whose voltage swing is from 0 to 2xVDD is