Inter-modulation

Equation (2.20) is plotted in Figure 2.5.

Figure 2.5 Frequency spectrum of input, output of the nonlinear system

2.1.6 Inter-Modulation

Inter-modulation arises when more than one tone is present at the input. Assume that

Chapter 2 Basic Concepts of LNA Design

two strong interferers occur at the input of the receiver, specified by s(t)= A1cosω1t+

A2cosω2t. The inter-modulation distortion can be expressed mathematically by applying s(t) to (2.17):

Using trigonometric manipulations, we can find expressions for the second and the third-order inter-modulation products as follows:

( ) ( )

The third-order inter-modulation products at 2ω²-ω1, 2ω¹-ω2 and a nonlinear system (ex: LNA, PA..), the output signal will be corrupted are illustrated in Figure.2.6.

Figure 2.6 Inter-modulation in a nonlinear system

The output spectrum in the frequency domain can be determined from (2.22) by evaluating its Fourier transform Y(ω). This is shown in Figure 2.9, where the following signals: ω0: desired signal, ω1, ω2: strong interferers, 2ω1, 2ω2: harmonics of the interferers, ω¹±ω2: second order inter-modulations products, 2ω^1,2±ω2,1: Third order inter-modulation products. It can be seen from Figure 2.7 that the inter-modulation

Chapter 2 Basic Concepts of LNA Design

Furthermore, ω1, ω2 are close to ω0 ; therefore, trying to filter them out requires a filter bandwidth that is very narrow and is impractical. Keeping down 2ω²-ω1 by keeping the nonlinearity small is the only solution.

Figure 2.7 The effect of the inter-modulation distortion in the frequency domain

2.1.7 Third Order Harmonics Intercept Point (IP3)

From (2.21), we note that as the input level A increase, the desired signal at the output is proportional to A (by the small signal gain α1). On the other hand, from (2.22) we can see that the third-order product increases in proportion to A³. This is plotted on a linear scale in Figure 2.8 (a). Figure 2.8 (a) is re-plotted on a logarithmic scale in Figure 2.8 (b), where power level is used instead of amplitude level. As shown in Figure 2.10 (b), the third-order intercept point IP3 is defined to be the intersection of the two lines.

From Figure 2.8 (b), we can see that the amplitude of the input interferer at the third-order intercept point, AIP3, is defined by the relation

(

1 3

)

^{3 3}3 For a 50Ω load, we define the input third-order intercept point (IIP3) as IIP3=

Chapter 2 Basic Concepts of LNA Design

A²IP3/50Ω.(IIP3 is hence interpreted as the power level of the input interferer for a 50Ω load at the third-order intercept point).

Figure 2.8 (a) The linear gain (α1A) and the nonlinear component (3α3A³ /4 ); (b) The input and output third order intercept point (IIP3, OIP3)

2.1.8 1-dB Gain Compression Point (P1dB)

When the input signal to an amplifier is large, the amplifier will be saturates, hence clipping the signal. When the strength of the input signal is further increased, the output signal is no longer amplified. At this point, the output is said to be compressed. From (2.17), we observe that in y(t) there are two terms with frequency ω0 due to the nonlinear behavior. Assume that the other terms in y(t) have frequency outside the band of interest and hence are removed by the BPFs. Thus, y(t) becomes

3 2

In the case where α3 is negative, the second term is decreasing the gain. As the input starts to increase, the impact of the second term becomes important in the sense that it

Chapter 2 Basic Concepts of LNA Design

signal when the linear voltage gain drops by 1dB. Form (2.25), we see that the 1-dB compression point can be expressed mathematically by

2

We can rewrite (2.26) in terms of decibels:

2

The ideal of the 1dB compression point is shown graphically in Figure 2.9. In

Figure 2.9 Illustration of the 1-dB compression point

Figure 2.10 illustrates that when input signal is -20dBm, gain is 10dB, and P1dB is 0dBm, the output signal will be -20dBm+10=-10dBm. Due to output signal < P1dB= 0dBm, so the output signal will not distortion. Oppositely, if input signal is -5dBm, the output signal will be -5dBm+10=+5dBm. But the output signal over the P1dB= 0dBm, so

Chapter 2 Basic Concepts of LNA Design

the output signal will distortion. In Figure 2.11 illustrates that P1dB large when input signal is -20dBm or -5dBm, the output signal will not distortion.

Figure 2.10 Illustration of the P1dB small

Figure 2.11 Illustration of the P1dB large

2.2 Conventional LNA input matching Architecture

Low noise amplifier is the first stage in the receiver front-end circuits and is used to

Chapter 2 Basic Concepts of LNA Design

amplify the received weak RF signal with the minimum noise figure. Between the wideband input matching and the noise figure of the UWB LNA should be carefully studied and decide. Impedance matching is very important in LNA designs. There are four basic 50Ohm input matching architectures that have been explored in the traditional transistor-amplifier shown in Figure 2.12. In this section, we will investigate a number of circuit architecture that can be used of the task and discussed.

Figure 2.12 Traditional transistor-amplifier of input matching

a. Resistive Termination architecture

Resistive termination architecture is the most straightforward approach to achieve the wideband 50Ohm matching at the input as shown in Figure 2.13. The 50Ohm resistor (R) is placed across the input terminal of the LNA and hence providing a wideband matching.

Figure 2.13 Resistive termination matching technique

The bandwidth of this matching technique is determined by the input capacitance of the transistor M1 and can be very high. However, the resistor R adds into circuit will

Chapter 2 Basic Concepts of LNA Design

good input matching, but leads to high thermal noise in circuit. If ignoring all the noises from the transistors, the lower bound of the noise factor is equal to 2. Hence, the resistor termination technique is not practical in most application.

b. Common Gate input architecture (1/gm termination)

The last input matching method is to use a common-gate architecture as shown in Figure 2.16. [3], [4], [12]. A common gate (or the 1/gm termination) architecture has the highest potential to achieve the wideband input matching, good linearity, and input-output isolation, but it leads to lower gain and higher noise figure than using the other mentioned techniques. Using the common gate architecture has the lower bound noise factor is F 1

γ

≈ +

α

≧2.2. (i.e Long channel F=2.2, Short channel F=4.7～6).

Figure 2.14 Common gate input matching technique

c. Shunt-Series resistor feedback architecture

The resistor feedback technique is used for getting a good input matching architecture as shown in Figure 2.15 [9], [14], [21], [22], [23], [25]. This technique unlike resistive termination case, it does not attenuate the signal by a noisy attenuator before reaching the gate of amplifying device and hence the noise figure is expected to be much higher. However, the feedback resistor (RF) continues to generate thermal noise if its own.

Chapter 2 Basic Concepts of LNA Design

Figure 2.15 Shunt series resistor feedback matching technique

d. Inductive Source Degeneration architecture

The inductive source degeneration architecture is popular with input matching technique of LNA. [1], [5]-[7], [10], [13]-[18], [24], [26]-[30]. This matching technique provides a perfect matching without adding any noise to the system or giving any restrictions on the device gm. It uses an inductor as a source degeneration device and has another inductor connecting to the gate as shown in Figure 2.16.

Figure 2.16 Inductive source degeneration matching technique

Using the small signal analysis and neglecting Cgd of transistor M1, the impedance looking through the gate inductor can be written as:

( ) 1

in g s T s

gs

Z j L L L

ω

j C

ω

= + +

ω

+ (2.29)

Chapter 2 Basic Concepts of LNA Design

Where _T ^m

gs

g

ω =C (2.30)

At the resonance frequency where the inductor impedance and capacitor impedance are canceled out, the input impedance is then just the last term in the equation (2.29).

The tuned impedance is given by:

In Figure 2.17 shows the equivalent model of the inductive source degeneration architecture, the quality factor of the circuit is given by:

gs eq

Q C R

= ω

(2.33)

The effectively increase the transconductance of the input transistor by a factor can written as

G

_m

= Qg

_m. In typical narrow band matching, the quality factor is usually around 3-5. Assuming that the matching network is lossless, helps to reduce the input-referred added noise by a factor of Q as well as increasing the voltage gain of the circuit by the same factor.

Figure 2.17 Equivalent circuit of inductive source degeneration matching

Chapter 2 Basic Concepts of LNA Design

e. LNA design and comparison of input matching architecture

In general, the following should be considered in LNA design:

a. Input and Output matching (return loss): In wireless receiver, the component placed before LNA is usually the filter and antenna with characteristic impedance 50Ω, so input impedance matching of LNA must be matching to close to 50Ω. But, the input impedance matching is always different from the optimum noise matching.

b. Low Noise Figure (NF): The low noise figure of the LNA is dominates all noise figure of the entire receiver system. Thus, noise figure of LNA is the most important parameters to evaluate the performance. The low noise figure and low power dissipation are well-known that two issues are trade-offs one another.

c. Sufficient power gain: The sufficient power gain of the LNA is important, because it amplify the receiver RF signal and reduce the noise contribution from the following stages. But, the larger power gain will degrade the linearity of LNA.

d. Low power dissipation: Design a wide band low noise amplifier, the low power issue is important, but it trade off with noise figure and power gain.

Chapter 2 Basic Concepts of LNA Design

Table 2.1 Comparison of LNA input matching architecture Input matching architecture

Good narrow band input- matching.

Best noise performance.

Good power gain.

Good linearity.

Large area.

Chapter 2 Basic Concepts of LNA Design

2.3 Methods to Reduce Noise Figure of LNA

Due to the various requirements of low noise amplifiers, the low noise characteristic.

There are several methods to reduce the noise figure were proposed [6], [14], [31], [34].

2.3.1 External gate-source capacitor method

Since the induced gate current noise grows with the gate-source capacitance (Cgs), the addition gate-source capacitor (CE) can reduce the noise figure from the induced gate current noise by reducing Cgs. The input stage of LNA with an external capacitor (CE) is shown in Figure 2.18.

Figure 2.18 LNA with an external capacitor (CE) The input impedance of circuit in Figure 2.20 can be given by:

( ) 1

The quality factor Q of the input circuit is:

0 0

The noise figure can be derived as [1]

2

Chapter 2 Basic Concepts of LNA Design

From equation (2.36), the value of Q from Cgs allows for an adjustable Q for any given Cgs to reduce the noise figure [1].

2.3.2 Thermal noise canceling method

Figure 2.19 illustrates that a thermal noise canceling method with straightforward implementation using an ideal feed-forward voltage amplifier A with a gain -Av (with Av>0) [6].

Figure 2.19 LNA exploiting noise canceling with a plus adder By circuit inspection, the matching device noise voltages at node X and Y are

, , ,

The output noise voltage due to the noise of the matching device, Vout,n,i is then equal to

, , , , , ,

Output noise cancellation, Vout,n,i=0, is achieved for a gain AV equal to

, ,

Chapter 2 Basic Concepts of LNA Design

2.3.3 Gate-drain overlap capacitance neutralization method

The feedback from the gate-drain overlap capacitance (Cgd) can not be ignored in the high frequency, which leads to input matching and gain degradation. To reduce the feedback effect is by using cascade architecture, which leads to low voltage technique.

The inductor-tuned technique can be implemented as shown in Figure 2.20.

Figure 2.20 LNA with gate-drain overlap capacitance

It may not be suitable for on-chip implementations because the required inductance to resonant the Cgd is quite large for on-chip integration.

2.3.4 Quality factor (Q) of inductor enhancement method

Integrated high-Q inductors can improve the performance and integration-level of RFIC’s while reducing their power dissipation and cost. Poor quality factors of on-chip matching inductors are affects the noise at high frequency. A new implementation of high quality factor (Q) copper inductor on CMOS silicon substrate using a fully process is presented. The Q factor of such inductors depends upon the conductivity of metal layer and other parasitic components. Planner spirals can be of different shapes i.e.

square, hexagonal, octagonal and circular as shown in Figure 2.21.

Chapter 2 Basic Concepts of LNA Design

Figure 2.21 On-chip Planner Spiral Inductors of different shapes

Chapter 3 Design of the Lower Power Ultra-Wideband LNA

Chapter 3 Design of the Low Power Ultra-Wideband Low Noise Amplifier

3.1 Introduction

In this chapter, instead of using a common source amplifier, a common-gate amplifier is proposed for wideband input matching of UWB LNAs. It is well known that compared with using the common source amplifier, using the common gate amplifier can easily achieve wideband input matching, good linearity, and input-output isolation, but provides lower gain and higher noise figure. The π-section LC network technique is employed in the LNA to achieve sufficient gain with a reasonable noise figure level.

The gain flatness throughout the band is within ± 1.0dB. Here, we also propose a structure to combine the common gate with band pass filters, which can reduce parasitic capacitance of the transistor and leads low power consumption.

3.2 Proposed Low Power UWB LNA architecture

Bandwidth, power consuming, input impedance matching, noise figure, and

Chapter 3 Design of the Lower Power Ultra-Wideband LNA

reasonable power gain, are the major issues to be considered in the circuit design. It is well-known that these four issues are trade-offs one another [44]. Here, achieving optimum low power performance is our first priority. Our proposed UWB LNA circuit is shown in Figure 3.1, which employs the CMOS process. The LNA is composed by an input matching network and a π-section LC network.

Figure 3.1 Proposed Common-Gate UWB LNA, which is filter configuration

3.2.1 Wideband Input Matching Design

Here, a common-gate amplifier is used as an important component for the input matching network of the proposed LNA. Although the common gate amplifier can easily achieve wideband input matching, good linearity, and input-output isolation, its parasitic capacitances of the transistor, will degrade the LNA performance in the high frequency region. Therefore, a two-order band pass filter is also introduced to reduce the parasitic capacitance. Demonstrates the proposed input matching network, which is composed of a common gate amplified and a two-order band pass filter, and its small signal equivalent circuit model are shown in Figure 3.2.

Chapter 3 Design of the Lower Power Ultra-Wideband LNA

Figure 3.2 Common gate LNA input stage, which 2^nd band-pass filter, and small signal equivalent circuit model

In the equivalent circuit (Figure 3.2), ZL is the input impedance of the cascode stage and gm1 is the transconductance of the MOS transistor in common gate configuration, Ro is the parasitic resistance of the transistor. L1, C1, Ls, and C2+Cgs are lumped-element circuits for the two order band-pass filter. Series and shunt L-C tanks are used to adjust the pass band and the ripple. Based on band pass filter design fundamental [43], L1, C1, Ls, and C2+Cgs are given by, respectively, empirical constants and are equal to 1.5963 and 1.0967, respectively [43]. The matching network is adopted for noise and impedance match to the 50 Ohm source with

Chapter 3 Design of the Lower Power Ultra-Wideband LNA

L1=0.9nH, C1=850fF, Ls=3.50nH, C2+Cgs=240fF, which reflection coefficient and gain response simulation shown in Figure 3.3.

Figure 3.3 Reflection coefficient and gain response of 2^nd band-pass filter

With the small signal equivalent circuit model (Figure 3.2), the input impedance of the MOS transistor can be treated as a series RLC circuit and is written as below:

1

From the smith chart in Figure 3.4, shows the reflection coefficient S11 of the proposed low power UWB low noise amplifier with a structure to combine the common gate with band pass filters and compares that of the amplifier without band pass filters.

The addition of band pass filters gathers the values of input reflection coefficient S11

Chapter 3 Design of the Lower Power Ultra-Wideband LNA

coefficient with feedback circuit for frequency range is close to 50Ω matching.

Figure 3.4 The smith chart of input reflection coefficient with 2^nd band-pass filter

3.2.2 π-section LC network Design

Flat gain over the entire bandwidth, is another important requirement of the UWB LNA design. However, the shunt of M1’s gate-drain parasitic capacitance, Cgd1 , and M2’s gate-source parasitic capacitance, Cgs2 , provides an additional path for the RF signal current to the ground, which leads to power gain reduction especially for the high frequency band. In order to solve this problem, a π-section LC network technique is first adopted and proposed for our design. Figure 3.5 (b) shows the circuit of the π-section LC network, which is formed by an inductor and the gate-source parasitic capacitances.

The small signal equivalent circuit of the π-section LC network circuit is illustrated in Figure 3.6. Id1 is the small signal drain current of M1. L2 is the introduced passive inductor. Ro and Co represent the parasitic resistance and capacitance of the inductor, respectively. Ro is the series resistance and is around 3 to 20 Ohms, and Co is the fringing field capacitance of the spiral, which is also called ”feed-through capacitance”.

Chapter 3 Design of the Lower Power Ultra-Wideband LNA

Figure 3.5 (a) Proposed low power LNA, and (b) π-section LC network of proposed LNA.

Figure 3.6 π-section small signal equivalent circuit model

After some derivations, the π-section LC network circuit gain, Vd1/Id1, is found and given by

Chapter 3 Design of the Lower Power Ultra-Wideband LNA capacitance between the spiral and the substrate. Rsub, and Csub are silicon substrate resistance and silicon substrate capacitance, respectively, which are relatively small and are neglected. Then, equation (3.6) becomes

1

Z(ω)=Vd1/Id1 is the input impedance of π-section LC network. To achieve a flat gain, finding a proper L2 is needed to make Z(ω) close to 50 Ohm through out the whole band.

From the smith chart in Figure 3.7, shows the reflection coefficient of π-section input reflection coefficient with different inductor L2..

Figure 3.7 Reflection coefficient of π-section with different inductor L2.

It is found from Figure 3.8 that L2=3 nH yields a satisfied flat gain within a variation of

±1.5 dB relative to the average. Therefore, inductor L2=3 nH is chosen for later simulation

Chapter 3 Design of the Lower Power Ultra-Wideband LNA

Figure 3.8 Power gain versus signal frequency with L2

3.2.3 Low power Design

The low dc current technique and low voltage technique are employed to attain the low power for the ultra-wideband low noise amplifier design, which used in proposed common gate LNA (chapter 3), and common source LNA (chapter 4).

A. Low direct current design

The low direct current design is used in proposed common gate UWB LNA design. The typical common gate LNA is shown in Figure 3.9.

Figure 3.9 Input impedance of typical common gate LNA The input impedance of the common gate amplifier in Figure 3.9 can be written

Chapter 3 Design of the Lower Power Ultra-Wideband LNA

The input impedance is approximately as

1

1

in m

Z ≈ g in the low frequency. It has to be matched to the 50Ohm. The common gate architecture (or the 1/gm termination) that is illustrate in Figure 3.10 (a) has the highest potential to achieve the wideband input impedance Z_in ≈ Ω . However, the drain current50 D ¹₂ n ox

(

gs thn

)

² 3.10 (c), we proposed a structure to combine the common gate with band pass filters technique, which can achieve the impedance transformations and leads low power consumption. The impedance transformations technique is shown in Figure 3.11 and its using two order band pass filter to achieve this design.

Figure 3.10 A flow chart of proposed low direct current design

Chapter 3 Design of the Lower Power Ultra-Wideband LNA

Figure 3.11 The impedance transformations technique with using band pass filter

B. Low voltage design

The bottle-neck for the low voltage design is the limitation of threshold voltage because it is not anticipated to decrease much below. The conventional cascode architecture amplifier shown in Figure 3.12 (a), it require a high supply voltage and not suitable for low voltage application. In order to overcome this problem, the cascade architecture with two LC tanks, as shown in Figure 3.12 (b). The RF signal is amplified by common-source and blocking capacitor couples the signal to common gate.

Figure 3.12 (a) Conventional cascode architecture LNA, (b) Low voltage LC tank cascade LNA.

The low voltage LNA needs two LC tanks and a large blocking capacitor which

Chapter 3 Design of the Lower Power Ultra-Wideband LNA

results in a large chip area. In order to solve this problem, a solution to the reduce

results in a large chip area. In order to solve this problem, a solution to the reduce

在文檔中 低功率、低電壓之超寬頻低雜訊放大器設計 (頁 23-0)