CHAPTER 3 Design of Low power Ultra-Wideband Low Noise
3.3 Simulation Results
Figure 3.14 shows the layout of the proposed UWB LNA. The size of the layout area is 0.89mm by 0.77mm including pads. And the measure PCB is shown in Figure 3.15.
In Figure 3.16, S11 and S22 versus signal frequency are illustrated. It is found that the input reflection S11＜-10.44dB and output matching S22<-12.05dB in the range of 3.1~10.6 GHz. The power gain (S21) is around 10.0~12.4dB. 3dB bandwidth of the LNA is 7.8 GHz and is satisfied the need of UWB. The noise figure of the LNA is shown in Figure 3.17. It is found that the noise figure is at least less than 4.4dB in 3.1~10.6GHz and its minimum value is 3.25dB at 8.5GHz. The linearity of an amplifier is traditionally described in terms of 1-dB compression point (P1dB) and third-order intercept point (IP3). However, the IP3 of the proposed LNA is not of great concern of this work due to the two reasons: Firstly, the UWB signals are intrinsically wideband signals rather than single tones in narrowband systems, which bring about the difficulty in defining the IP3 for the LNA. The simulation results also show that the output third-order-intercept points (OIP3s) are 7.669dBm at 3GHz, 5.33dBm at 5GHz, 5.09dBm at 6GHz, 4.24dBm at 8GHz, 2.23dBm at 10GHz. A low supply voltage of 1.5V is chosen, and the total power consumption is 3.0mW.
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.14 Layout of the proposed UWB LNA
Figure 3.15 Measure PCB of the proposed UWB LNA
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.16 S-parameters versus signal frequency
Figure 3.17 Noise figure versus signal frequency with or without Rb.
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
The performance of the proposed LNA is summarized in Table 3.1, with comparison to other recently published ultra-wideband LNAs’ simulation results.
Table 3.1
Summary of LNA performance and comparison with published LNAs
Ref. Tech. BW
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.18 Linearity parameters P1dB at 3GHz Linearity parameters P1dB can be explained by Figure 3.21.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =10+(-12)=-2dBm Simulation results of P1dB=-3.3dBm.
Figure 3.19 Linearity parameters OIP3 at 3GHz Linearity parameters OIP3 can be explained by Figure 3.22.
OIP3=Pout+1
2IMD=-10.443+1
2(46.667-10.443)=7.669dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.20 Linearity parameters P1dB at 4GHz Linearity parameters P1dB can be explained by Figure 3.23.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =11.5+(-16)=-5.5dBm Simulation results of P1dB=-5.8dBm.
Figure 3.21 Linearity parameters OIP3 at 4GHz Linearity parameters OIP3 can be explained by Figure 3.24.
OIP3=Pout+1
2IMD=-9.29+1
2(40.868-9.29)=6.49dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.22 Linearity parameters P1dB at 5GHz Linearity parameters P1dB can be explained by Figure 3.25.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =12+(-17)=-5dBm Simulation results of P1dB=-6.3dBm.
Figure 3.23 Linearity parameters OIP3 at 5GHz Linearity parameters OIP3 can be explained by Figure 3.26.
OIP3=Pout+1
2IMD=-8.816+1
2(37.119-8.816)=5.33dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.24 Linearity parameters P1dB at 6GHz Linearity parameters P1dB can be explained by Figure 3.27.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =12.44+(-19)=-6.56dBm Simulation results of P1dB=-7.8dBm.
Figure 3.25 Linearity parameters OIP3 at 6GHz Linearity parameters OIP3 can be explained by Figure 3.28.
OIP3=Pout+1
2IMD=-8.682+1
2(36.229-8.682)=5.09dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.26 Linearity parameters P1dB at 7GHz Linearity parameters P1dB can be explained by Figure 3.29.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =12.44+(-20)=-7.56dBm Simulation results of P1dB=-8.8dBm.
Figure 3.27 Linearity parameters OIP3 at 7GHz Linearity parameters OIP3 can be explained by Figure 3.30.
OIP3=Pout+1
2IMD=-8.85+1
2(35.802-8.85)=4.62dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.28 Linearity parameters P1dB at 8GHz Linearity parameters P1dB can be explained by Figure 3.31.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =12.44+(-21)=-8.56dBm Simulation results of P1dB=-9.84dBm.
Figure 3.29 Linearity parameters OIP3 at 8GHz Linearity parameters OIP3 can be explained by Figure 3.32.
OIP3=Pout+1
2IMD=-9.051+1
2(35.647-9.051)=4.24dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.30 Linearity parameters P1dB at 9GHz Linearity parameters P1dB can be explained by Figure 3.33.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =12.44+(-21)=-8.56dBm Simulation results of P1dB=-9.67dBm.
Figure 3.31 Linearity parameters OIP3 at 9GHz Linearity parameters OIP3 can be explained by Figure 3.34.
OIP3=Pout+1
2IMD=-8.92+1
2(33.864-8.92)=3.55dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.32 Linearity parameters P1dB at 10.6GHz Linearity parameters P1dB can be explained by Figure 3.35.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =10+(-14)=-4dBm Simulation results of P1dB=-5.7dBm.
Figure 3.33 Linearity parameters OIP3 at 10.6GHz Linearity parameters OIP3 can be explained by Figure 3.36.
OIP3=Pout+1
2IMD=-10.324+1
2(36.826-10.324)=2.93dBm
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
Chapter 4 Design of the Low Voltage Ultra-Wideband Low Noise Amplifier
4.1 Introduction
A very low-voltage ultra-wideband (UWB) low-noise amplifier (LNA) is achieved by reducing transistor’s threshold voltage using an external bias to the transistor body node. To achieve ultra-wideband input impedance matching, a novel design is proposed for the LNA by adding a feedback resistor Rf to a conventional LNA cascode architecture. Based on TSMC 0.18μm 1P6M process, the numerical result shows that the LNA has 11.8～14.0dB gain from 6 GHz to 10.0 GHz with input matching S11<-13.7dB and 2.81dB noise figure in 7.0GHz. It only dissipates 2.8 mW with a small power supply of 0.75V.
4.2 Proposed LNA with feedback resistor architecture
The proposed ultra-wideband Low Noise Amplifier architecture is shown in Figure 4.1, which is different from the conventional narrowband cascode Low Noise Amplifier
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
architecture [8], [17] by adding a feedback circuit. In Figure 4.2, Rf is added as a feedback element to the conventional cascode narrowband and Low Noise Amplifier and Ld, and Rd are used as peaking loads at the output [1], [10]. The capacitor Cf and C1
are used for ac coupling capacitors. The Sources-follower buffer M3 is designed for output matching, with the bias current at 5mA.
Figure 4.1 Conventional narrowband cascode LNA
Figure 4.2 The proposed ultra-wideband LNA, which is resistor feedback configuration
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
4.2.1 Resistive shunt feedback technique
The resistor feedback configuration is the most common method of negative feedback technique. First, determination of feedback resistance value Rf is important. In the proposed Low Noise Amplifier, the values of feedback resistors Rf (300-2000Ω) are employed to produce the wideband input impedance matching, without affecting the Noise Figure (NF) significantly. Due to the Noise Figure of the feedback amplifier cannot be optimized without sacrificing other important performance such as gain, gain flatness, input/output return loss.
Table 4.1 represents the minimum Noise Figure (NFmin), gain flatness, and input return loss (S11) of the feedback amplifier by different resistance values. In order to achieve a gain flatness of between 6.0-10.6 GHz, return loss S11<-10dB of 6.0GHz-10.6 GHz, and the noise figure of less than 2.5dB, the feedback resistance was chosen to between 800Ω and 1000Ω. Therefore, the Low Noise Amplifier can be tuned to achieve proper resistance value Rf for a wideband frequency range.
Table 4.1 Effect on feedback resistance
Feedback Rf NFmin Gain Flatness (-3dB range) Return Loss S11< -10dB
300 Ω 2.9 dB 6.9-11.3 GHz 2.0-8.7 GHz wideband Low Noise Amplifier with feedback resistor Rf=1000Ω and compares that of
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
the values of input reflection coefficient S11 closer to the center of the smith chart. The orbit of input impedance reflection coefficient with feedback circuit for frequency range is close to 50Ω matching. 3dB bandwidth of the LNA is 6.4 GHz and input matching
<-10dB bandwidth is 5.25GHz (Figure 4.4), which satisfied the need of UWB in the range of 6~10.6 GHz. The resistive and capacitive shunt feedbacks (Rf, Cf) also improve the better stability, gain flatness, and bandwidth.
Figure 4.3 The smith chart of input impedance matching (Rf=1000Ω)
Figure 4.4 Bandwidth with Rf=1000Ω to compare with the case without Rf
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
4.2.2 Noise analysis
For proposed Ultra-wideband Low Noise Amplifier (Figure 4.2), its noise equivalent circuit of the input is shown in Figure 4.5
Figure 4.5 Noise equivalent circuit of the input stage of proposed ultra-wideband LNA.
The noise factor for an amplifier is defined as:
F ≣ Total output noise
Total output noise due to the source (4.1)
As equation (4.1) shows, the noise factor equals to total output noise divided by source induced output noise. In order to calculate it, we evaluate the noise contribution from the input source. First the input equivalent Gm is
1 1 2 2
, where Q is the effective Q value for the input network of Low Noise Amplifier in (LNA). The power spectral density (PSD, Sx( )f ) of voltage for the source resistance Rs is equal to
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
obtain the first component of the output noise power density due to the 50Ω source is
2
From Figure 4.5, the output noise power spectral density (PSD) for the resistances Rl, Rg, and Rfm can be written as
The dominant noise contributor internal to the LNA is the channel current noise of the first MOS device. The output noise power density from this source is
2
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
We can express noise factor (F) as:
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
(4.4) (4.5) (4.12) (4.4)
Total output noise
F Total output noise due to the source
+ +
ω <<1, Noise Factor (F) can be determined as
0 1
To validate our derivation, comparison between the formulated and simulated Noise Figures of the input stage is shown in Figure 4.6. The comparison shows that Noise Figure (formulate and simulated) of the proposed Ultra wideband Low Noise Amplifier with feedback resistor Rf=1000Ω and compares that of the amplifier without feedback resistor Rf can be predicted well by using equation (4.15).
The addition of feedback resistor Rf increase the values of the Noise Figure (Figure 4.6), but also increase bandwidth for proposed Low Noise Amplifier (Figure 4.2). The Noise Figure is plotted in Figure 4.7 for the five cases of power dissipation. It is clear that the optimum QL for a fixed power dissipation.
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
Figure 4.6 Noise Figure versus Frequency (Formulated and Simulated)
Figure 4.7 Theoretical predictions of Noise Figure for several power dissipations.
4.2.3 A novel method to reduce LNA Noise Figure
In this section, a noise-reduction method using Source-Body Resistance (Rsb) technique is proposed. It is found that the method can effectively reduce the noise figure of the proposed Ultra-wideband LNA.
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
a. Substrate thermal noise reduced by adding an external resistance
In CMOS technology, the substrate parasitic impedance can induce the substrate thermal noise of RFIC circuits due to the leaky current through the drain/source to the substrate. Here, a simple method by adding an external resistance between the source and the body is proposed to reduce the thermal noise. To explore the method, a small signal equivalent circuit model of the substrate with an added resistor is developed and is shown in Figure 4.8.Figure 4.8 Equivalent circuit model of the substrate with an added resistor Rbx, which is located between the body node and the source node of transistor, and Rb, Rsb, Rdb represent the effective substrate model.
The input impedance of the substrate, Zsub is derived and given as:
0 0
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
From equation (4.18), increase of the added resistance, Rbx leads to a reduction of the equivalent substrate resistance Rsub, which validates our proposed method.
In this section, the proposed method is applied to UWB LNA to validate its effectiveness. Figure 4.9 illustrates the proposed UWB LNA architecture with an external resistance Rbx added to the transistor M1. To explore the noise figure of the LNA, the noise factor is derived first and is equal to the ratio between the input noise power and the output noise power of the circuit.
According to the proposed UWB LNA and using the substrate model shown in Figure 4.9. Its shows that the small-signal equivalent circuit for substrate model with add resistor (Rbx). The resistor Rbx is an additional resistor which is connected between the body node and source node of transistor M1. Resistor Rbx helps to improve the high frequency performance of the LNA noise figure.
Figure 4.9 The small-signal equivalent circuit for substrate model with add resistor (Rbx)
b. Substrate noise analysis and simulation
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
Amplifier. Here we will derive the noise figure according to small signal model. To obtain the expression for noise figure, it is instructive to calculate the transfer functions of the input/output noise sources in the LNA. The small signal equivalent circuit used in the computation is shown in Figure 4.10, and Zsub represents simplified the substrate parasitic impedance noise from the substrate model (Figure 4.9).
Figure 4.10 Noise equivalent circuit for LNA with substrate noise
out d sub
Using (4.19) to replace (4.18) can be written as
1 1 1 1
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
According to the definition, noise factor is
{ }
Using (4.24) to replace (4.23) can be written
2 2 2
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
Using (4.26) (4.27) (4.28) (4.29) (4.30) (4.31) to replace (4.25) can be written
2
Using (4.33) to replace (4.32) can be written
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA frequency, ωT is cutoff frequency. C2 is gate noise and substrate noise correction coefficients. Equation (4.34) is derived to explain why increasing resistance Zsub leads to a increasing of low noise amplifier noise factor. Determination of substrate resistance value Rbx is important. In Figure 4.11 shows that the curve becomes gentle after Rbx=10kΩ, the values of substrate resistance Rbx =10kΩ are employed to proposed low noise amplifier.
Figure 4.11 Noise Figure versus Resistor Rbx
4.2.4 Simulation results
A low supply voltage of 1.5V is chosen, and the total power consumption is 9.0mW. In Figure 4.12, S11, S12, S21, and S22 versus signal frequency are illustrated.
It is found that the input reflection S11＜-11.72dB and output matching S22<-14.61dB in the range of 6~10.6 GHz. The power gain (S21) is around 12.0~14.4dB. The noise
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
figure of the proposed LNA is shown in Figure 4.13. It shows that the noise figure (NF) is smaller when Rbx=10kΩ to compare with the case without Rbx. The simulation results also show that the input third-order-intercept points (IIP3s) are -7.0dBm at 6GHz, -7.5dBm at 8GHz, -4.5dBm at 10GHz.
Figure 4.12 S-parameters versus signal frequency
Figure 4.13 Noise Figure versus signal frequency with Rbx=10kΩ to compare with the case without Rbx
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
Figure 4.14 Linearity parameters P1dB at 6GHz Linearity parameters P1dB can be explained by Figure 4.21.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =14.3+(-19)=-4.7dBm Simulation results of P1dB=-3.3dBm.
Figure 4.15 Linearity parameters OIP3 at 6GHz Linearity parameters OIP3 can be explained by Figure 4.22.
OIP3=Pout+1
2IMD=-6.689+1
2(32.662-6.689)=6.3dBm
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
Figure 4.16 Linearity parameters P1dB at 7GHz Linearity parameters P1dB can be explained by Figure 4.21.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =14.5+(-20)=-5.5dBm Simulation results of P1dB=-6.6dBm.
Figure 4.17 Linearity parameters OIP3 at 6GHz Linearity parameters OIP3 can be explained by Figure 4.22.
OIP3=Pout+1
2IMD=-6.686+1
2(31.284-6.686)=5.7dBm
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
Figure 4.18 Linearity parameters P1dB at 8GHz Linearity parameters P1dB can be explained by Figure 4.21.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =14.4+(-21)=-6.6dBm Simulation results of P1dB=-7.7dBm.
Figure 4.19 Linearity parameters OIP3 at 8GHz Linearity parameters OIP3 can be explained by Figure 4.22.
OIP3=Pout+1
2IMD=-7.041+1
2(31.072-7.04)=5dBm
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
Figure 4.20 Linearity parameters P1dB at 9GHz Linearity parameters P1dB can be explained by Figure 4.21.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =13.9+(-22)=-8.1dBm Simulation results of P1dB=-9.2dBm.
Figure 4.21 Linearity parameters OIP3 at 9GHz Linearity parameters OIP3 can be explained by Figure 4.22.
OIP3=Pout+1
2IMD=-7.7353+1
2(32.533-7.735)=4.7dBm
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
Figure 4.22 Linearity parameters P1dB at 10GHz Linearity parameters P1dB can be explained by Figure 4.21.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =12.2+(-19)=-6.8dBm Simulation results of P1dB=-8dBm.
Figure 4.23 Linearity parameters OIP3 at 10GHz Linearity parameters OIP3 can be explained by Figure 4.22.
OIP3=Pout+1
2IMD=-8.79+1
2(35.249-8.79)=3dBm
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
4.3 Proposed UWB LNA with low voltage design
In this section, a very low-voltage UWB LNA is achieved by reducing transistor’s threshold voltage using an external bias to the transistor body node. Here, our proposed UWB LNA not only achieves low voltage requirement but also takes care of other issues.
4.3.1 Threshold Voltage
The threshold voltage of a MOS transistor is calculated for circuit analysis:
0
( 2 2 )
th th F BS F
V = V + γ φ − V − φ
, (4.35) where Vth0 is the value of Vth with VBS=0, γ is the body effect coefficient, and ΦF is the strong inversion surface potential of the transistors. In Figure 4.24 shows that a VGS>Vth will be turn on NMOS transistor.
Figure 4.24 NMOS I/V characteristic
In Figure 4.25 (a), if a MOSFET is off (in depletion region), we actually have to apply a VGS<Vth to turn off the NMOS. If a MOSFET is on (in strong inversion region or saturation region), we actually have to apply a VGS
≥
Vth to turn on the NMOS and will generation of conduction channels as shown in Figure 4.25 (b).Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
Figure 4.25 Depletion region and Inversion region (saturation region) with (a) VGS<Vth, (b) VGS
≥
Vth of NMOS transistorsFigure 4.26 VGS (min Vth) with or without VBS
Figure 4.26 illustrates the threshold voltage is decreased as the external bias VBS is increased (Vth1 is with external bias VBS=0.6V and Vth2 is without external bias VBS).
From equation (4.35), it is found that the threshold voltage is decreased as the bias VBS
is increased as shown in Figure 4.27. To reduce the threshold voltage as much as
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
Figure 4.27 Threshold voltage Vth as a function of external bias VBS
The cascode LNA architecture is widely used design, but requires a high supply voltage (>0.9V), which employs two transistors stacked. In Figure 4.28, the transistor M1 and M2 shows a device I-V curves without external bias VBS. If fixed dc current 3mA, the supply voltage VDS (VDD) is varied between 0.9V and 1.8V with transistor working in the saturation region. Also in Figure 4.29, an external bias VBS=0.6 voltage is employed to forward-bias the body-source junction of transistor M1 and M2. The supply voltage VDS (VDD) is varied between 0.65V and 1.8V with transistor working in the saturation region.
Figure 4.28 Device I-V Curves without external bias VBS
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
Figure 4.29 Device I-V Curves with external bias VBS=0.6
Here the supply voltage is very low of 0.75V compare with others [1], [7], [8], [15] , [10] with dc current 3.8mA. In our design, an external bias is employed to the transistor body node as shown Fig.4.30, which leads to transistor’s threshold voltage (Vth) reduction and supply voltage from 0.65V to 1.8V. The very low voltage design of the proposed UWB LNA is shown in Figure 4.30. A VBS=0.6 voltage is employed to forward-bias the body-source junction of transistor M1 and M2. The supply voltage VDD
can be variation to between 0.65V and 1.8V with transistor working in saturation region.
We chose the supply voltage 0.75V with dc current is 3.8mA and power consumption is 2.8mW.
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
4.3.2 Simulation results
In Figure 4.31, input matching S11, power gain S21, reverse isolation and output matching versus signal frequency are illustrated. The power gain S21 with proposed UWB LNA (VDD=1.8V, Power=11.6mW) and proposed low voltage UWB LNA (VDD=0.75V, Power=2.8mW) are small than -13.7dB in the range of 6.0~10.6 GHz as shown in Figure 4.32. The noise figure (NF) of proposed low voltage UWB LNA compare with proposed UWB LNA is shown in Figure 4.33. It is found that the noise figure is at least less than 3.6dB in 6.0~10.6GHz and its minimum value is 2.8dB at 7 GHz. The output third-order-intercept points (OIP3s) are 7.669dBm at 6GHz, 5.0dBm at 8GHz, 4.53dBm at 10GHz. The performance of the proposed UWB LNA with low voltage technique is summarized in Table 4.2, with comparison with other recently published UWB LNAs’ simulation results.
In Figure 4.31, input matching S11, power gain S21, reverse isolation and output matching versus signal frequency are illustrated. The power gain S21 with proposed UWB LNA (VDD=1.8V, Power=11.6mW) and proposed low voltage UWB LNA (VDD=0.75V, Power=2.8mW) are small than -13.7dB in the range of 6.0~10.6 GHz as shown in Figure 4.32. The noise figure (NF) of proposed low voltage UWB LNA compare with proposed UWB LNA is shown in Figure 4.33. It is found that the noise figure is at least less than 3.6dB in 6.0~10.6GHz and its minimum value is 2.8dB at 7 GHz. The output third-order-intercept points (OIP3s) are 7.669dBm at 6GHz, 5.0dBm at 8GHz, 4.53dBm at 10GHz. The performance of the proposed UWB LNA with low voltage technique is summarized in Table 4.2, with comparison with other recently published UWB LNAs’ simulation results.