CHAPTER 2 Basic Concepts of Low Noise Amplifier Design
2.3 Methods to Reduce Noise Figure of LNA
Due to the various requirements of low noise amplifiers, the low noise characteristic.
There are several methods to reduce the noise figure were proposed [6], [14], [31], [34].
2.3.1 External gate-source capacitor method
Since the induced gate current noise grows with the gate-source capacitance (Cgs), the addition gate-source capacitor (CE) can reduce the noise figure from the induced gate current noise by reducing Cgs. The input stage of LNA with an external capacitor (CE) is shown in Figure 2.18.
Figure 2.18 LNA with an external capacitor (CE) The input impedance of circuit in Figure 2.20 can be given by:
( ) 1
The quality factor Q of the input circuit is:
0 0
The noise figure can be derived as [1]
2
Chapter 2 Basic Concepts of LNA Design
From equation (2.36), the value of Q from Cgs allows for an adjustable Q for any given Cgs to reduce the noise figure [1].
2.3.2 Thermal noise canceling method
Figure 2.19 illustrates that a thermal noise canceling method with straightforward implementation using an ideal feed-forward voltage amplifier A with a gain -Av (with Av>0) [6].
Figure 2.19 LNA exploiting noise canceling with a plus adder By circuit inspection, the matching device noise voltages at node X and Y are
, , ,
The output noise voltage due to the noise of the matching device, Vout,n,i is then equal to
, , , , , ,
Output noise cancellation, Vout,n,i=0, is achieved for a gain AV equal to
, ,
Chapter 2 Basic Concepts of LNA Design
2.3.3 Gate-drain overlap capacitance neutralization method
The feedback from the gate-drain overlap capacitance (Cgd) can not be ignored in the high frequency, which leads to input matching and gain degradation. To reduce the feedback effect is by using cascade architecture, which leads to low voltage technique.
The inductor-tuned technique can be implemented as shown in Figure 2.20.
Figure 2.20 LNA with gate-drain overlap capacitance
It may not be suitable for on-chip implementations because the required inductance to resonant the Cgd is quite large for on-chip integration.
2.3.4 Quality factor (Q) of inductor enhancement method
Integrated high-Q inductors can improve the performance and integration-level of RFIC’s while reducing their power dissipation and cost. Poor quality factors of on-chip matching inductors are affects the noise at high frequency. A new implementation of high quality factor (Q) copper inductor on CMOS silicon substrate using a fully process is presented. The Q factor of such inductors depends upon the conductivity of metal layer and other parasitic components. Planner spirals can be of different shapes i.e.
square, hexagonal, octagonal and circular as shown in Figure 2.21.
Chapter 2 Basic Concepts of LNA Design
Figure 2.21 On-chip Planner Spiral Inductors of different shapes
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Chapter 3 Design of the Low Power Ultra-Wideband Low Noise Amplifier
3.1 Introduction
In this chapter, instead of using a common source amplifier, a common-gate amplifier is proposed for wideband input matching of UWB LNAs. It is well known that compared with using the common source amplifier, using the common gate amplifier can easily achieve wideband input matching, good linearity, and input-output isolation, but provides lower gain and higher noise figure. The π-section LC network technique is employed in the LNA to achieve sufficient gain with a reasonable noise figure level.
The gain flatness throughout the band is within ± 1.0dB. Here, we also propose a structure to combine the common gate with band pass filters, which can reduce parasitic capacitance of the transistor and leads low power consumption.
3.2 Proposed Low Power UWB LNA architecture
Bandwidth, power consuming, input impedance matching, noise figure, and
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
reasonable power gain, are the major issues to be considered in the circuit design. It is well-known that these four issues are trade-offs one another [44]. Here, achieving optimum low power performance is our first priority. Our proposed UWB LNA circuit is shown in Figure 3.1, which employs the CMOS process. The LNA is composed by an input matching network and a π-section LC network.
Figure 3.1 Proposed Common-Gate UWB LNA, which is filter configuration
3.2.1 Wideband Input Matching Design
Here, a common-gate amplifier is used as an important component for the input matching network of the proposed LNA. Although the common gate amplifier can easily achieve wideband input matching, good linearity, and input-output isolation, its parasitic capacitances of the transistor, will degrade the LNA performance in the high frequency region. Therefore, a two-order band pass filter is also introduced to reduce the parasitic capacitance. Demonstrates the proposed input matching network, which is composed of a common gate amplified and a two-order band pass filter, and its small signal equivalent circuit model are shown in Figure 3.2.
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.2 Common gate LNA input stage, which 2nd band-pass filter, and small signal equivalent circuit model
In the equivalent circuit (Figure 3.2), ZL is the input impedance of the cascode stage and gm1 is the transconductance of the MOS transistor in common gate configuration, Ro is the parasitic resistance of the transistor. L1, C1, Ls, and C2+Cgs are lumped-element circuits for the two order band-pass filter. Series and shunt L-C tanks are used to adjust the pass band and the ripple. Based on band pass filter design fundamental [43], L1, C1, Ls, and C2+Cgs are given by, respectively, empirical constants and are equal to 1.5963 and 1.0967, respectively [43]. The matching network is adopted for noise and impedance match to the 50 Ohm source with
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
L1=0.9nH, C1=850fF, Ls=3.50nH, C2+Cgs=240fF, which reflection coefficient and gain response simulation shown in Figure 3.3.
Figure 3.3 Reflection coefficient and gain response of 2nd band-pass filter
With the small signal equivalent circuit model (Figure 3.2), the input impedance of the MOS transistor can be treated as a series RLC circuit and is written as below:
1
From the smith chart in Figure 3.4, shows the reflection coefficient S11 of the proposed low power UWB low noise amplifier with a structure to combine the common gate with band pass filters and compares that of the amplifier without band pass filters.
The addition of band pass filters gathers the values of input reflection coefficient S11
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
coefficient with feedback circuit for frequency range is close to 50Ω matching.
Figure 3.4 The smith chart of input reflection coefficient with 2nd band-pass filter
3.2.2 π-section LC network Design
Flat gain over the entire bandwidth, is another important requirement of the UWB LNA design. However, the shunt of M1’s gate-drain parasitic capacitance, Cgd1 , and M2’s gate-source parasitic capacitance, Cgs2 , provides an additional path for the RF signal current to the ground, which leads to power gain reduction especially for the high frequency band. In order to solve this problem, a π-section LC network technique is first adopted and proposed for our design. Figure 3.5 (b) shows the circuit of the π-section LC network, which is formed by an inductor and the gate-source parasitic capacitances.
The small signal equivalent circuit of the π-section LC network circuit is illustrated in Figure 3.6. Id1 is the small signal drain current of M1. L2 is the introduced passive inductor. Ro and Co represent the parasitic resistance and capacitance of the inductor, respectively. Ro is the series resistance and is around 3 to 20 Ohms, and Co is the fringing field capacitance of the spiral, which is also called ”feed-through capacitance”.
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.5 (a) Proposed low power LNA, and (b) π-section LC network of proposed LNA.
Figure 3.6 π-section small signal equivalent circuit model
After some derivations, the π-section LC network circuit gain, Vd1/Id1, is found and given by
Chapter 3 Design of the Lower Power Ultra-Wideband LNA capacitance between the spiral and the substrate. Rsub, and Csub are silicon substrate resistance and silicon substrate capacitance, respectively, which are relatively small and are neglected. Then, equation (3.6) becomes
1
Z(ω)=Vd1/Id1 is the input impedance of π-section LC network. To achieve a flat gain, finding a proper L2 is needed to make Z(ω) close to 50 Ohm through out the whole band.
From the smith chart in Figure 3.7, shows the reflection coefficient of π-section input reflection coefficient with different inductor L2..
Figure 3.7 Reflection coefficient of π-section with different inductor L2.
It is found from Figure 3.8 that L2=3 nH yields a satisfied flat gain within a variation of
±1.5 dB relative to the average. Therefore, inductor L2=3 nH is chosen for later simulation
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.8 Power gain versus signal frequency with L2
3.2.3 Low power Design
The low dc current technique and low voltage technique are employed to attain the low power for the ultra-wideband low noise amplifier design, which used in proposed common gate LNA (chapter 3), and common source LNA (chapter 4).
A. Low direct current design
The low direct current design is used in proposed common gate UWB LNA design. The typical common gate LNA is shown in Figure 3.9.
Figure 3.9 Input impedance of typical common gate LNA The input impedance of the common gate amplifier in Figure 3.9 can be written
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
The input impedance is approximately as
1
1
in m
Z ≈ g in the low frequency. It has to be matched to the 50Ohm. The common gate architecture (or the 1/gm termination) that is illustrate in Figure 3.10 (a) has the highest potential to achieve the wideband input impedance Zin ≈ Ω . However, the drain current50 D 12 n ox
(
gs thn)
2 3.10 (c), we proposed a structure to combine the common gate with band pass filters technique, which can achieve the impedance transformations and leads low power consumption. The impedance transformations technique is shown in Figure 3.11 and its using two order band pass filter to achieve this design.Figure 3.10 A flow chart of proposed low direct current design
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.11 The impedance transformations technique with using band pass filter
B. Low voltage design
The bottle-neck for the low voltage design is the limitation of threshold voltage because it is not anticipated to decrease much below. The conventional cascode architecture amplifier shown in Figure 3.12 (a), it require a high supply voltage and not suitable for low voltage application. In order to overcome this problem, the cascade architecture with two LC tanks, as shown in Figure 3.12 (b). The RF signal is amplified by common-source and blocking capacitor couples the signal to common gate.
Figure 3.12 (a) Conventional cascode architecture LNA, (b) Low voltage LC tank cascade LNA.
The low voltage LNA needs two LC tanks and a large blocking capacitor which
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
results in a large chip area. In order to solve this problem, a solution to the reduce threshold voltage is employed to low voltage technique. The threshold voltage problem comes from the well-known relationship as given
0
( 2 2 )
th th F BS F
V = V + γ φ − V − φ
(3.10) , where Vth0 is the value of V with Vth BS=0, γ is the bulk threshold parameter andφF is the strong inversion surface potential of the MOSFET. To reduce the threshold voltage as much as possible, we want to the bias VBS as high as possible. In Figure 3.13 (a) the allowable voltages cascode architecture with inductive source degeneration is a popular configuration for LNA design. If M1and M2 are both in saturation, then VX is determined primarily by Vb2: VX=Vb2(=VDD)-Vgs2. For M2 to be saturated, VDD≧Vb2(=VDD)-Vthn, that is, VDD≧Vgs1-Vthn+Vgs2-Vthn if Vb2 is chosen to place M1 at the edge of saturation. But it has not very low voltage supply applications because the power supply must satisfy the following a requirement VDD + VSS ≥2Vthn. The VDD
and VSS are the positive and negative power supply, Vthn is the threshold voltage of the each of the NMOS transistor.
Figure 3.13 (a)The allowable voltages, and (b) low voltage design of the cascode architecture LNA.
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
The low voltage design of the cascode LNA is shown in Figure 3.13 (b). A VBS=0.6 voltage is employed to forward-bias the body-source junction of transistor M1
and M2. The VDD can be attained to 0.7V with dc current is 4.5mA. The proposed Low-voltage technique can be explained by UWB feedback LNA architecture is taken up in the next chapter.
3.3 Simulation Results
Figure 3.14 shows the layout of the proposed UWB LNA. The size of the layout area is 0.89mm by 0.77mm including pads. And the measure PCB is shown in Figure 3.15.
In Figure 3.16, S11 and S22 versus signal frequency are illustrated. It is found that the input reflection S11＜-10.44dB and output matching S22<-12.05dB in the range of 3.1~10.6 GHz. The power gain (S21) is around 10.0~12.4dB. 3dB bandwidth of the LNA is 7.8 GHz and is satisfied the need of UWB. The noise figure of the LNA is shown in Figure 3.17. It is found that the noise figure is at least less than 4.4dB in 3.1~10.6GHz and its minimum value is 3.25dB at 8.5GHz. The linearity of an amplifier is traditionally described in terms of 1-dB compression point (P1dB) and third-order intercept point (IP3). However, the IP3 of the proposed LNA is not of great concern of this work due to the two reasons: Firstly, the UWB signals are intrinsically wideband signals rather than single tones in narrowband systems, which bring about the difficulty in defining the IP3 for the LNA. The simulation results also show that the output third-order-intercept points (OIP3s) are 7.669dBm at 3GHz, 5.33dBm at 5GHz, 5.09dBm at 6GHz, 4.24dBm at 8GHz, 2.23dBm at 10GHz. A low supply voltage of 1.5V is chosen, and the total power consumption is 3.0mW.
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.14 Layout of the proposed UWB LNA
Figure 3.15 Measure PCB of the proposed UWB LNA
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.16 S-parameters versus signal frequency
Figure 3.17 Noise figure versus signal frequency with or without Rb.
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
The performance of the proposed LNA is summarized in Table 3.1, with comparison to other recently published ultra-wideband LNAs’ simulation results.
Table 3.1
Summary of LNA performance and comparison with published LNAs
Ref. Tech. BW
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.18 Linearity parameters P1dB at 3GHz Linearity parameters P1dB can be explained by Figure 3.21.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =10+(-12)=-2dBm Simulation results of P1dB=-3.3dBm.
Figure 3.19 Linearity parameters OIP3 at 3GHz Linearity parameters OIP3 can be explained by Figure 3.22.
OIP3=Pout+1
2IMD=-10.443+1
2(46.667-10.443)=7.669dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.20 Linearity parameters P1dB at 4GHz Linearity parameters P1dB can be explained by Figure 3.23.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =11.5+(-16)=-5.5dBm Simulation results of P1dB=-5.8dBm.
Figure 3.21 Linearity parameters OIP3 at 4GHz Linearity parameters OIP3 can be explained by Figure 3.24.
OIP3=Pout+1
2IMD=-9.29+1
2(40.868-9.29)=6.49dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.22 Linearity parameters P1dB at 5GHz Linearity parameters P1dB can be explained by Figure 3.25.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =12+(-17)=-5dBm Simulation results of P1dB=-6.3dBm.
Figure 3.23 Linearity parameters OIP3 at 5GHz Linearity parameters OIP3 can be explained by Figure 3.26.
OIP3=Pout+1
2IMD=-8.816+1
2(37.119-8.816)=5.33dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.24 Linearity parameters P1dB at 6GHz Linearity parameters P1dB can be explained by Figure 3.27.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =12.44+(-19)=-6.56dBm Simulation results of P1dB=-7.8dBm.
Figure 3.25 Linearity parameters OIP3 at 6GHz Linearity parameters OIP3 can be explained by Figure 3.28.
OIP3=Pout+1
2IMD=-8.682+1
2(36.229-8.682)=5.09dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.26 Linearity parameters P1dB at 7GHz Linearity parameters P1dB can be explained by Figure 3.29.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =12.44+(-20)=-7.56dBm Simulation results of P1dB=-8.8dBm.
Figure 3.27 Linearity parameters OIP3 at 7GHz Linearity parameters OIP3 can be explained by Figure 3.30.
OIP3=Pout+1
2IMD=-8.85+1
2(35.802-8.85)=4.62dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.28 Linearity parameters P1dB at 8GHz Linearity parameters P1dB can be explained by Figure 3.31.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =12.44+(-21)=-8.56dBm Simulation results of P1dB=-9.84dBm.
Figure 3.29 Linearity parameters OIP3 at 8GHz Linearity parameters OIP3 can be explained by Figure 3.32.
OIP3=Pout+1
2IMD=-9.051+1
2(35.647-9.051)=4.24dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.30 Linearity parameters P1dB at 9GHz Linearity parameters P1dB can be explained by Figure 3.33.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =12.44+(-21)=-8.56dBm Simulation results of P1dB=-9.67dBm.
Figure 3.31 Linearity parameters OIP3 at 9GHz Linearity parameters OIP3 can be explained by Figure 3.34.
OIP3=Pout+1
2IMD=-8.92+1
2(33.864-8.92)=3.55dBm
Chapter 3 Design of the Lower Power Ultra-Wideband LNA
Figure 3.32 Linearity parameters P1dB at 10.6GHz Linearity parameters P1dB can be explained by Figure 3.35.
P1dB=P1dB(dBm)=G1dB(dB)+IP1dB(RF_pwr)(dBm) =10+(-14)=-4dBm Simulation results of P1dB=-5.7dBm.
Figure 3.33 Linearity parameters OIP3 at 10.6GHz Linearity parameters OIP3 can be explained by Figure 3.36.
OIP3=Pout+1
2IMD=-10.324+1
2(36.826-10.324)=2.93dBm
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
Chapter 4 Design of the Low Voltage Ultra-Wideband Low Noise Amplifier
4.1 Introduction
A very low-voltage ultra-wideband (UWB) low-noise amplifier (LNA) is achieved by reducing transistor’s threshold voltage using an external bias to the transistor body node. To achieve ultra-wideband input impedance matching, a novel design is proposed for the LNA by adding a feedback resistor Rf to a conventional LNA cascode architecture. Based on TSMC 0.18μm 1P6M process, the numerical result shows that the LNA has 11.8～14.0dB gain from 6 GHz to 10.0 GHz with input matching S11<-13.7dB and 2.81dB noise figure in 7.0GHz. It only dissipates 2.8 mW with a small power supply of 0.75V.
4.2 Proposed LNA with feedback resistor architecture
The proposed ultra-wideband Low Noise Amplifier architecture is shown in Figure 4.1, which is different from the conventional narrowband cascode Low Noise Amplifier
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
architecture [8], [17] by adding a feedback circuit. In Figure 4.2, Rf is added as a feedback element to the conventional cascode narrowband and Low Noise Amplifier and Ld, and Rd are used as peaking loads at the output [1], [10]. The capacitor Cf and C1
are used for ac coupling capacitors. The Sources-follower buffer M3 is designed for output matching, with the bias current at 5mA.
Figure 4.1 Conventional narrowband cascode LNA
Figure 4.2 The proposed ultra-wideband LNA, which is resistor feedback configuration
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
4.2.1 Resistive shunt feedback technique
The resistor feedback configuration is the most common method of negative feedback technique. First, determination of feedback resistance value Rf is important. In the proposed Low Noise Amplifier, the values of feedback resistors Rf (300-2000Ω) are employed to produce the wideband input impedance matching, without affecting the Noise Figure (NF) significantly. Due to the Noise Figure of the feedback amplifier cannot be optimized without sacrificing other important performance such as gain, gain flatness, input/output return loss.
Table 4.1 represents the minimum Noise Figure (NFmin), gain flatness, and input return loss (S11) of the feedback amplifier by different resistance values. In order to achieve a gain flatness of between 6.0-10.6 GHz, return loss S11<-10dB of 6.0GHz-10.6 GHz, and the noise figure of less than 2.5dB, the feedback resistance was chosen to between 800Ω and 1000Ω. Therefore, the Low Noise Amplifier can be tuned to achieve proper resistance value Rf for a wideband frequency range.
Table 4.1 Effect on feedback resistance
Feedback Rf NFmin Gain Flatness (-3dB range) Return Loss S11< -10dB
300 Ω 2.9 dB 6.9-11.3 GHz 2.0-8.7 GHz wideband Low Noise Amplifier with feedback resistor Rf=1000Ω and compares that of
Chapter 4 Design of the Low Voltage Ultra-Wideband LNA
the values of input reflection coefficient S11 closer to the center of the smith chart. The orbit of input impedance reflection coefficient with feedback circuit for frequency range is close to 50Ω matching. 3dB bandwidth of the LNA is 6.4 GHz and input matching
<-10dB bandwidth is 5.25GHz (Figure 4.4), which satisfied the need of UWB in the range of 6~10.6 GHz. The resistive and capacitive shunt feedbacks (Rf, Cf) also improve the better stability, gain flatness, and bandwidth.
Figure 4.3 The smith chart of input impedance matching (Rf=1000Ω)
Figure 4.3 The smith chart of input impedance matching (Rf=1000Ω)