Ching-Wei Tsai, Howard C.-H. Wang, Min-Hwa Chi, and Denny D. Tang, Fellow, IEEE
Abstract—A positive bias temperature instability (PBTI)
recov-ery transient technique is presented to investigate trap properties in HfSiON as high-k gate dielectric in nMOSFETs. Both large-and small-area nMOSFETs are characterized. In a large-area device, the post-PBTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped electron emission from HfSiON gate dielectric, which is manifested by a staircase-like drain current evolution with time, is observed during recovery. By measuring the temper-ature and gate voltage dependence of trapped electron emission times, the physical mechanism for PBTI recovery is developed. An analytical model based on thermally assisted tunneling can successfully reproduce measured transient characteristics. In ad-dition, HfSiON trap properties, such as trap density and activation energy, are characterized by this method.
Index Terms—HfSiON, high-k trap properties, positive bias
temperature instability (PBTI) recovery transient, single electron emission, thermally assisted tunneling.
I. INTRODUCTION
T
HE AGGRESSIVE CMOS device scaling has been reach-ing the physical limit of conventional SiO2MOSFETs asa result of significant direct tunneling current through ultrathin oxides [1]. The resultant intolerable standby power consump-tion has made further oxide scaling impractical. To resolve this dilemma, high-permittivity (high-k) materials have emerged as a post-SiO2solution [2]. Among the candidates, Hf-based
ma-terials are most promising, and considerable efforts have been devoted to their film compositions [3], [4], process optimization [5], [6], as well as reliability assessment and analysis [7]–[9]. Recently, HfSiON has been successfully integrated into CMOS devices as gate dielectric for low-power applications with good reliability, comparable mobility (as SiO2), and greatly reduced
gate leakage [6].
Manuscript received June 30, 2005. This work was supported by the National Science Council under Contract NSC 93-2215-E009-032 and the TSMC under the TSMC/NCTU JDP Program. The review of this paper was arranged by Editor J. Welser.
T. Wang, C.-T. Chan, and C.-J. Tang are with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: twang@cc.nctu.edu.tw).
C.-W. Tsai, H. C.-H. Wang, M.-H. Chi, and D. D. Tang are with the Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu 300, Taiwan, R.O.C.
Digital Object Identifier 10.1109/TED.2006.871849
Several reliability issues for high-k gate dielectrics are being studied, including threshold voltage (Vt) instability [10], [11], charge trapping [9], [12], degradation [13], [14], and break-down [8], [14], and [15]. Pantisano et al. reported that Vt instability in high-k gate dielectric CMOS is mainly controlled by the dynamics of electron charging/discharging in preexisting high-k bulk defects [10]. Young et al. concluded that fast elec-tron trapping is a significant source of observed device dc per-formance degradation [11]. Shanware et al. found that charge trapping in HfSiON exhibits logarithmic time dependence [9]. Crupi et al. [13] and Degraeve et al. [14] indicated that traps at shallow and deep energies are respectively responsible for Vt instability and stress-induced leakage current (SILC). Moreover, high-k bulk trap density is demonstrated to strongly correlate to yield in terms of dielectric breakdown [8]. Thermo-chemical breakdown with a leakage current acceleration model was proposed to explain high-k dielectric breakdown [15].
Unlike SiO2 gate dielectric CMOS, where negative bias
temperature instability (NBTI) in pMOSFETs dictates device lifetime [16], high-k CMOS lifetime is believed to be limited by positive bias temperature instability (PBTI) in nMOSFETs [7], [12]. Similar to NBTI effects in conventional SiO2devices,
high-k-induced PBTI degradation (charge trapping) and recov-ery (charge detrapping) are both considered to be important in determining high-k device lifetime [12], [19]. Conventionally, BTI characterization is carried out by periodically interrupting stress to measure electrical parameters, introducing a delay between stress and measurement, which may give rise to an imprecise or even incorrect result [17]–[20]. Recently, two-frequency charge pumping (CP) measurement has been utilized to characterize high-k trap properties [8], [14]. However, the CP measurement still has three drawbacks. 1) The CP current may be too small to be measured in small-size devices at a lower fre-quency. 2) Due to the mixture of interface and high-k traps, the two-frequency CP method may not be viable when high-k trap density is comparable to or even less than interface trap density. 3) CP alone cannot provide detailed description for high-k trap behavior such as trap activation energy.
In this paper, we develop a novel transient characterization technique to explore high-k trap properties by measuring the poststress recovery drain current transient in large- and small-area devices. In small-small-area devices, single-charge phenomenon
Fig. 1. (a) Schematic diagram for PBTI recovery transient measurement. High-speed switches minimize the transition delay down to the microsecond range between stress and recovery. (b) Waveforms applied to the gate and drain during stress and recovery phases.
is observed. Based on the temperature and voltage dependence of the single-charge effects, an analytical model for PBTI recovery is developed and high-k trap parameters are extracted. The model is further verified by comparison with measured transient characteristics in a large-area device.
II. PBTI TRANSIENTMEASUREMENT
The devices used in this paper are nMOSFETs with a polysil-icon electrode and a bilayered gate dielectric stack consisting of HfSiON and an interfacial SiO2layer (IL). The gate width
is 100 µm and 0.16 µm, and the gate length ranges from 80 to 220 nm. Detailed fabrication process and device characteristics can be found in [6] and [7]. The devices are first subjected to a positive gate bias (Vg) stress, and then “recover” at a lower Vg. In the “stress phase,” electrons in the inversion channel are in-jected and trapped into preexisting high-k gate dielectric traps, whereas in the “recovery phase,” the trapped charges escape via thermally assisted tunneling (TAT). The evolution of the recov-ery drain current (Id) is monitored by a special measurement setup, as shown in Fig. 1(a). A conventional “sense-after-stress” method introduces a delay between phase transitions. This delay, as has been reported in literature for both NBTI in SiO2
and PBTI in high k, leads to inaccurate experimental results [12], [17]–[20]. Thus, in our measurement setup [19], [20], a computer-controlled system including high-speed switches, an operational amplifier, and a digital oscilloscope is used to monitor Id. The delay between stress and recovery is minimized down to the microsecond range. The sampling rate is 104
read-ings per second. Fig. 1(b) depicts the waveforms applied on gate
Fig. 2. Evolutions of drain current before and after stress in a MOSFET with SiO2as gate dielectric, measured by the experimental setup in Fig. 1.
Fig. 3. Temporal evolutions of drain current before and after stress in a large-area high-k gate dielectric nMOSFET. Vg= 0.7 V, 0.2 s for stress
and Vg/Vd= 0.3 V/0.2 V for recovery. The device dimension is W/L =
100 µm/0.08 µm. The symbols represent measurement data, and the line is the calculation result from (11).
and drain during stress and recovery. The system was tested on MOSFETs with SiO2as gate dielectric and stable current–
time characteristic was obtained (Fig. 2), ensuring that the system introduces no spurious transient effect.
A. Recovery Transient in Large-Area Devices
The recovery transient of the drain current at Vg/Vd= 0.3/0.2 V in a large-area (100 µm× 0.08 µm) nMOSFET is shown in Fig. 3 after stress at Vg= 0.7 V for 0.2 s. The prestress drain current is also plotted for comparison. The poststress Id increases with a logarithmic time dependence for about four decades of time from 1 ms to 10 s and is saturated at a level close to the prestress one, suggesting full recovery for the cho-sen stress condition. Note that conventional measurement (for example, by Agilent 4156), which usually takes a few seconds between stress and recovery phase transition, is unable to mea-sure the initial transient in the millisecond range in Fig. 3 and may significantly underestimate the magnitude of the transient effect. We repeat the same measurement (stress and recovery) on a SiO2 control sample. The result is shown in Fig. 2, and
no transient effect is noticed. This comparison implies that the observed transient should arise from the high-k gate dielectric rather than from the interfacial oxide layer.
Fig. 4. Recovery drain current transients before and after stress in a small-area device. Bias conditions for stress and recovery are exactly the same as in Fig. 3. The device dimension is W/L = 0.16 µm/0.08 µm. Each current jump is attributed to single trapped charge escape from high-k gate dielectric. Only three electrons are trapped during stress. The emission time of the three trapped electrons is denoted as τ1, τ2, and τ3.
Fig. 5. Temperature dependence ofτ1. The activation energy extracted from the Arrhenius plot is 0.18 eV. Each data point is an average of ten readings.
B. Single Electron Emission in Small-Area Devices
We performed the same experiment (identical stress and recovery condition) on a small-area device (W/L = 0.16 µm/ 0.08 µm) where only a few traps are present. The recovery Id, interestingly, exhibits a staircase-like evolution, as shown in Fig. 4. The poststress drain current returns to the prestress level, suggesting again full recovery. Each current jump in Fig. 4 is believed to be due to single electron emission from traps in HfSiON gate dielectric. Here, only three electrons are trapped in the measured device during stress. In Fig. 4, individual electron emission times τ1, τ2, and τ3can be clearly defined by
this technique. We further explore the dependence of electron emission times on recovery gate voltage and temperature. We take an average of the electron emission times from ten mea-surements on the same device by repeated stress and recovery. Fig. 5 shows the temperature dependence of τ1. The extracted
activation energy (Ea) from the Arrhenius plot is about 0.18 eV. Fig. 6 shows the gate voltage dependence of the first two elec-tron emission times. Both τ1and τ2increase with recovery Vg.
III. RESULTS ANDDISCUSSION
A. Trapped Charge Emission Model
Three possible paths for electron detrapping are illustrated in the energy band diagram in Fig. 7, namely: (a) Frenkel–Poole
Fig. 6. Dependence of trapped electron emission time on recovery gate voltage. Ten measurements are made for each recovery Vgto take average.
Fig. 7. Energy band diagram illustrating possible paths for trapped charge emission: (a) F–P emission. (b) Tunneling to the gate. (c) Tunneling to the Si substrate.
(F–P) emission; (b) Shockley-Read-Hall (SRH)-like TAT to the gate electrode; and (c) TAT to the Si substrate. The detrap-ping path (a) is ruled out, because the activation energy Ea for F–P emission should be about the trap energy (>1 eV) and the measured Ea is only 0.18 eV. Path (b) is also ex-cluded, because a larger (more positive) recovery Vg would accelerate detrapping, giving a shorter charge emission time. The measured τ versus Vg is just opposite (Fig. 6). As a result, (c) is identified as the dominant path of trapped charge emission. Moreover, the temperature effect implies the role of thermal process in the charge tunneling process. As a result, an analytical model based on TAT is developed with the energy band diagram and trap distance illustrated in Fig. 8. According to the WKB approximation, the trapped charge emission time is formulated as τi−1= υ exp(−αoxTox) exp(−αkxi) (1) where υ = NC(1− fc)υthσ0 exp −Ea kT (1a) αox= 22m∗oxq(Et+ ΦB) αk= 22m∗kqEt . (1b)
Fig. 8. Schematic representation of the band diagram in recovery phase and trap positions. Eais the activation energy for SRH-like TAT.
The prefactor ν in (1) is a lumped parameter, often referred to as the “attempt-to-escape frequency,” and is expressed in (1a), where NC is the effective density-of-state in Si conduction band, fcis the Fermi–Dirac (FD) distribution function in Si sub-strate at the energy aligned to the trapped charge, NC(1− fc) is the amount of available states in Si substrate for outtunneling electrons from high-k traps, and σ0and Ea are the trap cross section and the activation energy, respectively. Other variables have their usual definitions. The FD distribution (fc) is a func-tion of Vgin recovery. A smaller recovery Vgleads to a smaller channel electron density, or a smaller fc, and thus, a shorter electron emission time. As the recovery Vg reduces below the threshold voltage, fc approaches zero, and thus, the electron emission time becomes independent of Vg, as shown in Fig. 6. The electron nearest to the interface of Si substrate will be the first for detrapping. In order to exclude the temperature effect resulting from the FD distribution, we chose a small recovery Vg(≤ 0.3V ), i.e., fc∼ 0, in the measurement of trap activation energy Eain Fig. 5.
B. High-k Bulk Trap Density
The high-k trap density (Nt) can be evaluated through the proposed analytical model. By comparing
τ1= υ−1exp(αoxTox) exp(αkx1) (2a)
τ2= υ−1exp(αoxTox) exp(αkx2) (2b)
we obtain
τ2
τ1
= exp [αk(x2− x1)] . (3)
Assuming the high-k traps have a uniform distribution in space, the high-k trap density is readily calculated as
Nt= 1 W L(x2− x1) = αk W L ln τ2 τ1 . (4)
Equation (3) predicts that the ratio of emission times (τ2/τ1) is
only related to the physical distance between trap sites. Fig. 9
Fig. 9. Ratio of τ2 to τ1 versus gate voltage in the recovery phase. Note
that τ2/τ1 remains almost unchanged with respect to Vg, as predicted by
(3). The extracted high-k trap density is 3.5× 1017 cm−3, or equivalently,
8.8× 1011cm−2.
indeed shows that τ2/τ1 (ten readings of each Vg on the same device; ten devices measured) is constant and is independent of recovery Vg. For measurement convenience, we chose certain fixed recovery currents rather than recovery voltages in Fig. 9, thus, leading to scattered data points as a result of threshold voltage variation. An average τ2/τ1 of 3.4 is obtained,
cor-responding to an average high-k trap density of Nt= 3.5× 1017cm−3(assuming m∗
k= 0.18 m0[21]), or equivalently, an
area density of 8.8× 1010cm−2.
It should be pointed out that in the analysis above, we assume single trap energy. This assumption is reasonable, as the trap energy range corresponding to stress Vg(= 0.7 V) and recovery
Vg(= 0.3 V) is very small. Only traps in this small energy range are charged and discharged in the measurement above. For a larger stress Vg, the injected electrons may fill high-k traps at different positions and energies. We will discuss this issue later.
C. Modeling of PBTI Recovery Transient in a Large-Area Device
In a large-area device, the high-k charge detrapping rate is given by Q(x, t) = Q(x, 0) exp −t τ (x) (5)
where Q(x, t) = qNt(x, t) is the time-dependent trapped charge density and τ (x) is described in (1). The threshold volt-age shift ∆Vtinduced by trapped electron emission is written as
∆Vt(t) =− i ∆Q(xi, t) C(xi) =− i qNt(xi, 0) εHK (THK− xi) 1− exp −t τi (6) where C(xi) is the corresponding capacitance for trapped charges located at xi from high-k/IL interface and εHK and
can be approximated by a step function written as exp −t A exp(−αkx) = 0 for x≤ (αk)−1ln t A 1 for x≥ (αk)−1ln t A . (8) This approximation translates into a “clear-cut” picture; after time t, electrons with emission times shorter than t are completely detrapped while all of the rest remain trapped. Therefore, (7) is further simplified as
∆Vt(t)≈ − qNt εHK (αk)−1 ln(At) 0 (THK− x)dx. (9)
The time window of interest for modeling is four decades as shown in Fig. 3. According to (3), the time span is equivalent to a physical distance of around 10 Å in high k, or an equivalent oxide thickness (EOT) of 2 Å. Therefore, the term THK− x in
(9) is approximated as a constant, or xeff, and (9) reduces to
∆Vt(t)≈ − qNtxeff εHKαk ln t A . (10)
The corresponding recovery drain current evolution in the measurement interval can be written as
∆Id(t)∝ qGmNtxeff εHKαk ln t A (11) where Gm(= dI/dV ) is the transconductance. Using the extracted Nt and Ea from a small device, the simulated recovery transient from (11) is shown in Fig. 3 and is in good agreement with the measured result. Equation (11) also reveals that the recovery slope in Fig. 3 is linearly proportional to the high-k trapped charge density.
As mentioned earlier, the injected electrons may fill differ-ent energy traps at a larger stress Vg. In this case, the trap energy distribution should be taken into account, and (11) is modified as ∆Id(t)∝ ∆E qGmNt(Et)xeff εHKαk(Et) dEt ln(t) (12)
where ∆E represents the energy range of trapped charges. Equation (12) shows that at a larger stress Vg, the recovery tran-sient still follows logarithmic time dependence but has a larger
Fig. 10. Normalized drain current evolution with recovery time for two stress
Vg(0.7 and 1 V). The Vgin the recovery phase is 0.3 V.
Fig. 11. (a) Comparison of the current jump amplitude for Lgate= 0.14 µm
and Lgate= 0.08 µm. Both devices are subject to identical stress and recovery
conditions. (b) Amplitude of the current jump versus Lgate.
slope because of a larger ∆E. Fig. 10 shows the measured recovery transients for two stress Vg. As expected, the larger stress Vgexhibits a larger slope.
Finally, the authors would like to remark that we chose a very short stress time (0.2 s) in this paper, because the purpose of this paper is to characterize the preexisting traps in HfSiON gate dielectric. For a longer stress time and a larger stress Vg, additional high-k traps will be generated. The PBTI stress-induced high-k trap creation will be explored in our future publication.
D. Gate Length Effect
The single-charge effect is investigated on devices with different gate lengths, i.e., 0.08, 0.14, and 0.22 µm. Fig. 11 shows that the quantized feature in the recovery transient is still
FETs. The quantized feature in recovery current evolution due to single-charge detrapping is observed for the first time in a small-area device. An SRH-like TAT model for high-k trapped charge emission is developed. Our model can well explain the measured electric field and temperature dependence of single-charge emission times. Our model also reveals that the recovery drain current transient in large-size devices should follow logarithmic time dependence. The high-k trap density can be extracted from charge emission times in a small device or from the drain current recovery slope in a large device. For trap activation energy, single-charge emission measurement is necessary, because the transient slope in a large device does not contain the activation energy. The proposed technique for single-charge effect characterization can provide insight into trap properties in high-k gate dielectrics in nanoscale CMOS device development.
REFERENCES
[1] S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum–mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s,” IEEE Electron Device Lett., vol. 18, no. 5, pp. 209–211, May 1997.
[2] H. Iwai, S. Ohmi, S. Akama, C. Ohshima, A. Kikuchi, I. Kashiwagi, J. Taguchi, H. Yamamoto, J. Tonotani, Y. Kim, I. Ueda, A. Kuriyama, and Y. Yoshihara, “Advanced gate dielectric materials for sub-100 nm CMOS,” in IEDM Tech. Dig., 2002, pp. 625–628.
[3] T. Watanabe, M. Takayanagi, K. Kojima, K. Sekine, H. Yamasaki, K. Eguchi, K. Ishimaru, and H. Ishiuchi, “Impact of Hf concentration on performance and reliability for HfSiON-CMOSFET,” in IEDM Tech. Dig., 2004, pp. 507–510.
[4] C. Choi, C. S. Kang, C. Y. Kang, R. Choi, H. J. Cho, Y. H. Kim, S. J. Rhee, M. Akbar, and J. C. Lee, “The effects on nitrogen and silicon profile on high-k MOSFET performance and bias temperature instability,” in VLSI
Symp. Tech. Dig., 2004, pp. 214–215.
[5] J. C. Lee, H. J. Cho, C. S. Kang, S. Rhee, Y. H. Kim, R. Choi, C. Y. Kang, C. Choi, and M. Abkar, “High-k dielectrics and MOSFET characteris-tics,” in IEDM Tech. Dig., 2003, pp. 95–98.
[6] H. C.-H. Wang, S.-J. Chen, M.-F. Wang, P.-Y. Tsai, C.-W. Tsai, T.-W. Wang, S. M. Ting, T.-H. Hou, P.-S. Lim, H.-J. Lin, Y. Jin, H.-J. Tao, S.-C. Chen, C. H. Diaz, M.-S. Liang, and C. Hu, “Low power device technology with SiGe channel, HfSiON, and poly-Si gate,” in
IEDM Tech. Dig., 2004, pp. 161–164.
[7] H. C.-H. Wang, C. W. Tsai, S. J. Chen, C. T. Chan, H. J. Lin, Y. Jin, H. J. Tao, S. C. Chen, C. H. Diaz, T. Ong, A. S. Oates, M. S. Liang, and M. H. Chi, “Reliability of HfSiON as gate dielectric for advanced CMOS technology,” in VLSI Symp. Tech. Dig., 2005, pp. 170–171.
[8] R. Degraeve, A. Kerber, P. Roussell, E. Cartier, T. Kauerauf, L. Pantisano, and G. Groeseneken, “Effect of bulk trap density on HfO2reliability and
yield,” in IEDM Tech. Dig., 2003, pp. 935–938.
[9] A. Shanware, M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, H. Bu, M. J. Bevan, R. Khamankar, S. Aur, P. E. Nicollian, J. McPherson, and L. Colombo, “Evaluation of the positive bias temperature stress stability in HfSiON gate dielectrics,” in Proc. Int. Reliab. Phys. Symp., 2003, pp. 208–213.
[10] L. Pantisano, E. Cartier, A. Kerber, R. Degraeve, M. Lorenzini, M. Rosmeulen, G. Groeseneken, and H. E. Maes, “Dynamics of threshold
[14] R. Degraeve, F. Crupi, D. H. Kwak, and G. Groeseneken, “On the defect generation and low voltage extrapolation of QBDin SiO2/HfO2stacks,”
in VLSI Symp. Tech. Dig., 2004, pp. 140–141.
[15] T. Yamaguchi, I. Hirano, R. Iijima, K. Sekine, M. Takayanagi, K. Eguchi, Y. Mitani, and N. Fukushima, “Thermochemical understanding of dielec-tric breakdown in HfSiON with current acceleration,” in Proc. Int. Reliab.
Phys. Symp., 2005, pp. 67–74.
[16] N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, and T. Horiuchi, “The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling,” in VLSI Symp. Tech.
Dig., 1999, pp. 73–74.
[17] S. Rangan, N. Mielke, and E. C. C. Yeh, “Universal recovery behavior of negative bias temperature instability,” in IEDM Tech. Dig., 2003, pp. 341–344.
[18] M. Denais, A. Bravaix, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier, Y. Rey-Tauriac, and N. Revil, “On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET’s,” in IEDM Tech. Dig., 2004, pp. 109–122.
[19] C. T. Chan, C. J. Tang, C. H. Kuo, H. C. Ma, C. W. Tsai, H. C. H. Wang, M. H. Chin, and T. Wang, “Single-electron emission of eraps in HfSiON as high-k gate dielectric for MOSFETs,” in Proc. Int. Reliab. Phys. Symp., 2005, pp. 41–44.
[20] C. T. Chan, H. C. Ma, C. J. Tang, and T. Wang, “Investigation of post-NBTI stress recovery in pMOSFETs by direct measurement of single oxide charge de-trapping,” in VLSI Symp. Tech. Dig., 2005, pp. 90–91. [21] Y. T. Hou, M. F. Li, H. Y. Yu, Y. Jin, and D. L. Kwong, “Quantum
tunneling and scalability of HfO2and HfAlO gate stacks,” in IEDM Tech. Dig., 2002, pp. 731–734.
[22] M. H. Tsai, T. P. Ma, and T. R. Hook, “Channel length dependence of random telegraph signal in sub-micron MOSFETs,” IEEE Electron
Device Lett., vol. 15, no. 12, pp. 504–506, Dec. 1994.
Tahui Wang (S’85–M’86–SM’94) was born in Tao-Yuan, Taiwan, R.O.C., on May 3, 1958. He re-ceived the B.S.E.E. degree from the National Taiwan University, Taipei, Taiwan, R.O.C., and the Ph.D. degree in electrical engineering from the University of Illinois, Urbana-Champaign, in 1980 and 1985, respectively.
From 1985 to 1987, he was with Hewlett-Packard Laboratories, Palo Alto, CA, where he was engaged in the development of GaAs high-electron mobility transistor devices and circuits. Since 1987, he has been with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., where he is currently a Professor. His research interests include hot carrier phenomena characterization and reliability physics in very large scale integration devices, RF CMOS devices, and non-volatile semiconductor devices.
Dr. Wang is a recipient of the Best Teaching Award by the Ministry of Education, R.O.C. He has served as a Technical Committee Member of many international conferences, among them IEDM, IRPS, and VLSI-TSA. He was an Invited Speaker of the 2003 IEDM on the topic of nitride flash reliability.
Chun-Jung Tang was born in Tai-Nan, Taiwan, R.O.C., in 1982. He received the B.S. degree in electronics engineering from the National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 2004. He is currently working toward the Ph.D. degree at the National Chiao-Tung University.
His research interests include electrical charac-terization and reliability models in high-k CMOS devices.
Ching-Wei Tsai was born in Tao-Yuan, Taiwan, R.O.C. He received the B.S. and Ph.D. degrees from the National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1998 and 2003, respectively, both in electronics engineering.
In 2003, he joined the Taiwan Semiconduc-tor Manufacturing Company (TSMC), Hsinchu, where he is currently with the Department of Ex-ploratory Technology Development. His research interests include ultrathin gate dielectric reliability of MOSFETs and nonvolatile memory devices such as flash memories and FeRAMs.
metal gate, and strained-Si technologies for sub-65-nm node CMOS device technology. He is the holder of 13 U.S. patents and has authored and coauthored 15 papers in technical journals and conferences.
Dr. Wang was a member (2004, 2005) of the CMOS Devices Subcommittee for the International Electron Devices Meeting (IEDM).
Min-Hwa Chi, photograph and biography not available at the time of publication.
Denny D. Tang (S’69–M’74–SM’85–F’90), photograph and biography not available at the time of publication.
