A Low-Power K-Band CMOS Current-Mode Up-Conversion Mixer Integrated with VCO

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(1)IEICE TRANS. ELECTRON., VOL.E92–C, NO.10 OCTOBER 2009. 1291. PAPER. A Low-Power K-Band CMOS Current-Mode Up-Conversion Mixer Integrated with VCO∗ Wen-Chieh WANG†a) , Student Member and Chung-Yu WU†b) , Member. SUMMARY A low-power K-band CMOS current-mode up-conversion mixer is proposed. The proposed mixer is realized using four analog current-squaring circuits. This current-mode up-conversion mixer is fabricated in 0.13-μm 1P8M triple-well CMOS process, and has the measured power conversion gain of −5 dB. The fabricated CMOS up-conversion mixer dissipates only 3.1 mW from a 1-V supply voltage. The VCO can be tuned from 20.8 GHz to 22.7 GHz. Its phase noise is −108 dBc/Hz at 10-MHz offset frequency. It is shown that the proposed mixer has great potential for low-voltage and low-power CMOS transmitter front-ends in advanced nano-CMOS technologies. key words: CMOS, current-mode, K-band, up-conversion mixer. 1.. Introduction. Over the last decade, the rapid growth in the field of RF wireless applications has led to considerable effort being expended in the design of high-performance and low-cost RF integrated circuits (RFICs) in advanced CMOS technologies. In addition to the application in the industrial, scientific, and medical (ISM) radio band within 24–24.25 GHz, the FCC has opened the 22–29-GHz frequency band in 2002 for short-range automotive radar systems and autonomous cruise control (ACG) systems [1]. Therefore, the design of K-band CMOS RFICs has become very important for these applications. As the CMOS technology reaches the scale of nanometer nodes, the supply voltage is reduced accordingly to around 1 V or less. The lower the supply voltage, the smaller the voltage headroom left for designing CMOS RFICs. Since a large voltage swing is required to keep signal information in voltage-mode circuits, voltage-mode circuits gradually face the problem of insufficient voltage headroom and become difficult to operate under lower supply voltage. As a result, different circuit design techniques need to be explored. Current-mode circuit techniques offer the opportunity for low-voltage operations due to the signal information being mainly carried with the time-varying current signals. Therefore, it is possible to design current-mode circuits suitable for smaller voltage headroom. Moreover, a summation Manuscript received January 18, 2009. Manuscript revised May 2, 2009. † The authors are with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan. ∗ This work was supported in part by the National Science Council (NSC), Taiwan, under the Grant NSC 96-2221-E-009-179. a) E-mail: wangste@ieee.org b) E-mail: cywu@alab.ee.nctu.edu.tw DOI: 10.1587/transele.E92.C.1291. of current signals can easily be realized by connecting signal paths together without the use of additional amplifiers; thus, further saving power. With the afore-mentioned advantages, the current-mode circuit techniques offer great potential in the design of RFICs in nano-CMOS technologies. Among all proposed current-mode CMOS RF frontend circuits [2]–[6] so far, a 24-GHz CMOS current-mode power amplifier is proposed in [2] which offers large output power with high power-added efficiency. Both the K-band current-mode CMOS receiver [3] and the 24-GHz CMOS current-mode transmitter [4] as proposed by the present authors have demonstrated the advantages of low supply voltage and low power consumption. A CMOS current-mode preamplifier with low voltage and low power dissipation is presented in [5]. Moreover, a 2-GHz current-mode selfswitching up-converter with a 1-V supply is also proposed in [6]. It requires a LO signal power as small as −15 dBm; however, it dissipates 49 mW. Generally, a large LO signal power of more than 0 dBm is required for voltage-mode mixers, Gilbert-type mixer [7] and dual-gate mixer [8] for example. The high voltage swing is in general required to keep signal information. Nevertheless, the voltage headroom has gradually become insufficient for nano-CMOS technologies which utilize low voltage supplies. In short, these problems may make it difficult for voltage-mode mixers to maintain their operating performance in advanced nano-CMOS technologies. In this work, a current-mode design technique for Kband RF double-balanced up-conversion mixer has been proposed and been verified through a silicon-proven chip in 0.13-μm CMOS process. The short channel effects of this current-mode mixer are also analyzed. The design goal of the proposed current-mode up-conversion mixer is to investigate the new design concept in the CMOS RF front-end circuits. The desired conversion gain is 0 dB at the operation frequency of 24-GHz band with the power consumption as small as possible. The measurement results have demonstrated that the proposed mixer has advantages of a small power dissipation of 3.1 mW from a low power supply of 1 V. Besides, a small LO signal power level of −4 dBm is required to achieve the measured power conversion gain of −5 dB. In Sect. 2, the analyses and implementations of the circuits are described. The measurement results are presented in Sect. 3. Finally, the conclusion is given in Sect. 4.. c 2009 The Institute of Electronics, Information and Communication Engineers Copyright .

(2) IEICE TRANS. ELECTRON., VOL.E92–C, NO.10 OCTOBER 2009. 1292. Fig. 1. 2.. The circuit of double-balanced current-mode up-conversion mixer.. Circuit Analysis and Implementation. 2.1 Double-Balanced Current-Mode Up-Conversion Mixer The circuit diagram of the proposed double-balanced CMOS up-conversion mixer is shown in Fig. 1. The core of the mixer is composed of four analog current-squaring circuits which are originally modified from [9]. The transistors M1 –M4 are biased in the saturation region. The bulk and source of M2 and M4 are separated to reduce the parasitic capacitances at the nodes N1 and N2 . Lower signal loss is achieved due to smaller parasitic capacitances appeared at nodes N1 and N2 . With the resistor R1 (R2 ), the impedance of the path from the node N1 (N2 ) to ground through the source-to-bulk parasitic capacitance of M2 (M4 ) is increased. Hence, the signal loss to ground is further reduced. The squaring circuit is improved by adding the transistor M4 which acts as a current buffer and keeps the VDS of M3 the same as the VDS of M1 in order to alleviate the channel length modulation. The current i1 is multiplied by the current-mirror circuit formed by M1 and M3 where the aspect ratio of M3 is N times that of M1 . The sum of the gateto-source voltages of M1 and M2 is kept constant and equal to VDD . Based on the square-law drain current equation for simplicity, the relationship between iin and iO is expressed as [4] ⎛ 2 ⎞ ⎜⎜⎜ iin ⎟⎟ iin ⎜ iO = N × i1 = N ⎝ + IB ⎟⎟⎠ + (1) 16IB 2 1 W (2) IB ≡ kn (VDD − 2Vth )2 8 L where Vth is the threshold voltage, W/L is the channel width to channel length ratio of the MOS devices, and kn = μnCox is the zero vertical-field mobility μn multiplied by the oxide capacitance per unit area Cox . From the first term of (1), the current-squaring function is realized. The second and third terms of (1) are unwanted components and are to be. removed. The four inputs of the mixer are iin1 = (ilo+,1 +ii f +,1 ), iin2 = (ilo−,1 +ii f −,1 ), iin3 = (ilo+,2 +ii f −,2 ), and iin4 = (ilo−,2 +ii f +,2 ). ii f +,1 , ii f −,1 , ii f +,2 , and ii f −,2 are two-pair differential IF signals where ii f +,1 = ii f +,2 = ii f + = IIF cos ωIF t and ii f −,1 = ii f −,2 = ii f − = −IIF cos ωIF t. Furthermore, ilo+,1 , ilo−,1 , ilo+,2 and ilo−,2 are two-pair differential LO signals where ilo+,1 = ilo+,2 = ilo+ = ILO cos ωLO t and ilo−,1 = ilo−,2 = ilo− = −ILO cos ωLO t. The summation of IF and LO current signals is performed by directly connecting the wires of LO and IF together without additional power dissipations. With the differential LO and IF signals, the LO and IF leakages which result from the second term of (1) can be eliminated at the mixer output if the output currents iO1 − iO4 of the four current-squaring circuits are summed together as iOP = (iO1 + iO2 ) and iOM = (iO3 + iO4 ). The summations of current signals are performed using wire connections. In addition, the even-order harmonics resulted from square terms of LO and IF current signals are eliminated by the subtraction of iOP and iOM . Some circuits that perform subtraction of current signals have been reported [10], [11]. As for the circuit in [10], current signals flowing through two unequal paths will result in gain and phase differences, and additional poles will lead to signal losses in high frequency. Besides, higher voltage headroom and additional power are required. In [11], LC network is adopted to perform current subtraction. However, only it can have good subtraction only at the resonant frequency. In the proposed design, the transformer XFMR1 is adopted to achieve high frequency and wideband subtraction of current signals. The XFMR1 avoids excessive voltage drop. This also ensures that the proposed mixer operates well at a low power supply. From (1) and with the four inputs of the mixer, the resultant RF output current ir f = η(iOP − iOM ) can be derived as ηNILO IIF ir f = [cos (ωLO +ωIF ) t+cos (ωLO −ωIF ) t] (3) 4IB where η represents the losses from the on-chip transformer XFMR1 and the output impedance matching network. From.

(3) WANG and WU: A LOW-POWER K-BAND CMOS CURRENT-MODE UP-CONVERSION MIXER INTEGRATED WITH VCO. 1293. (3), it can be seen that the mixer function is realized. With the exclusion of the losses η, the intrinsic current conversion gain CGintrinsic of the proposed current-mode mixer is expressed as CGintrinsic ≡ =. (iOP − iOM )|ω=(ωLO +ωIF ) or ω=(ωLO −ωIF ) 2(i − i ) if+. NILO . 16IB. i f − ω=ω IF. (4). As can be seen from (4), the intrinsic current conversion gain is proportional to the magnitude of the LO current ILO . The designed parameters (W/L) of M1 , M2 , M3 and M4 of the current-squaring circuit in Fig. 1 are (6 μm/0.13 μm), (6 μm/0.13 μm), (48 μm/0.13 μm), and (48 μm/0.13 μm), respectively. Moreover, R1 and R2 are with the value of 8 kΩ. In the advanced deep sub-micron CMOS technologies, the relationship between the drain current iDS and the gate overdrive voltage vOV = (vGS − Vth ) of CMOS devices is not exactly square due to short channel effects. As the proposed mixer is designed in the supply voltage of 1 V, the threshold voltages Vth of M1 and M2 are about 420 mV and 500 mV, and the gate-to-source voltages vGS of M1 and M2 are about 455 mV and 545 mV, respectively. M1 and M2 are operated in the saturation region, and the vOV of M1 and M2 are small. Hence, the drain current iDS is approximated as the following equation to analyze the second-order effects of the proposed mixer [3]. iDS ≈. 1 W 2 kn v (1 + λvDS ) . 2 L OV. χ1 ≈ 0.68, χ2 ≈ 0.97, and χ3 ≈ 1.38. Furthermore, the above derivations only consider body effect and channel length modulation effect, and the rest of short channel effects are ignored because of small vOV . From the above derivations (4), (6) and (7), the current conversion gain with the channel length modulation effect can be further expressed as CGintrinsic,short ≈ χ1. NILO . 16IB. (10). This indicates that the conversion gain of the mixer with short-channel devices is less than that of the mixer with long-channel devices. Besides, the parameter λ that models channel length modulation has a significant effect on CGintrinsic . Under the simulated conditions of the IF Frequency at 200 MHz and the LO frequency at 24 GHz, the relationship among the simulated CGintrinsic , the equivalent calculated input LO power PLO,IN , and the amplitude of the differential LO current signal idiff −loin = 2(ilo+ −ilo− ) is depicted in Fig. 2. It can be seen that the simulated CGintrinsic is higher than 0 dB if the amplitude of idiff −loin is greater than 1.5 mA or PLO,IN is greater than −8.2 dBm. Shown in Fig. 3 is the relationship between the simulated CGintrinsic and the amplitude of differential IF current signal idiff −ifin = 2(ii f + − ii f − ). When. (5). where the coefficient λ models the effect of the channel length modulation which is related to vDS . Although both M1 and M2 are with the same device size and are diode-connected, the drain-to-source voltages of M1 and M2 are different due to the fact that the latter suffers from body effect. Therefore, the channel length modulation effect should be considered. From Fig. 1, VDD = (vDS ,M1 + vDS ,M2 ). If δ = (vDS ,M2 − vDS ,M1 )/2 is assumed, vDS ,M1 = (VDD − 2δ)/2 and vDS ,M2 = (VDD + 2δ)/2. After some derivations, the expression iO in (1) is modified and expressed as ⎛ ⎞ i2 ⎜⎜ ⎟⎟ iin iO,short ≈ N ⎜⎜⎝χ1 in + χ2 + χ3 IB ⎟⎟⎠ (6) 16IB 2. Fig. 2 The relation among simulated CGintrinsic , the equivalent PLO,IN , and the amplitude of the differential LO current signal idiff −loin of the mixer.. where 2 (2+λVDD −6λδ) (7) (2+λVDD ) (2+λVDD −4λδ)+2λδ (2+λVDD +2λδ). 2 (2+λVDD ) (2+λVDD −4λδ)−(2+λVDD −2λδ)2 (8) χ2 = [(2+λVDD ) (2+λVDD −4λδ)+2λδ (2+λVDD +2λδ)] (2+λVDD ) (2+λVDD +2λδ) (2+λVDD −4λδ) . χ3 = 2 [(2+λVDD ) (2+λVDD −4λδ)+2λδ (2+λVDD +2λδ)] (9) χ1 =. Note that χ1 and χ2 are less than 1, whereas χ3 is greater than 1. As VDD = 1 V, λ ≈ 0.77 V−1 , and δ ≈ 45 mV,. Fig. 3 The relation between simulated CGintrinsic and the amplitude of the differential IF current signal idiff −ifin of the mixer..

(4) IEICE TRANS. ELECTRON., VOL.E92–C, NO.10 OCTOBER 2009. 1294. Fig. 5 Fig. 4. The circuit of IF current buffer/repeater.. The circuits of VCO and transformer-based VCO buffer/repeater.. the amplitude of idiff −loin is equal to 1 mA where the equivalent PLO,IN is equal to −11.7 dBm, the simulated CGintrinsic is −2.3 dB and the 1-dB compression point of intrinsic current conversion gain (CP1 dB ) is −0.9 dBmA. As the amplitude of idiff −loin is increased to 3 mA where the equivalent PLO,IN is equal to −2.9 dBm, the simulated CGintrinsic achieves 5 dB and the CP1 dB equals 1.8 dBmA. The operating frequency of the mixer can be altered by varying the control voltage VT 1 in order to change the values of N+/N-Well varactors C1 and C2 . The output matching network of the mixer formed by C3 , C PAD , and L1 is designed to equal 50 Ω for the purpose of measurement. 2.2 VCO, Transformer-Based VCO Buffer/Repeater and IF Current Buffer/Repeater The circuits of VCO and transformer-based VCO buffer/ repeater are shown in Fig. 4. The designed VCO is a conventional cross-coupled negative-gm oscillator which has attracted considerable interest because of its easy startup and good phase noise characteristics [12], [13]. The transistors M5 − M7 are biased in the saturation region where M5 is operated as a current source and M6 − M7 are operated to provide negative transconductances of −(gm6 /2) in order to cancel the parasitic resistances of the on-chip inductor L2 and the N+/N-well varactors C4 and C5 such that the oscillation is guaranteed. The output frequency of the VCO can be altered by varying the voltage VT 2 in order to change the values of C4 and C5 . The transformer-based VCO buffer/repeater is realized by a fully differential amplifier. M8 − M10 are biased in the saturation region. M8 with long channel length is operated as a current source and provides the capability for common-mode rejection. The design utilizes two identical on-chip transformers, XFMR2 and XFMR3 , in parallel and two N+/N-well varactors, C6 and C7 , as the load. C8 − C11 are dc blocking capacitors. The operating frequency is altered by varying the control voltage of VT 3 . As a result of the magnetic coupling of the transformers, four LO output currents ilo+,1 , ilo−,1 , ilo+,2 , and ilo−,2 are provided where ilo+,1 = ilo+,2 and ilo−,1 = ilo−,2 . The equivalent value of inductance look at the primary turn of the XFMR2 and XFMR3 in parallel of the. transformer-based VCO buffer/repeater has been design to be the same as the value of the inductance of the VCO. The device parameters of the N+/N-Well MOS varactors C4 − C7 are the same where the width is 1 μm, the length is 0.3 μm and the finger number is 32. The tuning voltage VT 3 of the transformer-based VCO buffer/repeater is tracked with the VT 2 of the VCO. Consequently, the center frequency of the narrow band transformer-based VCO buffer/repeater can be set the same as the VCO output frequency. The bandwidth of the transformer-based VCO buffer/repeater and the operation frequency of the VCO are extended by changing the resonant frequency of the LC network through varying the N+/N-Well MOS varactors C4 − C7 . Compared with generating the LO current signals ilo,1 and ilo,2 by active current mirrors with the technique of series inductive peaking to extend the bandwidth, the proposed circuit has the advantage of lower power consumption and smaller phase and magnitude differences between the two differential currents ilo,1 and ilo,2 , but at the cost of moderate increase of chip area. Shown in Fig. 5 is the IF current buffer/repeater based on current-mirror circuit. The input current signal ii f in+ is copied to two identical output current signals ii f +,1 and ii f +,2 . M11 − M16 are biased in the saturation region. Both M17 and M18 are diode-connected to provide bias voltage VB3 for M14 − M16 . C12 is the dc blocking capacitor. C13 is the bypass capacitor used to keep VB3 stable. Transistors M11 − M16 need to be laid out carefully to minimize the number of possible mismatches. 2.3 Design of On-Chip Transformer The on-chip transformer is realized with two planar symmetric windings where the primary winding is 1 turn and the secondary winding is also 1 turn. The metal structure and equivalent circuit diagram of the designed transformer are shown in Fig. 6. The drawing parameters of this on-chip transformer are with R = 80 μm, W = 9 μm, and S = 3 μm. The primary and secondary windings have center-tap point connections. This symmetric octagonal on-chip transformer is implemented by the top metal of Cu and the thickness is 3.35 μm. The equivalent relative permittivity εeff is 4.2. The electromagnetic tool HFSS is used to evaluate the performance and extract the characteristics of the designed on-.

(5) WANG and WU: A LOW-POWER K-BAND CMOS CURRENT-MODE UP-CONVERSION MIXER INTEGRATED WITH VCO. 1295. Fig. 8 The extracted coupling-coefficient kPS and quality factor Q of the designed on-chip transformer as a function of frequency.. Fig. 6 The metal structures and equivalent circuit diagram of the designed on-chip transformer.. kPS and the quality factor Q of the on-chip transformer as a function of frequency are also depicted in Fig. 8. The kPS denotes the strength of magnetic coupling between the primary and the secondary windings, and can be expressed by the mutual inductance M and self-inductances, LP,self and LS ,self , of the windings as the following. kPS = . M LP,self LS ,self. (13). The mutual inductance M is extracted from the impedance and admittance parameters as

(6). Z22 −1 M= − Z11 2 (14) Y11 ω. Fig. 7 The extracted self-inductance of the primary winding LP,self and of the secondary winding LS ,self , respectively, of the designed on-chip transformer.. chip octagonal transformers. Figure 7 illustrates the extracted self-inductance of onchip transformer as a function of frequency. The selfinductance can be derived from the impedance parameters by Im [Z11 ] ω Im [Z22 ] = ω. LP,self =. (11). LS ,self. (12). where LP,self and LS ,self presents the self-inductance of the primary and of the secondary winding, respectively. Z11 is the input impedance seen from the Port-1 (primary side) and the Port-2 (secondary side) is open circuit. In addition, Z22 is the input impedance seen from the Port-2 and the Port-1 is open circuit. Moreover, the extracted coupling-coefficient. where Y11 is the input admittance seen at the primary side when the secondary side is short circuit. From (11)–(14), it follows −1 − Z Y11 11 Z22 . (15) kPS = Im [Z11 ] Im [Z22 ] Note that the kPS has its minimum value at the self-resonant frequency. Beyond the self-resonant frequency, kPS grows over than a value of 1. However, it is not physically possible because the coupling in a passive system is limited to a maximum value of 1. In addition, such a behavior can be explained by taking (15) into consideration as the relation is validated to frequencies below resonant frequency. The quality factor of the transformer is extracted from the impedance of admittance parameters as . −1 Im [Z11 ] Im Y11 = . (16) Q= Re [Z11 ] Re Y −1 11 3.. Experimental Results. The proposed K-band current-mode up-conversion mixer was fabricated in 0.13-μm 1P8M triple-well CMOS process. The chip photo of the proposed mixer is illustrated.

(7) IEICE TRANS. ELECTRON., VOL.E92–C, NO.10 OCTOBER 2009. 1296. Fig. 9. Chip microphotograph of the current-mode up-conversion mixer.. in Fig. 9 The distance among each inductor and transformer is more than 100 μm in order to mitigate the magnetic coupling. Besides, large on-chip decoupling capacitors are placed between each bias/power supply and ground to reduce the occurrence of high-frequency noises and to obtain stable biases and supplies of the mixer. The chip area is 1.65 mm2 including testing pads. However, the dimension of the proposed current-mode up-conversion mixer itself is 0.6 mm × 0.3 mm, where the area is of 0.18 mm2 . The proposed mixer was measured through on-wafer probing. The measured return losses of the RF output port and IF input port are shown in Fig. 10(a) and Fig. 10(b), respectively. The return loss of the RF port is below −10 dB within the frequency range from 21.2 GHz to 22.8 GHz. The return loss of the IF port is below −20 dB within the frequency range from 170 MHz to 1.2 GHz. Under the 1-V supply, the proposed mixer dissipates a very small amount of power of 3.1 mW. The VCO, VCO buffer/repeater, and IF current buffer/repeater circuits dissipate 2.2 mW, 3.3 mW, and 3.1 mW, respectively. As the control voltage VT 2 is varied from 0 V to 2 V, the output frequency of the onchip VCO can be tuned from 20.8 GHz to 22.7 GHz. As the output frequency of the on-chip VCO is increased from 20.8 GHz to 22.7 GHz, the calculated LO signal power to the mixer PLO,IN is from −4 dBm to −12 dBm. Furthermore, the measured phase noise is −85 dBc/Hz and −108 dBc/Hz at 1-MHz and 10-MHz frequency offset from 22.7 GHz, respectively. The LO leakage of the proposed double-balanced mixer is around −16 dBc. The LO suppression capability is not good in this design, and it should be improved to the value of around −30 dBc. To improve the LO suppression capability, the device size of the four current-squaring circuits can be further increased to decrease the mismatch of threshold voltage due to the process variations. Moreover, symmetric layout for the differential signal paths should be carefully considered to further improve the LO suppression capability of the proposed double-balanced current-mode up-conversion mixer. The losses from the RF cables, probes, adaptors, 180◦ phase shifter, and power combiner are compensated. The. Fig. 10 (a) Measured return loss of the RF output port. (b) Measured return loss of the IF input port.. Fig. 11 Measured and post-simulated power conversion gain versus IF input power from one-tone testing result.. measured and post-simulated power conversion gains versus the IF input powers are shown in Fig. 11. In the measurement, the IF frequency is at 200 MHz, and the LO frequency is at 20.8 GHz where VT 2 is equal to 0 V. The doublesideband RF output signals are observed at the frequencies of 21 GHz (upper sideband, USB) and 20.6 GHz (lower sideband, LSB). The measured power conversion gain is about −5 dB where the losses from on-chip transformer and output matching network are included. From the EM ex-.

(8) WANG and WU: A LOW-POWER K-BAND CMOS CURRENT-MODE UP-CONVERSION MIXER INTEGRATED WITH VCO. 1297. Fig. 12 result.. Fig. 13. Measured 3rd-order intermodulation from two-tone testing. Measured conversion gain versus VCO tuning frequency.. traction by HFSS, the coupling loss of the designed on-chip transformer XFMR1 in Fig. 1 is about 5 dB in K-Band. The average single sideband (SSB) noise figure (NF) is around 12.7 dB. The measured input 1-dB compression point (IP−1 dB ) and output 1-dB compression point (OP−1 dB ) are −22 dBm and −28 dBm, respectively. The performance of intermodulation is measured by two-tone testing. Two IF inputs with the same signal power level are at the frequencies of 150 MHz and 250 MHz. The LO frequency is also tuned to 20.8 GHz where VT 2 is equal to 0 V. The measured results under these conditions are represented in Fig. 12. It reveals that the proposed mixer has the measured input 3rd-order intermodulation intercept point (PIIP3 ) and output 3rd-order intermodulation intercept point (POIP3 ) of about −9.6 dBm and −14.6 dBm, respectively. As the LO frequency is increased, the measured power conversion gain decreases because of the reduced output magnitude of on-chip VCO at the higher frequency and hence the reduced LO current signal. As shown in Fig. 13, the measured power conversion gain of the proposed mixer is from −5 dB to −14 dB and the calculated PLO,IN is reduced from −4 dBm to −12 dBm where the output frequency of on-chip VCO is tuned from 20.8 GHz to 22.7 GHz. As shown in Fig. 11, the measured power conversion gain is about −5 dB at the LO frequency of 20.8 GHz. The. measured results of the fabricated chip are close to the simulated results in the process corner SS. Due to the process variation to corner SS, the biasing current of VCO is reduced, and the gm of M6 and M7 decreases. It leads to smaller equivalent negative resistances. The output magnitude of VCO is reduced, and thus small LO current signals are generated through the transformer-based VCO buffer/repeater. The measured results well agree with the simulation results in the process corner SS. Therefore, the measured results are reasonable and can support our theory and simulated results. These initial experimental results are successful to verify the concept of the proposed low-voltage and low-power K-band CMOS current-mode up-conversion mixer. The performance of the proposed mixer is given in Table 1, along with comparisons with previously published CMOS current-mode up-conversion mixers [6]–[8]. As can be seen from Table 1, the proposed CMOS current-mode up-conversion mixer has the advantage of a very low power consumption of 3.1 mW from a 1-V power supply, which is much smaller than the CMOS current-mode self-switching up-conversion mixer [6] and the K-band CMOS voltagemode up-conversion mixers [7], [8]. Another advantage is that the proposed mixer needs the equivalent LO signal power as small as −4 dBm to achieve the measured power conversion gain of −5 dB, which is smaller than other published CMOS voltage-mode up-conversion mixers [7], [8]. The experimental results have demonstrated that the proposed mixer is successful to perform the high-frequency mixing in low-voltage and low-power operation. 4.. Conclusion. The current-mode design technique of CMOS RFICs has been developed and applied to the design of the first K-band CMOS current-mode up-conversion mixer. This currentmode mixer has been designed and fabricated in 0.13-μm 1P8M triple-well CMOS process. From the experimental results, we observe that the proposed current-mode upconversion mixer has a low power consumption of 3.1 mW under the low power supply of 1 V. In addition, a small LO signal power is required. The integrated VCO provides LO frequency from 20.8 GHz to 22.7 GHz. This work presents the first K-band CMOS current-mode upconversion mixer. The results demonstrate that the proposed current-mode mixer offers great potential for the application in low-voltage and low-power transmitter front-ends in advanced nano-CMOS technologies. Acknowledgment The authors would like to thanks the National Chip Implementation Center (CIC), National Applied Research Laboratories, Taiwan, for the fabrication of testing chip. The authors would also like the support of CAD tools HFSS, Designer/Nexxim from Ansoft Taiwan..

(9) IEICE TRANS. ELECTRON., VOL.E92–C, NO.10 OCTOBER 2009. 1298 Table 1 Performance comparison with previously published low-voltage low-power CMOS upconversion mixers.. References [1] “Federal Communications Commission,” FCC 02–04, Section XV.515.15.521. [2] C.-Y. Wu, S.-W. Hsu, and W.-C. Wang, “A 24-GHz CMOS currentmode power amplifier with high PAE and output power,” Proc. IEEE Int. Symp. Circuits and Syst., pp.2866–2869, May 2007. [3] C.-Y. Wu, W.-C. Wang, F.R. Shahroury, Z.-D. Huang, and H.-J. Zhan, “Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end,” Analog Integr. Circuits Signal Process., vol.58, no.3, pp.183–195, March 2009. [4] W.-C. Wang and C.-Y. Wu, “The 1-V 24-GHz low-voltage lowpower current-mode transmitter in 130-nm CMOS technology,” 3rd Conf. on Ph.D. Research in Microelectronics and Electronics, PRIME, pp.49–52, July 2007. [5] F. Yuan, “Low-voltage CMOS current-mode preamplifier: Analysis and design,” IEEE Trans. Circuits Syst. I, Regular Papers, vol.53, no.1, pp.26–39, Jan. 2006. [6] T. Umeda, S. Otaka, K. Kojima, and T. Itakura, “A 1 V 2 GHz CMOS up-converter using self-switching mixers,” IEEE Int. SolidState Circuits Conf. Tech. Dig., pp.402–403, Feb. 2002. [7] I.C.-H. Lai and M. Fujishima, “An integrated 20–26 GHz CMOS upconversion mixer with low power consumption,” Proc. IEEE Eur. Solid-State Circuits Conf., pp.400–403, Sept. 2006. [8] A. Verma, K.K. O, and J. Lin, “A low-power up-conversion CMOS mixer for 22–29-GHz ultra-wideband applications,” IEEE Trans. Microw. Theory Tech., vol.54, no.8, pp.3295–3300, Aug. 2006. [9] K. Bult and H. Wallinga, “A class of analog CMOS circuits based on the square-law characteristics of an MOS transistor in saturation,” IEEE J. Solid-State Circuits, vol.SC-22, no.3, pp.357–365, June 1987. [10] K. Tanno, O. Ishizuka, and T. Zheng, “Four-quadrant CMOS current-mode multiplier independent of device parameters,” IEEE Trans. Circuits Sytst. II, Analog Digit. Signal Process., vol.47, no.5, pp.437–477, May 2000. [11] A.K. Wong, S.H. Lee, and M.G. Wong, “Current combiner enhances active mixer performance,” Microwave and RF, pp.156–165, March 1994. [12] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. Solid-State Circuits, vol.31, no.3, pp.331–343, March 1996. [13] A. Hajimiri and T.H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol.34, no.5, pp.717–724, May 1999.. Wen-Chieh Wang was born in 1978. He received the B.S. from the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, in 2000. He is currently working toward the Ph.D. degree in the Institute of Electronics, National Chiao-Tung University, Hsihchu, Taiwan, and he is also with MStar Semiconductor, Inc., Taiwan. His current research interests are in CMOS low-voltage low-power radio-frequency integrated circuits design and analog integrated circuits design.. Chung-Yu Wu was born in 1950. He received the M.S. and Ph.D. degrees from the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1976 and 1980, respectively. In addition, he conducted post-doc research at UC Berkeley in summer of 2002. Since 1980, he has served as a consultant to high-tech industry and research organizations and has built up strong research collaborations with high-tech industries. From 1980 to 1983, he was an Associate Professor at National Chiao Tung University. During 1984 to 1986, he was a Visiting Associate Professor in the Department of Electrical Engineering, Portland State University, Portland, OR. Since 1987, he has been a Professor at National Chiao Tung University. From 1991 to 1995, he was rotated to serve as the Director of the Division of Engineering and Applied Science on the National Science Council, Taiwan. From 1996–1998, he was honored as the Centennial Honorary Chair Professor at National Chiao Tung University. Currently, he is the president and chair professor of National Chiao Tung University. He has published more than 250 technical papers in international journals and conferences. He also has 19 patents including nine U.S. patents. His research interests are nanoelectronics, lowpower/low-voltage mixed-signal VLSI design, biochips, neural vision sensors, RF circuits, and CAD analysis. Dr. Wu is a member of Eta Kappa Nu and Phi Tau Phi Honorary Scholastic Societies. He was a recipient of IEEE Fellow Award in 1998 and Third Millennium Medal in 2000. In Taiwan, he received numerous research awards from Ministry of Education, National Science Council, and professional foundations..

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