thermal noise model is developed. Short-channel effects (SCEs), substrate potential fluctuation effect, and parasitic-resistance-induced excess noises were implemented in analytical formulas to accurately simulate RF noises in sub-100-nm MOSFETs. The intrinsic noise extracted through a previ-ously developed lossy substrate de-embedding method and calculated by the improved noise model can consistently predict gate length scaling ef-fects. For 65- and 80-nm n-channel MOS with fT above 160 and 100 GHz,
NFminat 10 GHz can be suppressed to 0.5 and 0.7 dB, respectively. Drain current noise Sid reveals an apparently larger value for 65-nm devices than that for 80-nm devices due to SCE. On the other hand, the shorter channel helps reduce the gate current noise Sig attributed to smaller gate capacitances. Gate resistance Rg-induced excess noise dominates in Signear one order higher than the intrinsic gate noise that is free from Rg for 65-nm devices. The compact RF CMOS modeling can facilitate
high-frequency noise simulation accuracy in nanoscale RF CMOS circuits for low-noise design.
Index Terms—Lossy substrate de-embedding, radio frequency (RF) complementary metal–oxide–semiconductor (CMOS) model, short-channel effect (SCE), thermal noise model.
I. INTRODUCTION
The advancement of CMOS device technology to the sub-100-nm regime has driven a remarkable increase in cutoff frequency (fT) and maximum oscillation frequency (fmax) to well above 100 GHz and
has made RF CMOS a vital technology enabling communication SoC [1]–[3]. The decrease in noise with device scaling is desirable for low-noise RF circuit design. However, an accurate low-noise extraction and modeling emerges as a challenging subject for miniaturized devices. For the first time, a lossy substrate de-embedding method was devel-oped to successfully extract the intrinsic noise parameters in 80- and 65-nm devices for exploring the aggressive gate length scaling effect on RF noise [4], [5].
Regarding short-channel effect (SCE) on channel thermal noise, there has been much controversy in the last two decades [6]–[11]. It was reported that the channel thermal noise model implemented in the Berkeley Short-channel IGFET Model 3 (BSIM3, an industry standard model) generally underestimates drain current noise (Sid) and cannot
accurately simulate the noise parameters [12]. Our study suggests that hot carrier effect plays a minor role, and the classical noise model remains valid, provided that SCEs such as mobility degradation, velocity saturation, carrier heating, drain-induced barrier lowering
Manuscript received August 13, 2007; revised March 3, 2008. Published August 20, 2008 (projected). This work was supported in part by the National Science Council under Grant NSC 95-2221-E009-289 and Grant NSC 96-2221-E009-186. This paper was recommended by Associate Editor L. M. Silveira.
The authors are with the Institute of Electronics Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan, R.O.C. (e-mail: jcguo@mail. nctu.edu.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCAD.2008.927736
Rn, Yopt) can be derived from the noise power corresponding to the
simulated current noises and source impedance [13]. This enhanced noise model in the explicit form can easily be deployed in high-frequency circuit simulators such as Agilent ADS and can realize a compact RF CMOS model for dc, ac, and RF noise simulation over tens of gigahertz. The comparison between the improved noise model, BSIM3 noise model, and measurement reveals that BSIM3 underestimates NFmin and Sid in magnitude and frequency
depen-dence for miniaturized MOSFETs down to 65 nm. The improved noise model can fix the problem and demonstrate promising accuracy in sub-100-nm devices over wide frequencies and bias conditions.
II. RF DEVICETESTSTRUCTURE AND LOSSYSUBSTRATEMODEL
MOSFETs measuring 65 and 80 nm were fabricated to investigate gate length (Lgate) scaling effect on speed and noise. Multifinger
structures with the finger width fixed at 4 µm and various finger numbers NF = 6, 18, 36, and 72 were employed to reduce Rg and the induced excess noises. The noise parameters were measured by an ATN-NP5B system to 18 GHz for fixed Vgsat maximum gmor min-imum NFmin. Based on the noise correlation matrix method [14] and
equivalent circuit analysis for a two-port noisy network, the measured NFmin, Rn, and Yoptcan be used to derive Sidand Sig. The details
of device characterization and modeling flow involving measurement, parameter extraction, optimization, and model calibration can be found in our original work [4], [15].
Fig. 1 illustrates an RF device test structure composed of a device under test (DUT), ground–signal–ground (GSG) pad, and transmission line (TML) in 3-D topology, and the equivalent circuits representing lossy substrate networks underneath the pad and TML. Open and through-pad S-parameters were measured for lossy substrate model parameter extraction. The physical properties of substrate RLC param-eters have been defined in [15]. Then, the lossy substrate model was integrated with intrinsic MOSFET as a full equivalent circuit in Fig. 2 for extrinsic noise simulation and intrinsic noise extraction. Note that TML in a standard open pad is composed of M8 through M7–M4 and terminated at M3. The parasitic capacitances contributed from M3–M1 cannot be removed by the conventional open de-embedding. This kind of extrinsic gate capacitance is nonscalable with device dimension and may impose a significant influence on miniaturized devices in high-frequency performance.
III. INTRINSICMOSFET MODELING A. BSIM3I–V Model Calibration
An extensive calibration was done on the BSIM3 I–V model for sub-100-nm MOSFETs. The important corrections involve SCE in threshold voltage (VT), velocity saturation, CLM, and DIBL effects
Fig. 1. RF device test structure composed of DUT, GSG pad, and TML in 3-D topology and the equivalent circuits representing lossy substrate networks underneath the pad and TML.
Fig. 2. Full circuit schematics with substrate RLC network integrated with intrinsic MOSFET.
in saturation I–V , as well as DIBL and drain-to-source coupling capacitance effects in subthreshold I–V [16]. As a result, the I–V model with SCE parameters properly specified can accurately simulate Id–Vgs, Id–Vds, and transconductance (gm), as well as output conduc-tance (gds) for 80- and 65-nm n-channel MOS (nMOS) with various
NF’s [5]. The refined I–V model can predict gm enhancement by about 20%–30% for 65-nm devices compared to that for the 80-nm devices, which is attributed to the Lgate reduction by 20%.
The accurate simulation of gm is essential to predict Re(Y21)
and fT.
B. BSIM3C–V Model Calibration
C–V model calibration was done by incorporating extrinsic gate capacitances and appropriate threshold voltage tuning Voff,CV. The
impact from the nonscalable extrinsic capacitances increases in minia-turized devices with shorter Lgate and smaller NF. For the smallest device with Lgate= 65 nm and NF = 6, the extrinsic capacitances contribute about 30% of the total capacitance. The calibrated C–V model can accurately simulate C–V characteristics for various NF’s, as well as Lgate, and over a wide range of Vgsfrom weak-to-strong
inversion [5]. For Lgate scaling from 80 to 65 nm, Cgg is reduced
by about 16%–20%, corresponding to NF = 6−72, whereas Cgd is
reduced by only 7%–14%. The weaker dependence on Lgaterevealed
by Cgdsuggests drain depletion effect under saturation [5].
I–V and C–V models with the proven accuracy for sub-100-nm devices can validate high-frequency simulation for the prediction of key performance parameters such as fT and fmax, and NFmin.
Fig. 3 presents fT over a wide range of Id, in which fT is extracted corresponding to|H21| = 1. A good match between simulation and
measurement is demonstrated for all NF’s. The maximum fTrealized
Fig. 3. Comparison of measured and simulated fT versus Id(Vds= 1 V)
for 80- and 65-nm RF n-channel MOSFETs (nMOSFETs). (a) NF= 6.
(b) NF= 18. (c) NF = 36. (d) NF = 72. (Solid line) Calibrated model.
(Dashed line) CV model without Cgg,ext, Cgd,ext, and Cgs,ext.
by 65-nm nMOS is about 160 GHz. It exhibits 50%–60% improvement over its 80-nm counterpart with maximum fT at 100–110 GHz. The
fTenhancement factor matches well with the prediction calculated by an analytical expression of fT= gm/2π
(C2
gg− Cgd2 ), in which the
increase in gmby 20%–30% and reduction in Cggby 16%–20% can
improve fT by nearly 60% due to Lgate scaling from 80 to 65 nm.
Note that neglecting extrinsic gate capacitances will overestimate fT, as denoted by dashed lines in Fig. 3. The overestimation be-comes significant in miniaturized devices with smaller NF and shorter Lgate.
IV. IMPROVEDTHERMALNOISEMODEL FOR SUB-100-nm RF CMOS
The advantage provided by Lgatescaling on RF performance, such
as fT(gm, Cgg), calls for an interest to investigate its effect on
high-frequency noises. We reported interesting but abnormal features in NFminmeasured from sub-100-nm devices, such as weak dependence
on Lgate, strong dependence on NF, and nonlinear frequency depen-dence [5]. All three observations cannot be explained by thermal noise theory and intrinsic device performance. We proposed that substantial excess noises were generated from the lossy substrate and led to a dramatic impact on miniaturized devices in RF noises. In this paper, an improved thermal noise model is proposed to work with the proven lossy substrate model for accurate RF noise simulation in sub-100-nm devices.
In the following, an improved thermal noise model is implemented to replace the default noise model in BSIM3. The major features in-corporated in this improved noise model are SCE (velocity saturation, CLM, and carrier heating) and substrate-resistance-induced potential fluctuation effect in drain current noise, and gate-resistance-induced excess noises in both drain and gate current noises.
The model equations are formulated in (1)–(7) for drain current noise Sidand (8)–(11) for gate current noise Sig. To calculate drain
current noise Sid, SCEs such as the velocity saturation that originated
from lateral field-induced mobility degradation, carrier heating, CLM effect [10], [11], and nonuniform channel effect on VT, as well as body coefficient (α), have been implemented in (2)–(4). The frequency dependence generally revealed in the measured Sid and Rn with higher value at lower frequency is modeled by an excess noise Sid,sub
in (6), which is caused by the substrate potential variation associated with substrate resistance and capacitances (Rbulk, Cbulk) [17]. As
where Sιd0= 4kBT· gdo· 1− u + u2/3 1− u/2 (2) gdo= µeffW CoxVGT Leff (3) u = αVds VGT , VGT= Vgs− VT (4) ∆Sιd= Sιd,sub+ Sιd,Rg (5) Sιd,sub= 4kBT· Rbulkgmb 1 + (ωRbulkCbulk)2 (6) Sιd,Rg = 4kBT· Rg|Y21| 2 (7) where
α body effect coefficient; ιnd noise current at drain;
Sιd power spectral density of drain current noise;
Sιd,sub excess drain current noise caused by substrate-resistance-induced potential fluctuation;
Sιd,Rg excess drain current noise caused by the gate resistance. Gate current noise spectral density Sigis calculated by [9]
Sιg= |ιng|2 ∆f = Sιg0+ ∆Sιg (8) where Sιg0= 4kBT· β|lm(Y11) + lm(Y12)|2 5gdo (9) ∆Sιg= Sιg,Rg = 4kBT· Rg|lm(Y11)|2 (10)
and Sιg,Rg is the excess gate current noise caused by the gate resistance.
For short-channel devices with sub-100-nm gate lengths
Sιg0 Sιg,Rg∼= Sιg (11) where
ιng noise current at the gate;
Sιg power spectral density of the gate current noise.
V. NOISESIMULATIONRESULT ANDDISCUSSION A. Extrinsic Noise Simulation—Current Noises and Noise Parameters
The improved thermal noise model was implemented in intrinsic MOSFETs and integrated with the proven lossy substrate model for extrinsic noise simulation. Fig. 4 compare the measured and simulated Sid and Sig over frequencies of up to 18 GHz. As shown in Fig. 4(a) and (b), the improved noise model can consistently predict Sid for
Fig. 4. Measured and simulated Sid and Sig for 65- and 80-nm nMOSFETs of various NF’s. Vds= 1.0 V. The gate bias is fixed at maximum gm, and the
frequency is swept from 1 to 18 GHz. (a) 65-nm Sid. (b) 80-nm Sid. (c) 65-nm
Sig. (d) 80-nm Sig. (Solid line) Improved noise model. (Dashed line) BSIM3 noise model.
Fig. 5. Measured and simulated NFminversus frequency (1–18 GHz) for
65- and 80-nm nMOSFETs. (a) NF = 6. (b) NF = 18. (c) NF = 36.
(d) NF = 72. The bias conditions are at Vds= 1.0 V and Vgsat maximum
gm. (Solid line) Improved noise model. (Dashed line) BSIM3 noise model.
BSIM3 simulation reveals an underestimation in NFmin, with an apparently
worse deviation for 65-nm devices.
65- and 80-nm nMOS, in which the SCE was presented with higher Sid in 65-nm devices. The frequency dependence of Sid with an increase at sufficiently low frequencies can be simulated by the introduced excess noise Sid,sub in (6) due to substrate potential variation. Note
that conventional models commonly assume that Sid is a pure white
noise independent of frequency. However, the measured Sid generally
reveals apparent frequency dependence. For comparison, the BSIM3 noise model appears to underestimate Sidfor 65-nm devices and fails to predict the frequency dependence. This result suggests that the SCE was not appropriately implemented in the BSIM3 noise model with a simple equation given by Sid= 4kBT µeffQinv/L2[10]–[12].
As for extrinsic Sig in Fig. 4(c) and (d), the frequency dependence deviates much from the theory of being proportional to ω2, and the
NF dependence is abnormally weak, both due to the lossy-substrate-introduced excess noises.
Fig. 5 presents the simulated NFminover frequencies to 18 GHz and
the comparison with the measurement. The improved noise model can predict the extrinsic NFminfor 65- and 80-nm devices with various
Fig. 6. Extracted intrinsic NFmin for 80- and 65-nm nMOSFETs under
varying frequencies (1–18 GHz). Vds= 1.0 V, and Vgsis at maximum gm
(0.7/0.6 V for 80/65-nm devices) and minimum NFmin (0.55/0.35 V for
80/65-nm devices). (a) NF = 6. (b) NF= 18. (c) NF= 36. (d) NF= 72.
(Line) Fukui’s formulas. (Star) Noise de-embedding by the noise correlation matrix method.
65-nm devices. The excellent match with measured noises in depen-dence of Lgate, NF, and frequency proves the solution realized by the improved thermal noise mode working with the lossy substrate model for extrinsic noise simulation.
B. Intrinsic Noise Parameters—Frequency Dependence and Comparison With Noise Correlation Matrix De-Embedding
The lossy substrate model and intrinsic MOSFET model proven over varying frequencies and device dimensions enable an accurate lossy substrate de-embedding for intrinsic noise extraction. The lossy substrate de-embedding can precisely be done by removing all ele-ments of the pad and substrate RLC networks from the full equivalent circuit in [15]. The parasitic resistances (Rg, Rs, Rd, and Rbulk) that
remained with the intrinsic MOSFET act as important elements that are responsible for the excess noises even after de-embedding. Fig. 6 shows the intrinsic NFminextracted for 65- and 80-nm nMOS under
Vgsat maximum gmand minimum NFmin, respectively. The accuracy
of the extracted intrinsic noise is justified by a good match with the Fukui formula Fmin= 1 + k∗f /fT[gm(Rg+ Rs)]1/2 [18] for those under Vgsat minimum NFmin. Apparently, the 65-nm devices
demonstrate lower NFminthan their 80-nm counterparts with the same
NF. The suppression of NFminby about 0.2 dB at 10 GHz suggests
the contribution from fT enhancement by nearly 60% due to Lgate
scaling and the advantage offered by continuous scaling to the deep sub-100-nm regime. Note that the noise de-embedding by using the noise correlation matrix method [14] was simultaneously performed for a comparison. The results shown by the star sign in Fig. 6 reveal a dramatic fluctuation over frequency. It is a common problem presented in many publications, and a smoothing was reported to get a reasonable frequency dependence [19].
C. Extrinsic and Intrinsic Current Noise—Lossy Substrate De-Embedding and Noise Model Comparison
Fig. 7 presents intrinsic current noises Sidand Sigextracted through
lossy substrate de-embedding and the comparison with extrinsic ones such as Sid and Sig. For Sid compared to Sid shown in Fig. 7(a)
and (b), the increase in lower frequency while suppression to near constant at higher frequency can be explained by the de-embedding effect on|Y21|2, which is a major parameter determining Sid. At lower
Fig. 7. Comparison between the extrinsic (Sid and Sig ) and intrinsic (Sidand
Sig) current noises, which were simulated by full circuit and intrinsic models
for 65-nm nMOSFETs. (a) Sid and Sid for NF = 6. (b) Sid and Sid for
NF = 18. (c) Sig and Sigfor NF = 6. (d) Sig and Sigfor NF= 18. A good
match between the full circuit simulation (lines) and measurement (symbols) was demonstrated.
Fig. 8. Comparison of intrinsic Sid and Sig between 65- and 80-nm
nMOSFETs to show SCE. NF = 6. (a) Sid. (b) Sig. Vds= 1.0 V. Vgsis
at maximum gmand frequency in the range of 1–18 GHz.
frequency, |Y21|2 is dominated by |Re(Y21)|2, which may increase
after de-embedding. As for higher frequency, |Im(Y21)|2 may take
over the influence on Sidfor larger NFbefore de-embedding, whereas the substantial decrease in|Im(Y21)|2 after de-embedding will
sup-press Sid to near constant. Note that the intrinsic Sid simulated by
the BSIM3 noise model was put together for comparison. The results indicate much lower noises and diminishing frequency dependence. It supports previous comments that the BSIM3 noise model is not valid for noise simulation in miniaturized devices with significant SCE. As for Sig and Sig shown in Fig. 7(c) and (d), the lossy substrate
de-embedding can reduce the gate current noise by orders of magnitude and recover the frequency dependence to follow the ideal theory of being proportional to ω2. The results prove an effective de-embedding
of parasitic capacitances at the input represented by Im(Y11) and
Im(Y12) in (9).
D. Intrinsic Current NoisesSidandSig—SCE
Fig. 8(a) and (b) presents intrinsic Sid for 65- and 80-nm devices
to investigate SCE. The obviously larger Sid for 65-nm devices,
compared to that for 80-nm devices, accounts for the major effect from larger gdodue to shorter effective length Leff. The excess noise that
originated from Rg given by Sid,Rg in (7) also increases with Leff
scaling due to the larger|Y21|2. The frequency-dependent excess noise
Sid,subgiven by (6) can consistently simulate the interesting
behav-ior, which is different from the general assumption of white noise. Again, the BSIM3 noise model underestimates Sidand its frequency
Fig. 10. Simulated intrinsic Sid for 65-nm nMOSFETs with various bulk
resistance Rbulk, with optimized values of 1000, 400, and 10 Ω. (a) NF = 6.
(b) NF = 18. Vds= 1.0 V. Vgsis fixed at maximum gmand frequency in the
range of 1–18 GHz.
shown in Fig. 8(c) and (d), the obviously smaller Sigfor 65-nm devices
than that for 80-nm devices accounts for the smaller gate capacitances Cgg and Cgs represented by Im(Y11) and Im(Y11) + Im(Y12),
re-spectively, for intrinsic devices after de-embedding. The decrease in Sigwhile Sidis increasing with Lgatescaling results in the absolute
dominance of Sidover Sigin nanoscale devices. For 80-nm devices,
Sid remains higher than Sigby more than one order. As for 65-nm
devices, the ratio keeps going up to more than two orders.
E. Excess Noises inSidandSig− RgandRbulkEffect
Gate-resistance-induced excess noise was simulated by (7) and (10) for Sidand Sig, respectively. Fig. 9 presents the simulation for
65-nm devices with and without Rg for comparison. In practical devices, Rgcannot be eliminated to zero. Assuming an ideal condition in simulation without Rg, the intrinsic Sidcan be reduced by about
13%–17% over 18 GHz. The suppression of Sigdue to the removal
of Rg is even larger to near one order. Note that variation in Rg causes a near-parallel shift in Sid and Sig over frequency, i.e., no
influence on frequency dependence. Regarding one more excess noise in Sidthat originated from the substrate potential fluctuation calculated
by (6), noise simulation was done to investigate the Rbulk effect.
Fig. 10 indicates an interesting result in that the larger Rbulk leads
to a significant increase in Sid in lower frequency but has nearly no
influence in higher frequency (> 10 GHz). Sufficiently low Rbulkcan
suppress the frequency dependence and may approach a white noise, which is independent of frequency.
VI. CONCLUSION
A compact RF CMOS model has been developed for accurate RF noise simulation in sub-100-nm MOSFETs. An improved thermal noise model was implemented in explicit form, incorporating SCE, substrate potential variation, and resistance-induced excess noises. The accuracy has been proven by a good match with measurement in fT(gm, Cgg, Cgd), noise parameters, and current noises over
fre-quencies. The improved thermal noise model can solve problems in
The authors would like to thank NDL for the RF device measure-ment and CiC for the RF simulation environmeasure-ment.
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