including the p-type, the n-type, and the two-way CFMV structures. The CFMV structures make use of multiple supply voltages and do not require level converters. In contrast, previous works employing multiple supply voltages need level converters to prevent static currents, which may result in large power consumption. In addition, the CFMV structures group the gates with the same supply voltage in a cluster to reduce the complexity of placement and routing for the subsequent physical layout stage. Next, we formulated the problem and proposed an efficient heuristic algorithm to solve it. The heuristic algorithm has been implemented in C and exper-iments were performed on the ISCAS85 circuits to demonstrate the effec-tiveness of our approach.
Index Terms—CFMV, clustered voltage scaling, converter-free, CVS, low-power, multiple-voltage, voltage scaling.
I. INTRODUCTION
A. Background and Related Work
Power dissipation has become one of the most significant parameters in very large scale integration design due to the trend toward portable computing and communications systems. For portable devices, power dissipation limits the battery life and the available time. Even for non-portable devices, power dissipation affects the cost of packaging and cooling equipment.
Total power dissipation in a digital CMOS circuit can be obtained from the sum of three components: static dissipation, dynamic dis-sipation, and short-circuit dissipation [1]. In general, the total power dissipation is dominated by the dynamic dissipation and may be esti-mated byPd = a 1 fclk1 CL 1 VDD2 , wherea is the activity factor,
fclkthe switching frequency,CLthe total node capacitance, andVDD the supply voltage. This formula is the basis of previous researches in low-power CMOS digital design [2]–[11].
As the dynamic power dissipation is proportional to the square of the supply voltage, voltage scaling is evidently the most effective technique to minimize the power dissipation. Moreover, the conclusion of [8] provides us a clear goal in minimizing the power dissipation, i.e., op-erate the circuits as slowly as possible, with the lowest possible supply voltage.
The most popular voltage scaling technique is to operate all the gates in a circuit with a reduced supply voltage, which is limited by the crit-ical paths. However, the gates that are not on the critcrit-ical paths could operate slower with lower supply voltages. This motivated some re-searchers to operate gates with two or more supply voltages in a circuit [10]–[12].
Manuscript received September 17, 1998; revised July 10, 2000. This work was supported by the National Science Council, Taiwan, R.O.C., under Grant NSC 89-2219-E-002-003. This paper was recommened by Associate Editor M. Redram.
Y.-J. Yeh and S.-Y. Kuo are with the Department of Electrical En-gineering, National Taiwan University, Taipei Taiwan, R.O.C. (e-mail: yeh@lion.ee.ntu.edu.tw; sykou@cc.ee.ntu.edu.tw).
J.-Y. Jou is with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu Taiwan, R.O.C. (e-mail: jyjou@bestmap.ee.nctu.edu.tw).
Publisher Item Identifier S 0278-0070(01)00362-1.
Fig. 1. Block diagram of the CVS structure.
Usami et al. proposed a clustered voltage scaling (CVS) technique to reduce the power consumption with two supply voltages [11]. The block diagram of CVS is shown in Fig. 1. They arranged supply volt-ages such that the voltage swings of all paths are in decreasing order. Then level converters and latches with the level-conversion function are inserted before the primary outputs to prevent the static current. B. Motivation and Goals
In previous works, level converters and latches with the level-con-version function were inserted to prevent the static current in circuits with multiple supply voltages. However, there exist some overheads with level converters.
First, the power consumption of level converters is not negligible. From our circuit simulation, the power consumption of a level con-verter is about four times that of an incon-verter. Next, the insertion of level converters introduces extra delays into the circuits. The rising delay of a level converter is about four times that of an inverter, too. Finally, the insertion of level converters changes the topology of circuits.
Consequently, Usami et al. used level converters with care and just inserted level converters in front of the primary outputs to minimize the number of level converters [11]. Instead of using level converters with care, we try to find a voltage scaling technique without level converters in this paper.
To reduce the complexity of placement and routing when multiple supply voltages are used in physical layout, gates with the same supply voltage should be placed in a cluster. This is especially important for a standard-cell design since the gates in a standard-cell design are ar-ranged in rows and their power lines are connected directly. Hence, we would like to preserve the clustering property in this paper as Usami et al. did in the CVS technique.
Finally, the logic structure discussed in this paper is CMOS com-plementary logic. Other logic structures may have more sophisticated effects at the interface of different supply voltages, which is beyond the scope of this paper.
The rest of this paper is organized as follows. In Section II, we propose the converter-free multiple-voltage (CFMV) structures, which need no level converters, make use of multiple voltages, and have gates with the same supply voltage in a cluster. In Section III, we give some definitions, formulate our problem, and propose a heuristic algorithm for the problem. Then, experimental results are shown in Section IV and are compared to the results of previous work. Finally, concluding remarks and future works are provided in Section V.
II. CFMV STRUCTURES
A. Elimination of Level Converters
When multiple supply voltages are applied in a CMOS digital circuit, there might exist a static current flowing from the supply voltage to the 0278–0070/01$10.00 © 2001 IEEE
Fig. 2. (a) Inverter with VDDR drives another inverter with VDD. (b) Static currents of various reduced supply voltages withjV j = 0:9 V, V = 0:75 V, andV = 5 V.
ground at the interface of gates with different supply voltages. Level converters are usually used at the interface to prevent the static current. To avoid using level converters in a CMOS circuit with multiple supply voltages, we put constraints on the voltage differences between adja-cent gates with different supply voltages.
A simple analysis with the first-order MOS model predicts that there will be no static current if the supply voltage of a driver gate is higher than the subtraction of the threshold voltage of a PMOS from the supply voltage of a driven gate. Take Fig. 2(a) as an example where a CMOS inverter INV1 with the reduced supply voltageVDDR is connected directly to another CMOS inverter INV2 with the unreduced supply voltageVDD. Then, the output voltage of INV1 will beVDDR, which is also the input voltage of INV2. IfVDDR> VDD0 jVtpj, i.e., VSG of the PMOS in INV2 is less thanjVtpj, the PMOS in INV2 will beOFF and there will be no static current flowing from the supply voltage to the ground through INV2.
However, the subthreshold effect makes the above prediction impre-cise [13]. As we can see from Fig. 2(b), whenVDDR equals 4.1 V (VDD0 jVtpj), the static current is about 31.4 A,1which seems large and unacceptable. Therefore, the best way to determine the reduced voltage is by a circuit simulator, such as HSPICE, when the acceptable value of the static current is given. For example, we could use HSPICE to simulate the circuit in Fig. 2(a). If the acceptable value of the static current is 1A, we can determine VDDRto be 4.4 V with which the static current will be less than 1A.
B. Arrangement of Supply Voltages
From the above section, we know that if the voltage difference of a driven gate and its driver gate is less than a specific value, level con-verters are not necessary at the interface of gates with different supply voltages. We call such value a safe threshold voltage, denoted asVst. Next, we’ll discuss how to arrange multiple supply voltages in a circuit to eliminate level converters.
Assume that we have a set of n supply voltages,
fV dd0; V dd1; . . . ; V ddn01g, such that 1) V dd0 > V dd1 > 1 1 1 > V ddn01,
2) V ddi0 V ddi+1< Vstfori = 0; 1; . . . ; (n 0 2), 3) V ddi0 V ddj > Vstfori 0 j > 1.
Also, we have a set ofn clusters of gates fC0; C1; . . . Cn01g, where the gates in different clusters are supplied with different voltages and each cluster has two adjacent clusters at most. If we like to assign these supply voltages to the clusters such that there is no static current and no level converters, the only solution will be as shown in Fig. 3.
We call the structure shown in Fig. 3 a p-type CFMV structure if all clusters have the sameVss. Similarly, if all clusters have the same
Vdd and V ss0; V ss1; . . . ; V ssn01 are in increasing order, we call 1All the circuit simulations of this paper used the level-3 SPICE models of the TSMC 0.8-m single-poly double-metal process.
Fig. 3. Block diagram of the CFMV structure.
it an n-type CFMV structure. If bothVdd andVss are scalable, it is called a two-way CFMV structure. Whichever CFMV structure is used, the voltage swings along all paths are in increasing order. The set of supply voltagesf(Vdd0; Vss0); (Vdd1; Vss1); . . .g is called the fea-sible supply voltage set.
III. ALGORITHMS FOR THECFMV STRUCTURES
A. Preliminaries
A combinational circuit can be represented as a directed acyclic graphG = (V; E) consisting of two sets: a finite set V of elements called vertices and a finite setE of elements called edges. Each vertex
v 2 V is in one-to-one correspondence with a gate in the circuit and
is associated with a delayd(v), which is the delay of the gate. There is an edge denoted by an ordered pair(u; v) 2 E if the output of gate
u 2 V is connected to an input pin of gate v 2 V .
Definition 1 (Fan-Out Set): For any vertexv 2 V , the fan-out set 0+(v) = fwj(v; w) 2 Eg.
Definition 2 (Stable Time): The time when the output of vertexu becomes stable is called the stable time of vertexu, denoted as Ts(u). Definition 3 (Required Time): The required time of vertexu, de-noted asTr(u), is the latest time when the output of vertex u has to be stable to meet the timing constraint of the circuit.
Definition 4 (Slack): The slack of vertexu, denoted as s(u), is the maximal delay increase which vertexu may have under the timing con-straint. When the stable time and the required time of vertexu are com-puted, the slack of vertexu can be obtained by s(u) = Tr(u) 0 Ts(u). Definition 5 (Depth): Similar to the definition of level in [14], we can define the depth of a vertexu in a graph G to be the number of edges in the longest path fromu to a sink of G. The depth of a sink is defined to be zero and the depth ofu, denoted as dep(u), can be determined bydep(u) = 1 + maxv20 (u)dep(v). In addition, the depth of a graphG = (V; E) is defined by maxv2V dep(v).
Definition 6 (Reachable): If there is a pathp from u to v, we say thatv is reachable from u via p and is denoted by upv.
Definition 7 (Reachable Set): For any vertexv 2 V , the reachable set ofv is
R(v) = wj there exists a path p such that vpw : Definition 8 (Cut): LetV1andV2be two mutually disjoint subsets ofV such that V = V1[ V2; i.e.,V1andV2have no common vertices and together contain all the vertices ofV . Then the set of all those edges ofG having one end vertex in V1and the other inV2is called a cut of
G. This is denoted as hV1; V2i. The removal of hV1; V2i partitions G into two graphsG1andG2, which are the induced subgraphs ofG on the vertex setsV1 andV2.
Definition 9 (Directed Cut): A cut hV1; V2i whose edges are all fromV1toV2is called a directed cut, which is denoted by[V1; V2].
Definition 10 (Boundary Vertex): Let[V1; V2] be a directed cut of
Fig. 4. Algorithm for two supply voltages.
vertexv 2 V1is called a boundary vertex ofG1if there exists a vertex
u 2 V2such that(v; u) 2 [V1; V2].
Next, we present a lemma before the definition of proper-directed cut.
Lemma 1: Let[V1; V2] be a directed cut of G and v be a vertex in
V2. Then,R(v) V2.
From Lemma 1, we know that if a vertex is inV2, then all the vertices in its reachable set must be included inV2as well. Now we can define the proper-directed cut, which will be used to partition graphs in the following subsections.
Definition 11 (Proper-Directed Cut): [V1; V2] is called a proper-directed cut ofG if V2 contains all the sinks ofG, all the boundary vertices ofG, and all the vertices in their reachable set. pdc(G) denotes a set consisting of all the proper-directed cuts ofG. Take Fig. 7 as an example, where C1 is a proper-directed cut but C2 is not because the vertexd is a sink but not in the right hand side of C2.
B. Problem Formulation
Now we can formulate the problem that we would like to solve in this paper as the following. Given a circuit with timing constraints and a feasible supply voltage set, scale the supply voltages of a subset of gates with positive slacks to minimize the total power consumption for the CFMV structure.
Note that the formulated problem is for the CFMV structure and then has a much smaller solution space than a generic multiple-voltage scaling problem since the voltage sequence in the CFMV structure is a continuous subsequence of the feasible supply voltage set.
When there are only two elements in the given feasible supply voltage set, the optimal solution can be easily obtained by a depth-first search algorithm shown in Fig. 4. However, when there are more than two elements in the given feasible supply voltage set, the problem becomes much more difficult. Thus we next give an asymptotic bound on the solution space of the formulated problem.
Theorem 1: Assume that a graphG = (V; E) is partitioned into n clusters as shown in Fig. 5 as a solution of the formulated problem. Let
7i = n01k=i Vk,Gibe the induced subgraph ofG on 7i, andCibe the cut between7i+1andVi. Then,Ciis a proper directed cut ofGi, fori = 0; 1; . . . ; (n 0 2).
Theorem 2: The number of elements inpdc(G) is (2n=(p+1)), wheren is the number of vertices in the graph G and p is the depth of G. C. Heuristic Algorithm
Since the number of proper-directed cuts of a graph is exponentially proportional to its number of vertices, it is impractical to search all the
heuristic algorithm to search only a subset of the solution space. LetG0be the induced subgraph ofG on the vertices whose voltage level ism. After DFS(m) is applied, G0 is partitioned by a proper-directed cut[V1; V2], where the voltage level of the vertices in V1 is (m + 1) and in V2ism. Next, we give some theorems from which our heuristic algorithm is derived from.
Theorem 3: Let[V10; V20] be a proper-directed cut of G0andV10
V1, where[V1; V2] is obtained from DFS(m). Then, there must exist a negative slack ifG0is partitioned by[V10; V20].
Theorem 4: Let[V10; V20] be a proper-directed cut of G0andV10
V3, where[V3; V4] is a proper-directed cut such that there is no nega-tive slack. Then, there is no neganega-tive slack whenG0 is partitioned by
[V0 1; V20].
Theorem 5: Let[V3; V4] be a proper-directed cut of G0such that there is no negative slack andS = fvj0+(v) V4; 8 v 2 V3g. Then, the cuthV30 S; V4[ Si is a proper-directed cut of G0such that there is no negative slack.
Theorem 3 shows thatDFS() can give us a bound of feasible solu-tions. Theorem 4 shows how to find other feasible solutions when a feasible solution is given. Though the solution space can be narrowed down byDFS(), the remaining solution space is still exponentially pro-portional to the number of the remaining vertices. Hence, we use The-orem 5, which is implemented asFwd 0 One 0 Layer() in this paper, to search for potential solutions with a practical complexity.
Based on Theorems 3–5, we propose a heuristic algorithmCFMV(), shown in Fig. 6, to solve the formulated problem. Givenn elements in the feasible supply voltage set, we first initialize the voltage level of each vertex to zero, and then applyCFMV(n 0 1; 0) to a graph G =
(V; E). By way of illustration, let’s take a look at how CFMV(2; 0)
works.
Initially, the voltage level of each vertex is zero, ML = and
MP = 1. Then, CFMV(2; 0) calls DFS(0) to assign the voltage
levels offj; k; . . . ; rg to one. Next, CFMV(0; 0) is called such that
L1 = f(a; 0); (b; 0); . . . ; (i; 0)g and P 1 = 9:00. Then, CFMV(2; 1)
is called and it callsDFS(1). Since there is no positive slack, DFS(1) does not update the voltage level of any vertex. When CFMV(2; 1) returns, L2 = f(j; 1); (k; 1); . . . ; (r; 1)g and P 2 = 5:76. Since(P 1 + P 2 = 14:76) < (MP = 1), MP = 14:76 and
ML = f(a; 0); . . . ; (i; 0); (j; 1); . . . ; (r; 1)g.
Next, Fwd 0 One 0 Layer(0) is called to assign the voltage levels of fj; k; lg to zero. Then CFMV(0; 0) is called again such that L1 = f(a; 0); (b; 0); . . . ; (l; 0)g and P 1 = 12:00. Next, CFMV(2; 1) is called and it calls DFS(1), which assigns the voltage levels of fp; q; rg to two. The ML of CFMV(2; 1) is then f(m; 1); (n; 1); (o; 1); (p; 2); (q; 2); (r; 2)g. Be-fore CFMV(2; 1) returns, the voltage levels of fp; q; rg are assigned back to one. When CFMV(2; 1) returns, L2 =
f(m; 1); (n; 1); (o; 1); (p; 2); (q; 2); (r; 2)g and P 2 = 3:00.
Since(P 1 + P 2 = 15:00) > (MP = 14:76), MP and ML remain unchanged.
Next,Fwd 0 One 0 Layer(0) is called again to assign the voltage levels offm; n; og to zero. Then, CFMV(0; 0) is called such that L1 =
f(a; 0); (b; 0); . . . ; (o; 0)g and P 1 = 15:00. Next, CFMV(2; 1) is
Fig. 6. Heuristic algorithm for the formulated problem.
Fig. 7. Graph for the illustration ofCFMV(2; 0).
Since(P 1 + P 2) > MP , MP and ML remain unchanged. When
Fwd 0 One 0 Layer(0) is called, the voltage levels of fp; q; rg are
assigned zero.
Now the voltage level of each vertex is zero. So, L3 =
f(a; 0); . . . ; (r; 0)g and P 3 = 18:00. Since P 3 > MP , MP and ML remain unchanged. Finally, (MP , ML) is the best
solution found byCFMV(2; 0).
In the following, we give an asymptotic bound on the computation complexity ofCFMV.
Theorem 6: Letn be the number of vertices in the graph G and l be the number of elements in the feasible supply voltage set. Then, the computation complexity ofCFMV on G is O(nl01), for l = 2; 3; . . ..
IV. EXPERIMENTALRESULTS
We have implemented our heuristic algorithm in C on a Pentium II 450 PC running Linux (RedHat 6.0) with 128-MB memory, and per-formed experiments on all the ISCAS85 circuits. In addition, we im-plemented the CVS technique for comparison.
The experiment environment is shown in Fig. 8. The control file pro-vides the feasible supply voltage set. In our experimental cell library, the length of each MOS is 0.8m, the width of each PMOS is 16.8
Fig. 8. Experiment environment.
TABLE I
FEASIBLESUPPLYVOLTAGESETSUSED IN THEEXPERIMENT
m and the width of each NMOS is 8 m. Using HSPICE to simulate
each gate in the cell library, we obtained the parameters for timing and power analysis.
From [1], the rising delayTdLHof a gatev is estimated by
TdLH= (rise a0) + (rise a1) 2 Cout (1) whereCoutis the sum of the output capacitance of gatev and the input capacitances of its fan-outs. The falling delay is estimated similarly. If the supply voltage of a gate is scaled to (Vdd0 ,Vss0), its rising delay is estimated by T0 dLH= TdLH2 V 0 dd0 Vss0 Vdd0 Vss 2 (V dd0 Vss0 Vthp)2 (V0 dd0 Vss0 0 Vthp)2: (2) For the power analysis, the activity factor of each primary input is assumed to be 0.5 and the activity factors of other gates are computed accordingly. Then, the power consumptionPdof a gatev with supply voltages (Vdd0 ,Vss0), can be estimated by
Pd= 122 f 2 2 (Vdd0 0 Vss0 )2: (3) The feasible supply voltage sets used in our experiments are shown in Table I. Whenn voltage levels are used, the feasible supply voltage set is {(Vdd0; Vss0), . . ., (Vdd(n01); Vss(n01))}.
First of all, we compare the results of CFMV with those of CVS to show the effectiveness of the CFMV technique. Since the CVS nique uses two supply voltages, we compare it with the CFMV tech-nique with two voltage levels. The comparison results are shown in Table II. We can find that the CFMV technique is better than the CVS technique in most cases, except in c880 and c5315. On average, the power reduction of CVS (5 V, 4 V) is 7.17%, CVS (5 V, 3 V) is 8.99%, and two-way CFMV (2 levels) is 13.65%.
Next, we perform experiments on three types of CFMV structures with more voltage levels to find the effect of voltage levels as shown in Table III. We find that the more voltage levels are provided, the more power reduction we can obtain. For example, from Table III, the average power reduction of a two-way CFMV with two voltage levels is 13.65%, three voltage levels is 18.05%, and four voltage levels is 18.73%. Though more power reduction can be obtained with more voltage levels, the increment of power reduction is less with more voltage levels. It is a tradeoff between the power reduction and the cost of voltage levels.
TABLE III
EXPERIMENTALRESULTS OFCFMV ALGORITHM WITHTWO, THREE,AND
FOURVOLTAGELEVELS
V. CONCLUSION ANDFUTUREWORK
Voltage scaling with multiple supply voltages is a very challenging problem since the size of its solution space isO(ln), where l is the
portional to the number of gates.
Therefore, we tried to find a practical solution and proposed a heuristic algorithm for the formulated problem. The complexity of our heuristic algorithm is shown to be O(nl01). Furthermore, we implemented the heuristic algorithm in C, performed experiments on all the ISCAS85 circuits, and compared the results with those of the CVS technique. From the experimental results, we can find that the CFMV technique can reduce the power consumption by up to 33.39%. On average, 9–18% power reduction can be obtained using the CFMV technique.
In this paper, we used the maximum voltage difference allowed in the CFMV structures. In future work, we will find what the voltage differences should be to obtain maximum power reduction.
In addition, we used monotonously increasing supply voltages in the CFMV structures to have both the converter-free and the clustering features. If the clustering constraint is released, it is not necessary for the voltage sequences to increase monotonously. In the future, we will also explore the solution of such formulation.
Last but not least, if the converter-free constraint is released, it be-comes the generic problem and has the largest solution space. This is really a challenging research topic.
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