Electrostatic Discharge Protection Design for
Mixed-Voltage CMOS I/O Buffers
Ming-Dou Ker, Senior Member, IEEE, and Chien-Hui Chuang
Abstract—A new electrostatic discharge (ESD) protection cir-cuit, using the stacked-nMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffers of CMOS ICs. The new proposed ESD protection circuit, which combines the stacked-nMOS structure with the gate-coupling circuit technique into the SCR device, is fully compatible to general CMOS processes without causing the gate-oxide reliability problem. Without using the thick gate oxide, the experimental results in a 0.35- m CMOS process have proven that the human-body-model ESD level of the mixed-voltage I/O buffer can be successfully increased from the original 2 kV to
8 kV by using this proposed ESD protection circuit.
Index Terms—Electrostatic discharge (ESD), ESD protection circuit, mixed-voltage I/O buffer, silicon controlled rectifier (SCR).
I. INTRODUCTION
T
O IMPROVE circuit operating speed and performance, the device dimensions of MOSFET have been shrunk in the advanced deep-submicron integrated circuits. In order to follow the constant-field scaling requirement and to reduce power consumption, the power-supply voltages in CMOS ICs have also been scaled downwards. So, most microelectronic systems require the interfacing of semiconductor chips or subsystems with different internal power-supply voltages. With the mix of power-supply voltages, chip-to-chip interface I/O circuits must be designed to avoid electrical overstress across the gate oxide [1], to avoid hot-carrier degradation [2] on the output devices, and to prevent undesirable leakage current paths between the chips [3], [4]. For example, a 5-V interface is generally required for ICs realized in CMOS processes with a normal internal power-supply voltage of 2.5 or 3.3 V. The traditional CMOS I/O buffer with of 3.3 V is shown in Fig. 1(a), with output and input stages. When an external 5-V signal is applied to the I/O pad, the channel of the output pMOS and the parasitic drain–well junction diode in the output pMOS cause the leakage current paths from the I/O pad to , shown by the dashed lines in Fig. 1(a). Moreover, the gate oxides of the output nMOS, the gate-grounded nMOS for input electrostatic discharge (ESD) protection, and the Manuscript received October 1, 2001; revised April 1, 2002. This work was supported in part by the National Science Council, Taiwan, by the Industrial Technology Research Institute, Taiwan, and by the 2001 Dragon Thesis Award of the Acer Foundation, Taiwan.M.-D. Ker is with the Integrated Circuits and Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C. (e-mail: [email protected]).
C.-H. Chuang was with the Integrated Circuits and Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C. He is now with Faraday Technology Corporation, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C.
Publisher Item Identifier 10.1109/JSSC.2002.800933.
(a)
(b)
Fig. 1. Typical circuit diagram for (a) the traditional CMOS I/O buffer, and (b) the mixed-voltage I/O buffer with the stacked-nMOS and the self-biased-well pMOS.
input inverter stage are overstressed by the 5-V input signal. To solve the gate-oxide reliability issue without using the additional thick gate oxide process (also known as dual gate oxides in some CMOS processes [5], [6]), the stacked-MOS configuration has been widely used in the mixed-voltage I/O buffers [7]–[12], and in the power-rail ESD clamp circuits [13]. The typical 3-V/5-V-tolerant mixed-voltage I/O circuit is shown in Fig. 1(b) [8]. The pull-up pMOS, connected from the I/O pad to the power line, has self-biased circuits for tracking its gate and n-well voltages, when the 5-V input signals enter the I/O pad. The maximum output voltage level of such a 3-V/5-V-tolerant I/O buffer is only (3.3 V).
ESD stresses on an I/O pad have four basic pin-combi-nation modes: positive-to- (PS-mode), negative-to-(NS-mode), positive-to- (PD-mode), and negative-to-(ND-mode) ESD stress conditions [14], [15]. To have high enough ESD robustness of the CMOS output buffer, the CMOS buffer is generally drawn with larger device dimensions and a wider spacing from the drain contact to the poly gate, which often occupy a larger layout area in the I/O cell. The -to- ESD clamp circuits across the power lines of CMOS ICs have been reported to effectively increase ESD 0018-9200/02$17.00 © 2002 IEEE
the pad to power line, and cannot be discharged through the additional power-rail ( -to- ) ESD clamp circuit. Such positive-to- ESD current on the I/O pad is discharged through the stacked-nMOS in the snapback breakdown condi-tion. However, the nMOS in stacked configuration has a higher trigger voltage and a higher snapback holding voltage , but a lower secondary breakdown current , as compared to the single nMOS [19]. Therefore, such mixed-voltage I/O circuits with stacked nMOS often have much lower ESD levels under the positive-to- ESD stress condition, as compared to the I/O circuits with a single nMOS [19], [20].
To increase ESD level of such mixed-voltage I/O circuits, some designs with extra multiple diodes in stacked configura-tion have been added from the I/O pad to the power line [3], [4]. However, while mixed-voltage I/O circuits operate in a high-temperature environment with a high-voltage input, the forward-biased leakage current from the pad to through the stacked diodes with their parasitic vertical p-n-p bipolar junction transistors (BJT) devices must be reduced by some extra circuit designs [21]–[24]. To sustain a high ESD level within a smaller silicon area, the low-voltage-triggering SCR (LVTSCR) device [25]–[27] has been reported as one of the most effective ESD clamp devices in CMOS ICs. But, such an LVTSCR device cannot be directly applied to protect the mixed-voltage I/O buffers due to gate-oxide reliability issue on the thin-oxide nMOS, which is inserted in the LVTSCR device structure without using the thick gate oxide.
In this paper, a new ESD protection circuit is proposed to significantly improve ESD robustness of the mixed-voltage I/O buffers by using the stacked-nMOS triggered SCR device [28]. The new proposed ESD protection circuit, which combines the stacked-nMOS structure with the gate-coupling circuit technique into the SCR device, is fully process compatible for general mixed-voltage I/O circuits without causing the gate-oxide reliability problem. Without using the thick gate oxide, the proposed ESD protection design for 3-V/5-V-tol-erant mixed-voltage I/O buffer has been successfully verified in a 0.35- m CMOS process.
II. ON-CHIP ESD PROTECTIONCIRCUIT WITH STACKED-NMOS TRIGGERED SILICON
CONTROLLEDRECTIFIER
The proposed ESD protection design with the stacked nMOS triggered silicon controlled rectifier (SNTSCR) device for protecting the mixed-voltage I/O buffer is shown in Fig. 2(a).
(a)
(b)
Fig. 2. (a) Proposed ESD protection circuit with the SNTSCR device to protect the mixed-voltage I/O buffer. (b) Realizations of the SNTSCR device and the ESD detection circuit with the gate-coupling technique to trigger on the SNTSCR device.
The SNTSCR device structure and the ESD detection circuit are shown in Fig. 2(b). The ESD detection circuit, designed by using the gate-coupling technique with consideration of the gate-oxide reliability issue, is used to provide suitable gate biases to trigger on the SNTSCR device during the ESD stress condition. On the contrary, this ESD detection circuit must keep the SNTSCR off when the IC is under normal circuit operating conditions. Detailed device behaviors, circuit operating principles, and circuit design technique are given in the following.
A. Device Structure and Its Characteristics
The cross-sectional view of the proposed SNTSCR device is shown in Fig. 2(b). This SNTSCR device structure can be real-ized in general CMOS processes without any extra process mod-ification. In the SNTSCR device, two nMOS transistors (Mn1 and Mn2) are stacked in the cascoded configuration, where the drain of Mn1 is across the junction between an n-well region and the p-substrate. The p diffusion, n-well, p-substrate, and n diffusion to form a lateral SCR device for ESD current path between the I/O pad and is indicated by the dashed line in
Fig. 3. Measured dcI–V curves of the fabricated SNTSCR device with channel length of 0.35m for both Mn1 and Mn2 under different gate biases (X axis: 1 V/div; Y axis: 1 mA/div).
Fig. 2(b). The purpose of Mn1 and Mn2 connected in stacked configuration is to sustain the high voltage level of input signals without causing gate-oxide reliability issues in the SNTSCR device under the normal circuit operating condition. If only a single nMOS is inserted in the lateral SCR device, such as the traditional LVTSCR [25], the voltage across the gate oxide will be greater than when a high-voltage signal enters into the I/O pad. This causes the gate-oxide reliability issue on the tradi-tional LVTSCR for long-time operation in such mixed-voltage I/O circuits. During ESD stress condition, Mn1 and Mn2 are both turned on by suitable gate-biased design to trigger the lat-eral SCR on for discharging ESD current. Without using the thick gate oxide in CMOS process, the proposed SNTSCR de-vice has no gate-oxide reliability issue for using to protect the mixed-voltage I/O circuits.
The measured – characteristics of a standalone SNTSCR device with channel length of 0.35 m for both Mn1 and Mn2 under different gate biases of and are shown in Fig. 3. The trigger voltage of the SNTSCR device decreases from 10 to 6 V, when the gate bias increases from V
to V. As V, both
the Mn1 and Mn2 are turned on to trigger SNTSCR on, there-fore the decreases to around 1–2 V. The holding voltage of the SNTSCR device is around 1 V, which is not obviously changed by the different layout parameters on the channel length of Mn1 and Mn2 in this investigation. With suitable gate biases on Mn1 and Mn2, the trigger voltage of SNTSCR device can be reduced much lower than the snapback breakdown voltage of the stacked-nMOS (about 10 V) in the mixed-voltage I/O buffer. Therefore, the new proposed ESD protection circuit with the SNTSCR device can effectively protect the mixed-voltage I/O buffers.
B. Operating Principles
Fig. 4(a) and (b) shows the desired voltage waveforms of the gate biases ( and ) provided by the ESD detection circuit in the normal circuit operating condition and the ESD stress
(a) (b)
Fig. 4. Gate voltages onV andV of the SNTSCR device during (a) the normal circuit operating condition, and (b) the ESD stress condition, in a 3-V/5-V-tolerant mixed-voltage I/O circuit.
condition, respectively, in the 3-V/5-V-tolerant mixed-voltage I/O circuit.
In the normal circuit operating condition, the SNTSCR is kept off, so that it does not interfere with the voltage levels of signals on the I/O pad. At such a normal state, the Mn3 in Fig. 2(b) acts as a re-sistor to bias the gate voltage of Mn1 at . But, the gate of Mn2 is grounded through the resistor . When the I/O pad is ap-pliedwitha highinput voltage (5 V),the center commonn region between the Mn1 and Mn2 transistors has a voltage level of about (where is the thresholdvoltageofnMOS). So, all the devices in the ESD protection circuit can meet the limited elec-trical-field constraint of gate-oxide reliability during the normal circuit operation condition. When the voltage of the I/O pad trans-fers from 0 to 5 V, the coupled gate voltage of Mn2 through the capacitor is designed to be below the threshold voltage of nMOS, as that shown in Fig. 4(a). The coupled voltage through the capacitor can also increase the gate voltage of Mn1, when the voltage on the I/O pad transfers from 0 to 5 V. The pMOS (Mp) in Fig. 2(b) is therefore designed to clamp the excessive voltage once the voltage of Mn1’s gate increases to (where is the magnitude of the threshold voltage of Mp). The cor-responding voltage waveforms on and are illustrated in Fig. 4(a), when the voltage on I/O pad transfers from 0 to 5 V. By suitable design on the ESD detection circuit, the SNTSCR can be kept off under the normal circuit operating condition. Moreover, the pMOS (Mp) can further clamp the gate voltage of Mn1 to en-sure gate-oxide reliability on Mn1, even if the I/O pad has a high input voltage level.
During the positive-to- ESD stress condition, a positive high ESD voltage is applied to the I/O pad with grounded but floating. In this ESD stress condition, the gate of Mp is grounded since the initial voltage level on the floating power line is zero. So, the Mp is turned on, but the Mn3 is off. The capacitors and are designed to couple ESD transient voltage from the I/O pad to the gates of Mn1 and Mn2, respec-tively. The coupled voltage should be designed higher than the threshold voltage to turn on Mn1 and Mn2 for triggering the
A. Design Optimization on the ESD Detection Circuit
The purpose of the ESD detection circuit is to provide the suitable gate biases for the SNTSCR device under the normal circuit operating condition and ESD stress condition. To obtain suitable gate biases, it is important to determine the values of the coupling capacitors and and the sustaining resistors and . Based on the above operating principles, the suitable values of , , , and to meet the desired circuit oper-ation in different CMOS processes can be adjusted and finely tuned by using HSPICE simulation.
The dependence between the coupling capacitance and the sustaining resistance can be investigated by HSPICE simulation with different turn-on time periods on Mn1 and Mn2. A 0–5-V input waveform with a rise time of 10 ns is used to simulate a 5-V input signal applied to the I/O pad, when the mixed-voltage I/O circuit is under normal circuit operating condition with bias of 3.3 V. The HSPICE-simulated voltage waveforms on and are shown in Fig. 5(a), when the is chosen at 20 fF and the is chosen at 130 k . The coupled voltage on in Fig. 5(a) is smaller than 0.6 V , therefore the SNTSCR is not triggered on. The coupled voltage on is further limited to 3.8 V after the rising transition of the input 5-V signal, which is clamped by the pMOS Mp in Fig. 2(b).
The SNTSCR device should be triggered on by the ESD detection circuit during the ESD stress condition, before the devices in the mixed-voltage I/O circuit are broken down by the overstress ESD voltage. A 0–10 V ramp voltage waveform with a rise time of 5 ns is therefore used to simulate the rising transition of ESD voltage, before the mixed-voltage I/O circuit is broken down by ESD voltage. Under the positive-to-ESD stress condition, is floating with an initial voltage level of 0 V. The HSPICE-simulated voltage waveforms on and under such an ESD stress condition are shown in Fig. 5(b), when the ( ) is still kept at 20 fF (130 k ). The coupled voltage on and in Fig. 5(b) are both greater than 0.6 V . From the measured results shown in Fig. 3, the SNTSCR is turned on when the and are greater than 0.6 V. Therefore, the SNTSCR can be triggered on to discharge ESD current before the mixed-voltage I/O circuit is broken down by ESD voltage.
To further investigate the dependence between the coupling capacitors and sustaining resistors to trigger on the SNTSCR device under ESD stress condition, a turn-on time is further defined in Fig. 5(b) as the time period when the cou-pled voltages on and are both greater than the nMOS
(a)
(b)
Fig. 5. HSPICE-simulated results under (a) the normal circuit operating condition with a 5-V input signal, and (b) the ESD stress condition with a 10-V rising voltage, on the I/O pad.
threshold voltage under such a 0–10 V rising transition. In Fig. 5(b), the turn-on time is found to be about 17 ns. This turn-on time can be further adjusted by changing the coupling capacitors and sustaining resistors in the ESD detection circuit. The values of the coupling capacitors and sustaining re-sistors are changed and simulated by HSPICE to choose suitable and values for different required turn-on times.
Fig. 6 depicts the simulated results on the relation between coupling capacitance and sustaining resistance under two different turn-on times (10 and 20 ns). The turn-on time can be kept the same by using different values of the coupling capacitance and sustaining resistance. This leads to a more feasible design to realize the ESD detection circuit in different CMOS processes. To obtain a longer turn-on time, the and have to be designed with larger values, but, with too much larger and , the SNTSCR could be also trigged on by the normal 0–5 V input signals under the normal circuit operating condition. Therefore, there is a design boundary to choose suitable and to meet the desired circuit operation. Such a design boundary on the coupling capacitance and sustaining resistance can be found by HSPICE simulation, which is shown by the dashed line in Fig. 6. The overdesign region in Fig. 6 means that the coupling capacitance is overdesigned in the ESD
Fig. 6. HSPICE-simulated results on the relation between the coupling capacitanceC = C and the sustaining resistance R = R under different turn-on times.
Fig. 7. Modified design on the ESD detection circuit with the SNTSCR device to have a larger design region on the sustaining resistance and coupling capacitance for protecting the mixed-voltage I/O buffer.
detection circuit, which will cause the unexpected turn-on of SNTSCR under normal 5-V input operation. So, the coupling capacitance and sustaining resistance located in the overdesign region is not suitable for practical applications. With the design boundary, the coupling capacitance and sustaining resistance in ESD detection circuit can be still correctly chosen to meet the desired circuit operation for a given CMOS process.
B. Improved Design Window for and
To further improve the design region for easily choosing the suitable sustaining resistance and coupling capacitance in gen-eral CMOS processes, a modified design on the ESD detection circuit with an additional nMOS (Mn4) is shown in Fig. 7. The extra device, Mn4, is added across the sustaining resistor , which is located between the gate of Mn2 and . The gate of Mn4 is biased at . The gate of Mn4 is better connected to the power line through a diffusion resistor for considera-tion with the antenna rule issue. Under the normal circuit oper-ating condition, Mn4 is always turned on to clamp the coupling voltage below the threshold voltage , and to keep the
Fig. 8. HSPICE-simulated results on the relation between the coupling capacitanceC = C and the sustaining resistance R = R under different turn-on times of the modified ESD detection circuit in Fig. 7 to have a wider design window.
Fig. 9. HSPICE-simulated voltage waveforms onV and V in the modified circuit of Fig. 7, under normal operating condition with a 5-V input signal of 1-ns rise time on the I/O pad.
Mn2 always off. Therefore, the SNTSCR can be guaranteed off under the normal circuit operating condition.
Under the ESD stress condition, Mn4 is off since the initial voltage level on the floating power line is zero. The voltage coupled to the gate of Mn2 is determined by the sustaining resistance and the coupling capacitance . Therefore, the suitable design window for the sustaining resistance and cou-pling capacitance of this modified ESD detection circuit can be obviously improved. The sustaining resistance and coupling ca-pacitance of this modified ESD detection circuit to have the de-sired turn-on times of 10 or 20 ns are simulated and shown in Fig. 8, where the entire region is suitable for choosing the sus-taining resistance and coupling capacitance.
With a device dimension ( ) of only 10 m/0.35 m for Mn4, the and voltage waveforms in this modified cir-cuit, under the normal circuit operating condition with a 5-V input signal applied to the I/O pad, is simulated and shown in Fig. 9, where the input signal has a rise time of only 1 ns. As seen in Fig. 9, even if the rise time of the 5-V input signal is as fast as 1 ns, the coupled voltage waveform during the input
(a)
(b)
Fig. 10. Modified deign of the ESD protection circuit with the SNTSCR device for the mixed-voltage I/O buffer to have (a) higher noise margin to the I/O signals, and (b) no extra additional parasitic capacitance to the I/O pad.
transition can be kept always smaller than its . Therefore, the SNTSCR can be guaranteed off under the normal circuit oper-ating condition by this modified circuit design. By only adding the Mn4 into the ESD detection circuit, it becomes very easy and feasible to determine the suitable values for the coupling capacitance ( and ) and the sustaining resistance ( and
).
C. Modified Design to Improve Noise Margin of SNTSCR
When the mixed-voltage I/O buffer is under normal circuit operating condition with a high-voltage input signal, the over-shooting noise pulse generated from the external circuits or in-terfaces could be coupled into the I/O pad to accidentally trigger on the SNTSCR in the ESD protection circuit [29]–[32]. To further improve the noise margin of the SNTSCR device in the proposed ESD protection circuit without being accidentally triggered on during normal circuit operating condition, a fur-ther modified design is shown in Fig. 10(a). The ESD detection circuit is connected from the self-biased n-well of the pull-up pMOS, where the parasitic drain–well diode Dp between the I/O pad and the n-well essentially exists in the pMOS device
the ESD detection circuit and the SNTSCR device) to the I/O pad. With this modified connection, the ESD protection circuit with the SNTSCR device also has a higher noise margin to the overshooting glitch at the I/O pad, during the normal circuit operating condition. Under the positive-to- ESD stress condition, the ESD current first flows through the parasitic diode Dp into the floating n-well of the pull-up pMOS, and then is discharged to through the turned-on SNTSCR device. The coupling capacitance ( and ) in the ESD detection circuit and the parasitic junction capacitance in the SNTSCR device are blocked from the I/O pad by the drain–well diode Dp in the pull-up pMOS. This modified design is more suitable for high-speed I/O applications, which often require a lower input loading capacitance to the I/O pad.
IV. EXPERIMENTALRESULTS
The experimental test chip has been fabricated in a 0.35- m silicided CMOS process. There is a thin-oxide pull-up pMOS (pull-down stacked-nMOS) device placed between the I/O pad and ( ). The capacitors ( and ), resistors ( and ), Mp, Mn3, and Mn4 are composed of the ESD detection circuit for providing suitable gate biases to the SNTSCR device. Capacitors and are realized by inserting the metal layer right under the metal bond pad without adding extra layout area to the I/O cell. Their capacitance can be adjusted by changing the overlap area between the metal layer and the bond pad metal. and are realized by the n-well resistance, and their resistance can be adjusted by changing the length of the n-well regions in layout.
A. Leakage Current
The leakage current under normal circuit operating condi-tions is a concern for an ESD protection circuit connected to an I/O pin. The leakage currents of the fabricated mixed-voltage I/O buffers with and without the proposed ESD protection cir-cuit are measured and compared in Fig. 11. The leakage current is measured (using an HP4155) by applying a voltage ramp from 0 to 5 V to the I/O pad under the bias condition of 3.3-V and 0-V . In Fig. 11, the maximum leakage current of the mixed-voltage I/O buffer without (with) the proposed ESD pro-tection circuit under 5-V bias at the I/O pad is 175 (215) pA. The increase of the leakage current from adding the ESD pro-tection circuit is only 40 pA, whereas the SNTSCR device in the ESD protection circuit is drawn with a device width of 60 m. The mixed-voltage I/O buffer in this measurement has a channel
Fig. 11. Comparison of the leakage current of the mixed-voltage I/O buffers with and without the proposed ESD protection circuit. The mixed-voltage I/O buffer in this measurement has a channel width of 180m in the stacked-nMOS and a channel width of 360m in the pull-up pMOS.
Fig. 12. Comparison of the positive-to-V HBM ESD robustness of the mixed-voltage I/O buffers with and without the proposed ESD protection circuit, under different channel widths of the stacked nMOS in the mixed-voltage I/O buffers.
width of 180 m in the stacked nMOS and a channel width of 360 m in the pull-up pMOS.
B. ESD Robustness
The positive-to- human-body-model (HBM) [14] ESD levels of the mixed-voltage I/O buffers with and without the proposed ESD protection circuit are measured and compared in Fig. 12. The mixed-voltage I/O buffers with different stacked-nMOS channel widths are also tested as a reference. The HBM ESD level of the mixed-voltage I/O buffer (with stacked-nMOS channel width of 120 m) can be obviously improved from the original 2 kV to become greater than 8 kV by the proposed ESD protection circuit with the SNTSCR device. In Fig. 12, all the mixed-voltage I/O buffers protected by the proposed ESD protection circuit have the same SNTSCR device width of 60 m.
The HBM ESD robustness of the mixed-voltage I/O buffer, with and without the proposed ESD protection design (including
TABLE I
HBM ESD ROBUSTNESS OF THEMIXED-VOLTAGEI/O BUFFERWITH ANDWITHOUT THEPROPOSEDESD PROTECTIONDESIGNWITH
THESNTSCR DEVICE
the SNTSCR device), under the four pin-combination modes of ESD stress on the I/O pad, is listed in Table I. The stacked nMOS of the mixed-voltage I/O buffer in this ESD test has a of only 60 m/0.5 m, and the pull-up pMOS of the mixed-voltage I/O buffer has a of only 120 m/0.5 m. The stacked nMOS in the SNTSCR device has a of 60 m/0.35 m. As seen in Table I, the ESD levels under the PS-, NS-, and PD-modes have been significantly improved by the proposed ESD protection design with the SNTSCR device. Especially, the PS- and PD-mode ESD levels of the mixed-voltage I/O buffer have a great increase. In Table I, the ND-mode ESD stress is not improved, because the -to- ESD clamp circuit is not included in the test chip in this investigation. During the neg-ative-to- ESD stress, the ESD current may be discharged through the pull-up pMOS, or be first conducted to the power line and then discharged through the -to- ESD clamp circuit to the grounded . Without the -to-ESD clamp circuit in this test chip, the original -to-ESD levels of the mixed-voltage I/O buffer (without SNTSCR device) in the PD- and ND-mode ESD stresses are almost the same of 2.8 kV 2.9 kV. In the whole-chip layout of a CMOS IC, the turn-on efficient -to- ESD clamp circuit [16]–[18], [21], [24] should be added into the chip layout to improve the ND-mode ESD level of the mixed-voltage I/O buffers and also to avoid unexpected internal ESD damages.
The transmission line pulse generator (TLPG) with a pulse width of 100 ns is also used to verify the secondary breakdown current of the mixed-voltage I/O buffers with and without the proposed ESD protection circuit, and the measured results are shown in Fig. 13 under the positive-to- ESD stress condi-tion. The of the stacked nMOS with channel width of 180 m is around 2 A, but it can be increased up to 7 A by the proposed ESD protection circuit with an SNTSCR device of 60 m. The measured values are consistent to the HBM ESD level with a factor around 1.5 k . This has further verified the effective-ness of the proposed ESD protection circuit with the SNTSCR device.
The positive-to- machine-model (MM) [15] ESD levels of the mixed-voltage I/O buffers with and without the proposed ESD protection circuit are measured and compared in Fig. 14. The mixed-voltage I/O buffers with different stacked-nMOS channel widths are also tested as a reference. From the mea-sured results, the MM ESD level of the mixed-voltage I/O buffer with a channel width of 120 m in the stacked nMOS can be significantly improved from the original 200 V to
Fig. 13. Comparison of the TLPG-measuredI–V curves of the mixed-voltage I/O buffers with and without the proposed ESD protection circuit, under different channel widths of the stacked nMOS in the mixed-voltage I/O buffers.
Fig. 14. Comparison of the positive-to-V MM ESD robustness of the mixed-voltage I/O buffers with and without the proposed ESD protection circuit, under different channel widths of the stacked nMOS in the mixed-voltage I/O buffers.
become 800 V by the proposed ESD protection circuit with an SNTSCR device width of only 60 m.
C. Turn-on Verification
To verify the turn-on efficiency of the proposed ESD pro-tection circuit, a 0–8 V sharply rising voltage pulse with a rise time of 10 ns is applied to the I/O pad when is relatively grounded but is floating (to simulate the positive-to-ESD stress condition). The stacked nMOS in the output buffer has a snapback breakdown voltage of 10 V. Such a 0–8 V voltage pulse applied to the I/O pad does not break down the stacked nMOS of the mixed-voltage output buffer, but the 0–8 V voltage pulse can trigger on the ESD protection circuit to cause a degraded voltage waveform, as that shown in Fig. 15, where the applied 0–8 V voltage pulse is clamped to 2 V by the SNTSCR device. The mixed-voltage I/O buffer used in this measurement has the additional device Mn4, as shown in Fig. 7. During the positive-to- ESD stress, the gate of Mn4 is initially kept at 0 V. Therefore, the coupled gate voltage of Mn2 (Mn1) through the capacitor is sustained longer in time by the sus-taining resistor in Fig. 7. The SNTSCR device is there-fore triggered on by the coupled gate voltages and to
Fig. 15. Measured voltage waveform on the I/O pad triggered by a 0–8 V voltage pulse with a rise time of 10 ns, under the positive-to-V ESD stress condition. (Y axis: 2 V/div.; X axis: 100 ns/div.)
(a)
(b)
Fig. 16. Measured voltage waveforms on the I/O pad triggered by (a) 0–5 V and (b) 0–10 V voltage pulses with a rise time of 10 ns, under the normal operating condition withV = 3:3 V and V = 0 V. (Y axis: 2 V/div.; X axis: 100 ns/div.)
clamp the voltage on the I/O pad. The degraded voltage wave-form has verified the effectiveness of the proposed ESD pro-tection circuit with the SNTSCR device to protect the
mixed-voltage I/O circuits. The transition time of 10 ns from 8 to 2 V in Fig. 15 is the corresponding turn-on speed of the SNTSCR device realized in this 0.35- m CMOS process.
In the normal circuit operating condition with the
biased at 3.3 V (0 V), a 0–5 V input voltage pulse with a rise time of 10 ns is applied to the I/O pad. The voltage on the I/O pad is monitored by a digital oscilloscope. But the applied 0–5 V voltage waveform is not degraded, as shown in Fig. 16(a). The mixed-voltage I/O buffer used in this measurement has the additional device Mn4. During the normal circuit operating con-dition, the gate of Mn4 is biased at (3.3 V). The coupled gate voltage of Mn2 through the capacitor is discharged to ground by the turned-on Mn4. So, the SNTSCR device is not triggered on by the normal input signals of 5 V. If the applied voltage pulse is further increased to 10 V under the normal cir-cuit operating condition, the measured voltage waveform on the I/O pad is shown in Fig. 16(b). The applied 0–10 V voltage pulse is clamped to about 6 V in Fig. 16(b), but not to the voltage level of 2 V, as shown in Fig. 15. The stacked nMOS has a snapback breakdown of 10 V and a snapback holding voltage of 6 V in this 0.35- m CMOS process. Therefore, the degraded voltage level of 6 V in Fig. 16(b) is clamped by the stacked nMOS of the mixed-voltage I/O buffer in the snapback region. If the SNTSCR device in the ESD protection circuit is triggered on, the voltage level should be clamped to its holding voltage of 2 V. However, the applied 0–10 V voltage pulse is only clamped to 6 V, as shown in Fig. 16(b). This result has further confirmed that the additional Mn4 device (added in the ESD detection circuit) can safely apply the SNTSCR device to protect the mixed-voltage I/O buffer without being unexpect-edly triggered under the normal circuit operating condition.
V. CONCLUSION
A new ESD protection design, using the stacked-nMOS trig-gered silicon controlled rectifier (SNTSCR) device, has been successfully verified in a 0.35- m CMOS process. The – characteristics of the SNTSCR device with different gate biases and the turn-on behaviors of the ESD protection circuit have been measured to verify its effectiveness. By using the ESD de-tection circuit with suitable design on the coupling capacitance and sustaining resistance, the SNTSCR device can be fully trig-gered on within 10 ns to discharge ESD current. By changing the connection of the ESD protection circuit from the I/O pad to the floating n-well of the pull-up pMOS in the mixed-voltage I/O circuit, the SNTSCR device has a high enough noise margin to the overshooting glitch on the I/O pad, during the normal circuit operating condition. Without using the thick gate oxide, this new proposed ESD protection circuit is fully process com-patible with general sub-quarter-micron CMOS processes for effectively protecting the mixed-voltage interface circuits on the input and output pins.
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Ming-Dou Ker (S’92–M’94–SM’97) received the
B.S. degree from the Department of Electronics Engineering, and the M.S. and Ph.D. degrees from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, in 1986, 1988, and 1993, respectively.
In 1994, he joined the VLSI Design Department of the Computer and Communication Research Lab-oratories (CCL), Industrial Technology Research In-stitute (ITRI), Taiwan, as a circuit design engineer. In 1998, he has been a Department Manager in the VLSI Design Division of CCL/ITRI. Since 1994, he has also been a Research Advisor in the Integrated Circuits and Systems Laboratory of National Chiao-Tung Uni-versity. In 2000, he became an Associate Professor in the Department of Elec-tronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan. In the field of ESD protection and latch-up in CMOS integrated circuits, he has pub-lished over 115 technical papers in international journals and conferences. He holds 101 patents on ESD protection design for integrated circuits, including 37 U.S. patents. He has been invited to teach or consult on ESD protection design by more than 100 IC design houses or semiconductor companies in the Sci-ence-Based Industrial Park, Hsinchu, Taiwan, and in Silicon Valley, San Jose, CA. He has also participated as a member of the Technical Program Committee and as Session Chair of many international conferences. He was elected as the first President of the Taiwan ESD Association in 2001.
