646 IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 9, SEPTEMBER 2005
Reduction of Leakage Current in Metal-Induced
Lateral Crystallization Polysilicon TFTs With
Dual-Gate and Multiple Nanowire Channels
Yung-Chun Wu, Ting-Chang Chang, Po-Tsun Liu, Cheng-Wei Chou, Yuan-Chun Wu, Chun-Hao Tu, and
Chun-Yen Chang, Fellow, IEEE
Abstract—This letter addresses the leakage current in nickel
(Ni) metal-induced lateral crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with multiple nanowire chan-nels and dual-gate. Experimental results reveal that applying multiple nanowire channels improves the Ni-MILC poly-Si TFT performance. However, the leakage current of both single-gate with single-channel and multiple nanowire channels remains high ( 10 8A), because of the field emission of carriers through the poly-Si grain traps and the defects caused by Ni contamination. Applying the dual-gate structure can suppress the electrical filed in the drain depletion region, significantly reducing the leakage current of the Ni-MILC poly-Si TFT, increasing theON/OFFratio.
Index Terms—Dual-gate, metal-induced lateral crystallization
(MILC), nanowire, thin-film transistor (TFT).
I. INTRODUCTION
H
IGH-PERFORMANCE thin-film transistors (TFTs) fabricated on a polysilicon film formed by metal-induced lateral crystallization (MILC) using Ni have attracted much interest because of their potential use in three-dimensional circuit technology [1], liquid-crystal display (LCD) drivers and system-on-panel (SOP) applications [2]. It is a low-cost batch process that yields superior poly-Si films. However, the applications of Ni-MILC poly-Si TFTs remain limited, because the grain boundaries of poly-Si in the channel region substan-tially degrade performance. The electrical characteristics of the TFTs can be improved by reducing the number of defects in the poly-Si grain boundaries in the channel, and poly-Si TFTs with several multichannels have been reported to effectively reduce grain boundary defects [3], [4]. The Ni-MILC poly-Si TFT suffers from higher leakage current because of Ni con-tamination during MILC annealing [2], [5], [6] than those by solid phase crystallization and laser crystallization. The Ni impurity atomic percentage in MILC region was determined of 0.08% by secondary ion mass spectroscope (SIMS) analysis [5]. This Ni defects induced leakage current is directly relatedManuscript received May 27, 2005; revised June 27, 2005. The review of this letter was arranged by Editor J. Sin.
Y.-C. Wu, C.-W. Chou, Y.-C. Wu, C.-H. Tu, and C.-Y. Chang are with the Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.
T.-C. Chang is with Department of Physics and the Institute of Electro-Op-tical Engineering, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan, R.O.C. (e-mail: [email protected]).
P.-T. Liu is with Department of Photonics and Display Institute, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.
Digital Object Identifier 10.1109/LED.2005.854382
to the lateral electrical field in the drain depletion region in the off-state [7]. This is another major limitation on Ni-MILC poly-Si TFT applications. According to previous report, the poly-Si TFTs adopted multigate can effectively reduce leakage current, addressing this leakage issue [8].
This work develops a single-gate with a single-channel, a single-gate with multiple nanowire channels, and a dual-gate with multiple nanowire channels in the Ni-MILC poly-Si TFT to study their leakage current and performance. The experi-mental results reveal that a dual-gate with multiple nanowire channels structure can significantly reduce the leakage current, while maintaining the high performance of the Ni-MILC TFT.
II. DEVICESTURCTURE, SIMULATION,ANDFABRICATION
In this letter, three Ni-MILC poly-Si TFTs, one with a single-gate length of 5 m and a single-channel width of 1 m (G1S1), one with a single-gate length of 5 u m and ten strips of 84-nm wire channels (G1M10), and one dual-gate, each gate with a length of 2.5 m and ten strips of 84-nm wire channels (G2M10) were fabricated. Fig. 1(a) presents the top view of G2M10 Ni-MILC poly-Si TFT with source, drain, nanowire channels, a Ni-MILC seeding window and a dual-gate. The inset table lists all device dimensions. Fig. 1(b) presents the cross-sectional view of Ni-MILC poly-Si TFT, with a conventional top dual-gate, self-aligned offset MOSFET structure. As the anomalous off-current (leakage current) in the poly-Si TFTs is related to the lateral electrical field in the channel. Fig. 2 presents the simulation results obtained using an ISE TCAD 2-D device simulator of the lateral electrical field of the single-gate (G1) and dual-gate (G2) TFTs with the same bias condition. The peak lateral electrical field of the dual-gate TFT is lower than that of the single-gate TFT, indicating that the dual-gate (G2) structure effectively reduces the leakage current of poly-Si TFTs. The inset picture shows scanning electron microscopy (SEM) photography of active pattern with the source, the drain, ten nanowire channels and dual-gate. The each dual-gate length is 2.5 m, and the each channel width is 84 nm.
The 6-in p-type single crystal silicon wafers were coated 400-nm-thick SiO as the starting materials. Undoped 50-nm-thick amorphous-Si (a-Si) layer were deposited by low-pressure chemical vapor deposition (LPCVD) at 550 C. Then the active islands, including source, drain, and ten nanowire channels were patterned by Electron Beam lithography (EBL) and transferred
WU et al.: REDUCTION OF LEAKAGE CURRENT IN POLYSILICON TFTs 647
Fig. 1. (a) Topview plot of G2M10 Ni-MILC poly-Si TFT with source, drain, nanowire channels, Ni-MILC seeding window, and dual-gate. Device dimensions of all proposed Ni-PDMILC poly-Si TFTs are listed in inset table. (b) Cross-sectional view of Ni-MILC poly-Si TFT, which was a conventional top-gate, self-aligned offset MOSFET structure. All devices have the same active channel thickness of 50 nm and a gate TEOS-oxide thickness of 25 nm.
by reactive ion etching (RIE). After defining the active region, the 25-nm-thick tetra-ethyl-ortho-silicate oxide (TEOS-SiO ) was deposited by LPCVD as gate insulator. Then, 150-nm-thick undoped poly-Si films were deposited immediately on the gate oxide by LPCVD. The poly-Si layers were patterned by EBL and transferred by RIE to define the gate electrode. After gate formation, a 100-nm-thick TEOS-SiO layer as passivation layer was deposited by LPCVD. The poly-Si gate sidewall TEOS-SiO was formed self-aligned offset spacer with the width of 0.1 m, as shown in Fig. 1(b). Then, the MILC seeding window and contact holes were patterned by EBL and transferred by RIE in the same mask process. Then, a thin 10-nm-thick nickel (Ni) layer was deposited by physical vapor deposition (PVD). The MILC crystallization was carried out at 550 C for 48 h in an N ambient. The MILC crystallization length of 30 m, which is longer than 16 m [Fig. 1(a)] to promise the whole active channel was crystallized by MILC process. After annealing, the unreacted nickel on passivative TEOS-SiO were removed by H SO solution at 120 C with 10 min. Phosphorus ions at a dose of cm were implanted through the passivative TEOS-SiO to form the n+ gate, source/drain regions, and the self-aligned offset region
Fig. 2. Off-state lateral electrical field simulation results of single-gate and dual-gates poly-Si TFT by ISE TCAD versus 7 (a 2-D device simulator). The inset scanning electron microscopy (SEM) photography shows the active pattern with the source, drain, ten nanowire channels, and dual-gate.
Fig. 3. Comparison ofI –V transfer characteristics of G1S1, G1M10, and G2M10 Ni-MILC poly-Si TFT with the same device effective length(L ) of 5m. The inset table presents the leakage current (I ), maximumON/OFF
ratio and SS.
were formation in the same process step, as shown in Fig. 1(b). Then, the dopants were activated by rapid thermal annealing (RTA) at 850 C with 30 s. The 300-nm-thick aluminum (Al) layer was deposited by physical vapor deposition (PVD) and patterned for source, drain and gate metal pads. In this letter, no other H or NH plasma passivation was performed. This allowed the intrinsic behavior of the devices to be compared and studied.
III. RESULTS ANDDISCUSSION
The inset table of Fig. 3 lists all poly-Si TFT parameters, in-cluding leakage current ,ON/OFFratio and subthreshold swing (SS). The is defined as the drain current at V
648 IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 9, SEPTEMBER 2005
Fig. 4. Comparison ofI –V output characteristics of G1S1, G1M10, and G2M10 Ni-MILC poly-Si TFT with the same device effective length(L ) of 5m.
and V, and theON/OFFratio is defined as the maximum value of at V. By compassion of the single-gate with the single-channel (G1S1) and the ten nanowire chan-nels (G1M10) TFTs in Fig. 3, the G1M10 has a higherON cur-rent, a higherON/OFFratio and a steeper SS than the G1S1. These results reveal that the multiple nanowire channels have fewer defects at grain boundaries. However, both G1S1 and G1M10 exhibit severe leakage current ( A). The large leakage current is generated from the poly-Si grain boundary defects and Ni contamination defects via carrier thermionic field emis-sion and tunneling [7]. Notably, the leakage current of G1M10 of A is larger than that of G1S1 of
A. This result can be explained that the G1M10 suffered from a higher lateral field because its gate control was more robust than that of the G1S1 [9], [10] Ni-MILC poly-Si TFT. By compar-ison of the single-gate (G1M10) and dual-gate (G2M10) with the same ten nanowire channels Ni-MILC poly-Si TFT revealed that the G2M10 leakage current of A was sig-nificantly lower over three decades, whereas theONcurrent of G2M10 is close to that of G1M10 TFT. These findings reveal that the dual-gate structure can reduce the peak lateral electrical field in the drain depletion region. Therefore, the leakage cur-rent that arises from the field emission and tunneling of car-riers through the poly-Si grain traps and the defects associated with Ni contamination was reduced. This finding is consistent with the lower simulation value of the lateral electrical field of dual-gate TFT in Fig. 2. Fig. 4 compares the output curves of G1S1, G1M10, and G2M10 Ni-MILC poly-Si TFTs with the same effective gate length, of 5 m. The kink-effect of G2M10 is suppressed relative to those of the other TFTs. For
the same reason, the dual-gate structure effectively reduces the electrical field, reducing the impaction ionization in the active channel of the Ni-MILC poly-Si TFT. The G2M10 TFT goes into saturation at higher drain bias as compared to G1M10 and G1S1 TFT. This result can be explained that the G2M10 TFT has additional parasitic resistance between two gates [Fig. 1(b)].
IV. CONCLUSION
Experiment results show that applying ten nanowire channels enhances the Ni-MILC poly-Si TFT performance, including a higherON/OFFratio and a steeper SS than that of single-channel TFT. However the leakage current of single-gate Ni-MILC poly-Si TFTs is still high. By applying dual-gate structure can significantly reduce the Ni-MILC TFT leakage current, and increase theON/OFFratio. Only the saturation voltage of output curve is higher than single-gate TFT. This novel multichannel and dual-gate Ni-MILC poly-Si TFTs is quite easy and in-volves no additional processes, thus highly suitable for high-performance MILC poly-Si TFT applications.
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