Highly scaled charge-trapping layer of ZrON nonvolatile memory device with good retention

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Highly scaled charge-trapping layer of ZrON nonvolatile memory device with good

retention

C. Y. Tsai, T. H. Lee, C. H. Cheng, Albert Chin, and Hong Wang

Citation: Applied Physics Letters 97, 213504 (2010); doi: 10.1063/1.3522890

View online: http://dx.doi.org/10.1063/1.3522890

View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/97/21?ver=pdfcov Published by the AIP Publishing

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Highly scaled charge-trapping layer of ZrON nonvolatile memory device

with good retention

C. Y. Tsai,1T. H. Lee,1C. H. Cheng,1Albert Chin,1,a兲and Hong Wang2

1_{Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University,}

Hsinchu 30010, Taiwan

2_{School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798}

共Received 2 August 2010; accepted 5 November 2010; published online 24 November 2010兲 We have fabricated the TaN–关SiO2– LaAlO3兴–ZrON–关LaAlO3– SiO2兴–Si charge-trapping flash device with highly scaled 3.6 nm equivalent-Si3N4-thickness. This device shows large 4.9 V initial memory window, and good retention of 3.4 V ten-year extrapolated retention window at 85 ° C, under very fast 100 ␮s and low⫾16 V program/erase. These excellent results were achieved using deep traps formed in ZrON trapping layer by As+ implantation that was significantly better than those of control device without ion implantation. © 2010 American Institute of Physics.

关doi:10.1063/1.3522890兴

As listed in International Technology Roadmap for

Semiconductors,1 the metal-oxide-nitride-oxide-Si 共MONOS兲 charge-trapping flash 共CTF兲 devices1–15

have high potential to replace the poly-Si floating-gate flash memory for future generation nonvolatile memory共NVM兲 due to the discrete charge-trapping property and simpler planar process. Nevertheless, one fundamental drawback for CTF device is the distributed trap energy in Si3N4 共Ref. 11兲 as compared with the deep 3.15 eV energy in poly-Si floating-gate memory, where charge stored in shallower traps may escape and degrade the retention characteristics.12–15Such degraded retention is one of the major challenges in fewer electrons stored in highly scaled NVM device.1 Although improved retention can be achieved by increasing tunnel oxide thick-ness, this is traded off the intolerable slow erase time 共10– 100 ms兲.

One method to improve the retention is to use a deep conduction band energy共EC兲 high-␬trapping layer.12–16 Sig-nificant retention improvement has been realized by using high-␬Al共Ga兲N in the MONOS CTF that was also listed in ITRS as a key technology for CTF.1 To further lower the program/erase 共P/E兲 voltage, higher␬ HfON trapping layer MONOS has been fabricated,14 but the shortcoming is the lower trapping efficiency in HfON with a smaller memory window.14 To improve the memory window, dual trapping-layer HfON– Si3N4 CTF was used,15 but adding the lower

␬Si3N4 limits further down-scaling the equivalent-nitride thickness共ENT兲. However, scaling ENT to 3–4 nm is needed for future CTF NVM.1Alternatively, lower trapping energy can also be reached by forming nanocrystal in CTF using ion implantation.17–20 In this paper we have used both higher-␬ deep-EC ZrON and As+ implantation to improve the CTF performance. At a 3.6 nm ENT trapping layer, this device has an initial 4.9 V memory window and good retention of 3.4 V extrapolated ten-year retention window at 85 ° C, under fast 100 ␮s and low⫾16 V P/E. This is the thinnest ENT CTF device that meets ITRS scaling target to tenth nanometer.1

The TaN–关SiO₂– LaAlO₃兴–ZrON–关LaAlO₃– SiO₂兴–Si devices were fabricated on standard 6 in. p-type Si wafers. The double tunnel oxide layers of 2.5 nm thermal SiO2were

grown on Si substrates and 2.5 nm LaAlO₃was deposited by physical vapor deposition 共PVD兲. Then the 18 nm ZrON charge trapping layer was deposited by reactive PVD under mixed O₂and N₂. The As+_{-implantation into ZrON was} ap-plied at 3 keV, 5⫻1015 cm−2 dose, and 60° titled angle, which was followed by 950 ° C and 1 s rapid thermal anneal-ing 共RTA兲. It was reported that the memory window in-creases with increasing ion-implanted dose.20 The As+-implant condition of 5⫻1015 cm−2 and 3 keV dose were chosen to reach both the highest possible dose for manufacture and the lowest energy for the thinnest ENT. Next, 8 nm LaAlO₃was deposited by PVD and 6 nm SiO₂ was deposited by chemical vapor deposition of tetraethyl orthosilicate 关Si共C2H5O兲4兴 to form the double blocking lay-ers. Finally, 200 nm TaN was deposited by PVD, followed by gate definition, self-aligned 25 keV As+ _{implantation at 5} ⫻1015 _cm−2_{dose, and 900 ° C RTA to activate the dopant at} source-drain region. The flatband voltage共VFB兲 was obtained from the measured C-V data and quantum-mechanical C-V simulation.21 The threshold voltage 共Vth兲 was determined from the interception of gate voltage共Vg兲 to zero drain cur-rent 共Id兲 of linear Id-Vgcurve.

Figure1compares C-V hysteresis of ZrON CTF devices with and without the As+_{implantation. Larger C-V hysteresis} window of 8.1 V was obtained in As+-implanted CTF than

a兲_{Electronic mail: albert_achin@hotmail.com.}

-9 -6 -3 0 3 6 9 0.0 0.5 1.0 1.5 2.0 2.5 3.0 @ 100kHz V_FBShift 15V 16V 17V

control device w/o implant

As+-implanted ZrON CTF C a p a c ita n c e D e n s ity (fF /  m 2 ) Voltage (V) 15V 16V 17V

FIG. 1. C-V hysteresis of ZrON CTF devices with and without As+

implantation.

APPLIED PHYSICS LETTERS 97, 213504共2010兲

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the 5.7 V of control device under ⫾16 V sweep and close capacitance density of⬃2.6 fF/␮m2for both devices. Since the area of C-V curve is the charge共Q=CV兲, the increase of

V_FB indicates that the As+_{-implanted ZrON has higher trap} density for electron storage. The larger hysteresis window by As+ _{implantation may be due to the forming deep energy} levels in ZrON trapping layer that exists even after 950 ° C RTA. From the frequency-dependent C-V measurements, the

VFB shift 共⌬VFB兲 is independent on frequencies at 10–700 kHz. Thus, the hysteresis memory window is only from the ZrON trapping layer rather than the interface states between tunnel oxide and Si.

Figures2共a兲and2共b兲show the cross-sectional transmis-sion electron microscopy 共TEM兲 and secondary ion-mass spectroscopy 共SIMS兲 of ZrON–关LaAlO₃– SiO₂兴–Si struc-ture with As+ _{implantation. The polygrains were found in} ZrON after 950 ° C RTA that leads to the higher␬ value22,23 with As+implant. From the measured 18 nm ZrON thickness by TEM, an ENT of 3.6 nm was obtained from the ENT =␬Si3N4/␬ZrON⫻tZrON, where the␬Si3N4,␬ZrON, and tZrONare the dielectric constant of Si₃N₄, dielectric constant of ZrON, and the thickness of ZrON, respectively. The concentration of implanted As decreases rapidly before entering the double tunnel layer of LaAlO3-SiO2. Such low energy tilted-angle As+_{implantation is important to reduce the damage to tunnel} oxide layer.

Figure 3 shows the x-ray diffraction 共XRD兲 spectra of ZrON–关LaAlO3– SiO2兴–Si structure with and without As+ implantation. The strong diffraction peaks indicate the good ZrON crystallinity that is important to provide higher ␬ ⬃35 共Refs.22 and23兲 with a smaller ENT of 3.6 nm.

Be-sides, extra weak As peaks were also found in As+-implanted

and 950 ° C-annealed ZrON, with the same angles of clus-tered As-dots in As-rich GaAs.24This suggests the possibility to form the deep energy levels in ZrON due to large As work-function of 5.1 eV,25 which also explains the larger hysteresis shown in Fig. 1.

Data retention is one of the most importance parameters for NVM. Figure 4 shows the retention characteristics at 85 ° C. Under ⫾16 V and 100 ␮s P/E, the As+_-implanted ZrON devices have a larger initial memory window of 4.9 V than the 2.9 V data of control device without As+ implanta-tion, suggesting the higher trap density in As+_-implanted ZrON trapping layer. The very fast 100 ␮s P/E speed is due to the additional conduction and valance band disconti-nuity 共⌬EC and⌬EV兲 between LaAlO3 and SiO2, for easier electron and hole tunneling during program and erase, re-spectively. Still large ten-year extrapolated memory window of 3.4 V was obtained for As+_{-implanted ZrON CTF device} and better than that of control device. The good retention is due to the physically thicker double LaAlO3– SiO2for carrier confinement, while the ⌬EC and ⌬EV in LaAlO3/SiO2 im-prove the program and erase speed. This large ten-year re-tention window with a small 3.6 nm ENT trapping layer also allows multilevel cell storage at 85 ° C.15

In summary, we have used both higher␬ ZrON and As+ implantation to improve the device performance of MONOS CTF device. At record smallest 3.6 nm ENT, large 4.9 V initial memory window and good retention of 3.4 V ten-year extrapolated window at 85 ° C were measured in this CTF

0 400 800 1200 1600 2000 2400 101 102 103 104 105 106 107 Int ens ity (c o u nt s) Time (sec) O Al As (b) (a)

FIG. 2. 共Color online兲共a兲. Cross-sectional TEM and 共b兲 SIMS of ZrON–关LaAlO3– SiO2兴–Si structure with As+implantation.

20 30 40 50 60 70 0 100 200 300 400 As(003) ZrO₂(220) ZrO 2(103) As(012) ZrO 2(200) ZrO₂(111)

control un-implanted ZrON As+-implanted ZrON Int ens ity (co u nt s ) 2 (degree)

FIG. 3. 共Color online兲 XRD of ZrON–关LaAlO3– SiO2兴–Si structure with

and without As+_{implantation.}

100 102 104 106 108 -3 -2 -1 0 1 2 3 4 5 P/E: 16V 100s As+-implanted un-implanted _2.1V 2.9V 3.4V 85o C 4.9V 85o C 10 years Vth (V ) Time (sec)

FIG. 4. Retention characteristics of ZrON MONOS CTF devices at 85 ° C with and without As+_{implantation.}

213504-2 Tsai et al. Appl. Phys. Lett. 97, 213504共2010兲

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device, under very fast 100 ␮s speed and low P/E voltage of ⫾16 V.

The paper publication was supported by National Sci-ence Council of Taiwan under Project No. NSC99–2120–M-009–002

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