High-Frequency Characteristic Fluctuations of
Nano-MOSFET Circuit Induced by Random Dopants
Yiming Li, Member, IEEE, and Chih-Hong Hwang
Abstract—As the dimension of semiconductor device shrunk into nanometer scale (nanoscale), characteristic fluctuation is more pronounced, and become crucial for circuit design. In this paper, discrete-dopant-induced characteristic fluctuation of 16-nm-gate metal–oxide–semiconductor field effect transistors (MOSFET) circuit under high-frequency regime is quantitatively studied. The circuit gain, the 3 dB bandwidth and the unity-gain bandwidth of the tested nanoscale transistor circuit are calculated concurrently capturing the dopant-number- and discrete-dopant-position-induced fluctuations in the large-scale statisti-cally sound “atomistic” device/circuit coupled simulation. For the 16-nm-gate MOSFET circuit, the number of discrete dopants, varying from zero to 14, may result in 5.7% variation of the circuit gain, 14.1% variation of the 3 dB bandwidth, and 10.4% variation of the unity-gain bandwidth. To suppress the high-frequency characteristic fluctuations, an improved doping distribution along the longitudinal diffusion direction from the MOSFET’s surface to substrate is further performed to examine the associated fluc-tuation. The improved vertical doping profile with less dopants locating near surface of channel effectively reduces the fluctua-tions of the circuit gain, the 3 dB bandwidth and the unity-gain bandwidth dramatically. Compared with the original doping profile, the reduction is 32.3%, 19.4% and 51.8%, respectively. This study provides an insight into random-dopant-induced in-trinsic high-frequency characteristic fluctuations and verifies the potential fluctuation suppression technique on high-frequency characteristic fluctuations of nanoscale transistor circuit.
Index Terms—Characteristic fluctuation, fluctuation sup-pression technique, high frequency, modeling and simulation, nanometer scale metal–oxide–semiconductor field effect transis-tors (MOSFET) device and circuit, random dopant effect.
I. INTRODUCTION
S
ILICON-BASED devices are scaled down continually in order to increase density and speed. The gate lengths of scaled metal–oxide–semiconductor field effect transis-tors (MOSFETs) have been the sub-30 nm for 45 nm node high-performance circuit design [1]. Moreover, the devices with sub-10-nm-gate lengths have been currently investigated [2]–[5]. For the RF/mixed-signal applications, a cutoff fre-quency higher than 200 GHz have been also reported [6], [7].Manuscript received January 24, 2008; revised July 05, 2008. First published November 18, 2008; current version published December 05, 2008. This work was supported by the Taiwan National Science Council (NSC) under Contract NSC-97-2221-E-009-154-MY2, Contract NSC-96-2221-E-009-210, and Con-tract NSC-96-2752-E-009-003- PAE, and by the Taiwan Semiconductor Manu-facturing Company, Hsinchu, Taiwan, under a 2007–2009 grant.
The authors are with the Department of Communication Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan (e-mail: [email protected]; [email protected]).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2008.2007077
Yield analysis and optimization, which take into account the manufacturing tolerances, model uncertainties, variations in the process parameters, etc., are known as indispensable com-ponents of the circuit design methodology [8]–[12]. However, attention is seldom drawn to the existence of high-frequency characteristic fluctuations of active device due to random dopant placement. With device scaling, various randomness effects resulting from the random nature of manufacturing process, such as ion implantation, diffusion, and thermal an-nealing [13], have induced significant fluctuations of electrical characteristics in nanometer scale (nanoscale) MOSFETs. The number of dopants is of the order of tens in the depletion region of a nanoscale MOSFET, whose influence on device characteristic is large enough to be distinct [14].
Various random dopant effects have been recently studied in both experimental and theoretical approaches [14]–[35]. Fluctu-ations of characteristics are caused not only by a variation in an average doping density, which is associated with a fluctuation in the number of impurities, but also with a particular random dis-tribution of impurities in the channel region. Diverse approaches have recently been reported to study fluctuation-related issues in semiconductor devices [19]–[31] and circuit [32]–[35]. Un-fortunately, the effect of the discrete dopants induced high-fre-quency characteristic fluctuations on nanoscale MOSFET cir-cuit has not been well investigated yet. In this work, a statisti-cally sound “atomistic” device/circuit mixed-mode simulation approach is thus employed to analyze the discrete-dopant-in-duced high-frequency characteristic fluctuations in nanoscale MOSFET circuit, concurrently capturing “dopant concentration variation” and “dopant position fluctuation”. The statistically generated large-scale doping profiles are similar to the phys-ical process of ion implantation and thermal annealing [36]. Based on the statistically (totally randomly) generated large-scale doping profiles, device simulation is performed by solving a set of 3-D drift-diffusion equations with quantum corrections by the density gradient method [37]–[40], which is conducted using a parallel computing system [41]–[43]. In estimation of the high-frequency characteristic fluctuation, for obtaining more physical insight device and pursuing higher accuracy [44], a de-vice/circuit coupled simulation [45]–[47] with discrete dopant distribution is conducted to examine the associated high fre-quency characteristic fluctuations of circuit, which concurrently considers the discrete-dopant-number- and discrete-dopant-po-sition-induced fluctuations. We notice that the accuracy of de-veloped analyzing technique has been quantitatively verified in the experimentally measured characteristics of sub-20 nm de-vices [21]–[25].
Channel engineering technique has been known to be an effective way to suppress the random-dopant-induced charac-teristic fluctuation [18], [24], [27]. However, these studies are focus on the effectiveness of the suppression of dc character-istic fluctuations. Suppression techniques for high-frequency characteristic fluctuation are still lack for nanoscale MOSFET circuit. Therefore, to examine the fluctuation suppression on the high-frequency characteristic fluctuations of the explored nanoscale MOSFET circuit, an improved vertical doping profile along the longitudinal diffusion direction from the device’s surface to substrate is implemented. We thus calculate the fluctuations of the circuit gain, the 3 dB bandwidth, and the unity-gain bandwidth [48] of the tested circuit, and compare with the results before the improvement. Our comprehensive results show that the number of discrete dopants, varying from zero to 14, in the 16 nm MOSFET circuit, may result in 5.7% variation of the circuit gain, 14.1% variation of the 3 dB bandwidth, and 10.4% variation of the unity-gain bandwidth. For the aforementioned doping profile with less dopants lo-cating near surface of channel, the fluctuations of the threshold voltage, the circuit gain, the 3 dB bandwidth, and the unity-gain bandwidth are simultaneously reduced 14.2%, 32.3%, 19.4%, and 51.8%. Intrinsic high-frequency characteristic fluctuations of the nanoscale transistor circuit induced by random dopants and the effectiveness of fluctuation suppression technique are thus intensively explored.
This paper is organized as follows. In Section II, we intro-duce the analyzing technique for studying the random dopants effect in nanoscale device and circuit. In Section III, we ex-amine the discrete-dopant-induced characteristic fluctuations of the 16 nm device and circuit. Both dc and high-frequency char-acteristics are discussed, where the suppression technique for high-frequency characteristic fluctuations is also performed. Fi-nally, we draw conclusions and suggestion future work.
II. NANO-MOSFET CIRCUIT ANDSIMULATIONTECHNIQUE
The nominal channel doping concentration of these devices is 1.48 10 cm . They have a 16 nm gate, a gate oxide thickness of 1.2 nm, and a workfunction of 4.4 eV. Outside the channel, the doping concentrations in the source/drain and back-ground are 1.1 10 cm and 1 10 cm , respectively. For the channel region, to consider the effect of random fluctuation of the number and location of discrete channel dopants, 758 dopants are firstly randomly generated in an 80 nm cube, in which the equivalent doping concentration is 1.48 10 cm , as shown in Fig. 1(a). The 80 nm cube is then partitioned into 125 sub cubes of 16 nm . The number of dopants may vary from zero to 14, and the average number is six, as shown in Fig. 1(b), (c), and (d), respectively. These 125 sub cubes are then equivalently mapped into the channel region of the device for the 3-D device simulation with discrete dopants, as shown in Fig. 1(e). The common-source circuit with sinusoid input wave (offset is equal to 0.5 V), shown in Fig. 1(f), is used as a tested circuit to explore the fluctuation of high-frequency characteristics. All statistically generated discrete dopants, shown in Fig. 1, are incorporated into the large-scale 3-D device/circuit mixed-mode simulation which
Fig. 1. (a) Discrete dopants randomly distributed in the 80 nm cube with the average concentration of 1.482 1018 cm . There will be 758 dopants within the cube, but dopants may vary from zero to 14 (the average number is six) within its 125 sub cubes of 16 nm [(b), (c), and (d)]. The 125 sub cubes are equivalently mapped into channel region for dopant position/number- sensitive device simulation and device/circuit coupled simulation as shown in (e) and (f).
is conducted in our parallel computing system [19], [40]. The device simulation is performed by solving a set of 3-D den-sity-gradient equation coupling with Poisson equation as well as electron-hole current continuity equations [37]–[40]. There is no well-established device compact model for such ultrasmall nanoscale devices and to include the nonquasi static behavior of charge particle, so a 3-D quantum mechanical simulation of the device coupling with circuit equation is employed [19], [45]. The circuit nodal equations of the tested circuit are formulated and directly coupled with aforementioned device equations for device/circuit mixed-mode simulation. The time-domain simulation results are simultaneously used for the calculation of the property of the frequency response, where the frequency is sweep from 1 10 Hz to 1 10 Hz. We notice that the device mobility and characteristic fluctuation has been validated with the experimentally measured dc baseband data [21]–[25].
To examine the effectiveness of the channel engineering tech-nique in both nanoscale device and circuit, along the longitu-dinal diffusion direction from surface to substrate, an improved vertical doping profile with less dopants locating near surface
Fig. 2. There will be 758 dopants within a large rectangular solid, in which the equivalent doping concentration is 1.482 1018 cm . The dopant distribution in the direction of channel depth, the arrow line in Fig. 1(e), follows the normal distribution (b). Partitioned cubes are equivalently mapped into channel region for dopant position/number-sensitive device simulation and device/circuit cou-pled simulation, as shown in (c). Similarly, dopants within the 16 nm cubes may vary from zero to 14 (the average number is six) (d). The vertical dopant distribution of the improved and the original doping profile, which is generated from Fig. 1, are shown in (e) and (f).
of channel [18], [24], [27]–[29] is further implemented. 758 dopants are firstly randomly generated in a large rectangular solid ( , , : 16 2000 16 nm), in which the equivalent doping concentration is 1.48 10 cm , as shown in Fig. 2(a). The distribution of the generated dopants’ position in the -di-rection follows the normal distribution, as shown in Fig. 2(b). Both the mean position and the three sigma of this distribution are eight nanometers, which can be controlled by the manufac-turing processes of ion implementation and thermal annealing [36]. The inset of Fig. 2(b) shows the nominal case of the im-proved vertical doping profile, where the darker region indicates the higher doping concentration. The large rectangular solid is then partitioned into 125 sub cubes of 16 nm cube and mapped into device channel for discrete dopant and device/circuit cou-pled mixed-mode simulation, as shown in Fig. 2(c). The number of dopants may vary from zero to 14, and the average number is six, as shown in Fig. 2(d). The longitudinal dopant distribution of the improved and the original doping profile, which is gen-erated from Fig. 1, are studied in Fig. 2(e) and (f), respectively. The inset of Fig. 2(f) shows the distribution of doping concen-tration for the original doping profile. Since the position of dis-crete dopants generated in Fig. 1 is random in each direction,
Fig. 3. DC characteristic fluctuations of: (a)V , (b) I , (c) g , and (d)r of the 125 discrete dopant fluctuated 16-nm-gate planar MOSFET.
the distribution of dopant number in channel depth is uniform. We notice that the threshold voltages of the nominal devices for both the improved and original doping profiles, whose channel doping profile is continuously doped with 1.48 10 cm , are adjusted to be the same value 140 mV. Result shows that numbers of dopant appearing near the channel surface for the improved doping profile is significant less than that of the orig-inal doping profile, and thus may induce less surface potential fluctuation than the other.
III. RESULTS ANDDISCUSSION
In this section we first discuss the high-frequency character-istic fluctuations induced by discrete dopant through the char-acteristic fluctuation of device viewpoint. Then the improved doping profile technique is quantitatively calculated to examine the associated fluctuation suppression in both dc and high-fre-quency characteristic fluctuations.
Fig. 3 shows the dc characteristic fluctuations of the 125 discrete dopant fluctuated 16 nm planar MOSFETs. From the random-dopant-number point of view, the equivalent channel doping concentration is increased when the dopant number in-creases, which substantially alters the threshold voltage ,
off-state currents , maximum transconductance ,
and output resistance of transistor , shown in Fig. 3(a)–(d), respectively. The threshold voltage is determined from a current criterion that the drain current larger than W/L ampere. An expression of and the output resistance of transistor are shown in insets of Fig. 3(c) and (d). As the number of dopants in channel is increased, the device’s is increased and thus decreases the off-state current. Since the threshold voltage is increased with increasing channel doping concentra-tion, according to the definition in insets of Fig. 3(c) and (d), is decreased and is increased as the number of dopants is increased. The position of random dopants induced different fluctuation of characteristics in spite of the same number of dopants. Furthermore, the magnitude of the spread characteristics increases as the number of dopants increases.
Fig. 4. Fluctuations ofC for the 125 discrete dopant fluctuated 16-nm-gate planar MOSFET. The left plot is for the cases of the number of dopants equal or less than six, the average number whose equivalent channel doping concen-tration is 1.482 1018 cm , and the right one is for the cases of the number of dopants larger than six.
The detailed physical mechanism is described somewhere else [21]–[25].
The fluctuation of gate capacitance , as shown in Fig. 4, indicates that the maximum variation of gate capacitance is dominated by the number of discrete dopants. For cases with number of dopants in device channel larger than six, the average number whose equivalent channel doping concen-tration is 1.48 10 cm , the maximum variation of under 0.5 V gate voltage is about 0.00143 fF, which is about 3.5 times larger than other cases with number of dopants in channel equal or less than six. The magnitude of fluctuation is increased as number of dopants is increased. Therefore, as expected, the device characteristic is much more scattered as the number of dopants is increased, as shown in Fig. 3. Therefore, we can infer a larger high-frequency characteristic fluctuation induced by larger numbers of dopant in the nano-MOSFET circuit.
Fig. 5(a) shows the circuit gain versus operation frequency for all fluctuated cases, where the solid line shows the nom-inal case, whose channel doping profile is continuously doped with 1.48 10 cm . The circuit gain, 3 dB bandwidth, and unity-gain bandwidth of the nominal case are 8.14 dB, 68 GHz, and 281 GHz, respectively. The corresponding high-frequency characteristic fluctuations for the explore circuit are explored, as shown in Fig. 5(b)–(d), where the insets show the trend of circuit gain, 3 dB bandwidth, and unity-gain bandwidth as a function of device characteristic and circuit element. The gain of the studied circuit is proportional to transconductance multiplied by output resistance of circuit. The circuit output resistance is given by
(1) where and are the output current and voltage of the studied circuit. As the number of dopants in device channel is increased, the on-state current of transistor, which associated with the output current of the test circuit, is decreased and thus
Fig. 5. (a) High frequency response of the 125 discrete dopant fluctuated 16-nm-gate planar MOSFET, where the black line indicates the nominal case and dashed lines are the discrete dopant fluctuated cases. (b) Gain, (c) 3 dB bandwidth, and (d) unity-gain bandwidth fluctuations of the 125 discrete dopant fluctuated 16-nm-gate planar MOSFET circuit.
increases the output voltage of the circuit. Additionally, the output resistance of transistor, , is increased with increasing threshold voltage. Therefore, the circuit output resistance, , is increased as threshold voltage is increased. We notice that although the dependence of and on threshold voltage is opposed, the trend of circuit gain fluctuation is dominated the output resistance due to the square dependence of on . Therefore, the trend of circuit gain fluctuation is dominated by the output resistance and increased as number of dopant is increased, as shown in Fig. 5(b). Fig. 5(c) and (d) show the fluctuation of 3 dB bandwidth and the unity-gain bandwidth of the nano-MOSFET circuit, which indicate the variations of switching speed nano-MOSFET circuit resulted from random discrete dopants. The insets of Fig. 5(c) and (d) show the main sources of variations contributed from device characteristics fluctuations, , , and , as shown in Figs. 3(c) and (d) and 4. As the number of dopant in device channel is increased, the depletion width is decreased, and then increases the gate ca-pacitance. The fluctuation of accompanied with increasing and decreasing result in a decrement of 3 dB bandwidth and the unity-gain bandwidth on increasing dopant number. Similar to the dc characteristic of device, the high-frequency characteristic fluctuation of the nanoscale MOSFET circuit is much more scattered as number of dopants is increased. The standard deviations of the gain, 3 dB bandwidth, unity-gain bandwidth, and gain-bandwidth product are 0.46 dB, 9.63 GHz, 29.3 GHz, and 64.4 GHz, respectively. The high-frequency characteristic fluctuations of the tested circuit are summarized in Table I.
To evaluate the fluctuation suppression technique [18], [24], [27] on high-frequency characteristic fluctuations of the nanoscale MOSFET circuit, an improved vertical doping profile is implemented, where both the mean position and the three sigma of the vertical doping profile are eight nanometers. The
TABLE I
SUMMARIZEDHIGH-FREQUENCYCHARACTERISTIC
FLUCTUATIONS OF THENANO-MOSFET CIRCUIT
discrete dopants locating near the channel surface may substan-tially alter the surface potential and then disturb the distribution of electric field and current conducting path. The characteristic of device is significantly perturbed by both number and position of discrete impurities [21]–[25]. The mechanism of channel engineering is to reduce the probability of dopants appearing at channel region by introducing a lightly channel doping near the surface. Moreover, the holes in the heavily doped region, the mean position of the vertical doping profile, start to screen the charge of the discrete random acceptors in the depletion layer, reducing their effect on the threshold voltage fluctuation. Any further increase of doping concentration in the heavily doped region reduces further the width of the depletion layer and enhances the screening [27]. Fig. 6(a) shows the char-acteristics of the discrete dopant fluctuated device generated from the improved (dashed lines) and the original (solid lines) doping profiles. The spreading range of the improved doping profile is reduced and indicates a suppression of fluctuation on dc characteristic of device. The fluctuation of the threshold voltage is shown in Fig. 6(b), where the square symbol indi-cates the cases of the improved doping profile and the “ ” symbols symbol shows the cases of original doping profile. The scattering range of the threshold voltage is significantly suppressed, and the fluctuation of threshold voltage is reduced from 58.5 mV to 50.2 mV. Fig. 6(c)–(e) show the fluctuations of the on-state current , and maximum transconductance , respectively. As expected, the fluctuation of on-state current and maximum transconductance is effectively sup-pressed due to the less dopant locating near the channel surface. However, the fluctuation of off-state current can not be further suppressed due to the similar numbers of dopant locating near the path of leakage current (about 4 nm below the gate oxide). This result implies the importance of the vertical doping profile optimization.
Fig. 7(a) shows the gate capacitance fluctuation of the studied doping profiles, where the dashed and solid lines show the im-proved and the original doping profile, respectively. The fluctu-ation of gate capacitance is suppressed by 16.4%. The screening effect in the heavily doped region screens the charge of the dis-crete random acceptors in the thin depletion layer, and reduces their effect on the gate capacitance fluctuation. The suppressed fluctuation of gate capacitance and dc characteristic of device implies the effectiveness of the fluctuation suppression tech-nique on the high-frequency characteristics. The high-frequency response of the nanoscale MOSFET circuit is shown in Fig. 7(b). As expected, the spreading range of the improved doping profile is reduced through the improvement of doping profile. The fluc-tuation of the high-frequency characteristics, the circuit gain, the
Fig. 6. Fluctuations of: (a)I 0V , (b) V , (c) I , (d) I , and (e) (g ) of the 125 discrete dopant fluctuated 16-nm-gate planar MOSFETs, where the square and “2” indicate the cases of the improved and original doping distribu-tions, respectively.
Fig. 7. Comparison of gate capacitance and frequency response fluctuations of the discrete dopant fluctuated 16-nm-gate cases generated from the improved (dashed line) and original (solid line) doping distributions.
3 dB bandwidth and the unity-gain bandwidth of the nanoscale MOSFET circuit are calculated; as shown in Fig. 8(a)–(c), the square and “ ” symbols indicate the cases of the improved and original doping distributions. The effectiveness of fluctuation suppression technique in nanoscale device and circuit is sum-marized in Fig. 9. The fluctuation suppressions of the character-istics of the nanoscale device circuit are more pronounced than that of device due to the second-order nonlinear effect of cir-cuit characteristics. The fluctuation suppression of the high fre-quency characteristics is resulted from less dc characteristic and gate capacitance fluctuation of device by introducing a doping profile of Gaussian distribution along the longitudinal direction from surface to substrate. The result confirms the fluctuation suppression technique on high-frequency characteristic fluctu-ation of nanoscale device circuit and show the effectiveness of
Fig. 8. Comparison of: (a) gain, (b) 3 dB bandwidth, and (c) unity-gain bandwidth fluctuations of the 125 discrete dopant fluctuated 16-nm-gate planar MOSFET circuit with the improved (squares) and original (“2”) doping profiles.
Fig. 9. Effectiveness of fluctuation suppression technique in both the nanoscale device and circuit.
TABLE II
COMPARISON OFHIGH-FREQUENCYCHARACTERISTICFLUCTUATIONS FOR
DEVICESWITHORIGINAL ANDIMPROVEDDOPINGPROFILE
fluctuation suppression technique. The comparison of charac-teristic fluctuations for devices without and with doping profile improvement is summarized in Table II.
IV. CONCLUSIONS
In this paper, both the discrete-dopant-induced dc and high-frequency characteristics fluctuations of 16-nm-gate MOSFET
circuit have been studied using a 3-D “atomistic” simulation technique. Using the experimentally calibrated analyzing tech-nique, the result have shown that the discrete-dopant fluctu-ated 16 nm MOSFET circuit exhibits 5.7% variation of the cir-cuit gain, 14.1% variation of the 3 dB bandwidth and 10.4% variation of the unity-gain bandwidth. Without loss the device and circuit performance, by considering a doping profile with less dopants locating near surface of channel, the suppression technique on high-frequency characteristic fluctuations of the nanoscale transistor circuit have also shown its effectiveness. The improved doping profile significantly reduces the intrinsic characteristic fluctuation in the device level, and thus suppressed fluctuations of the tested circuit gain, the 3 dB bandwidth and the unity-gain bandwidth, and the reductions are 32.3%, 19.4%, and 51.8%, respectively. Experimental and theoretical verifica-tion will benefit the development of high-frequency 16-nm-gate MOSFET circuit; an experiment is thus currently under con-ducting to design, fabricate and measure the high-frequency characteristic fluctuations of the nanoscale device circuit.
We notice that the parasitic effects may play very important role in determining the overall high frequency performance in nanoscale transistor. Therefore, we have included the effects of the gate to source/drain overlap capacitance and the inner fringing capacitance in our modeling and simulation. Ac-cording to the 2007 ITRS roadmap, the ideal gate capacitance per micron device width in inversion is about 0.671 fF m. The total gate capacitance per micron device width in inversion including the parasitic gate overlap/fringing capacitance per micron device width [including the Miller effect] is about 0.835 fF/ m Therefore, the parasitic gate overlap/fringing ca-pacitance is about 20%
of the total gate capacitance. Besides the ITRS roadmap, ac-cording to [49], the effective fringing capacitance of state-of-art MOSFET is about 0.55 fF m and independent of the tech-nology node, where the outer fringing capacitance is about 0.13 fF m. Compare it with the total gate capacitance of 0.68 fF m, the outer fringing capacitance is about 16% of the total gate capacitance. We believe that our simulation approach can reflect the dominating factor on RF performance. To include the parasitic effect in nanoscale transistors’ circuit, a 3-D field simulation coupling with device and circuit simulation could be considered.
There are some practical and theoretical issues that worth to be addressed in our future work, such as the performance parameter fluctuations of high frequency characteristics, cali-bration of high-frequency measurement data, high-frequency circuit (e.g., LNA, mixer, etc) simulation, parasitic capaci-tance of nano-device, and modeling of device variability. This study is mainly based upon a large-scale statistically sound “atomistic” device and circuit coupled simulation methodology in time-domain for discrete-dopant-fluctuated nano-CMOS circuits. We are currently formulating the mathematical models and implementing this methodology in frequency domain together with harmonic balance technique, which will directly benefit the characteristic estimation using the frequency domain results, such as the calculation of -parameters. For the design and optimization of high-frequency devices and circuits, the numerical simulation is the first step toward the modeling of
device variability and the development of compact modeling for capturing device variability is urgent.
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Yiming Li (M’02) received the B.S. degrees in
ap-plied mathematics and electronics engineering, M.S. degree in applied mathematics, and Ph.D. degree in electronics from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 1996, 1998, and 2001, respectively.
In 2001, he joined the National Nano Device Laboratories (NDL), Taiwan, as an Associate Researcher, and the Microelectronics and Informa-tion Systems Research Center (MISRC), NaInforma-tional Chiao Tung University (NCTU), as an Assistant Professor, where he has been engaged in the field of computational science and engineering, particularly in modeling, simulation, and optimization of nanoelectronics and very large scale integration (VLSI) circuits. In Fall 2002,
he was a Visiting Assistant Professor with the Department of Electrical and Computer Engineering, University of Massachusetts at Amherst. From 2003 to 2004, he was the Research Consultant of the System on a Chip (SOC) Technology Center, Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan. From 2003 to 2005, he was the Director of the Departments of Nan-odevice and Computational Nanoelectronics, NDL, and an Associate Professor with the MISRC, NCTU, Since Fall 2004, he has been an Associate Professor with the Department of Communication Engineering, NCTU. He is the Deputy Director of the Modeling and Simulation Center, NCTU, and conducts the Parallel and Scientific Computing Laboratory, NCTU. He has authored or coauthored over 120 research papers appearing in international book chapters, journals, and conferences. He has served as a reviewer, guest associate editor, guest editor, associate editor, and editor for many international journals. His current research areas include computational electronics and physics, physics of semiconductor nanostructures, device modeling, parameter extraction, and VLSI circuit simulation, development of technology computer-aided design (TCAD) and electronic CAD (ECAD) tools and SOC applications, bioinformatics and computational biology, and advanced numerical methods, parallel and scientific computing, optimization techniques, and computational intelligence. He is included in Who’s Who in the World.
Dr. Li is a member of Phi Tau Phi, Sigma Xi, the American Physical Society, the American Chemical Society, the Association for Computing Machinery, the Institute of Electronics, Information and Communication Engineers (IEICE), Japan, and the Society for Industrial and Applied Mathematics. He has organized and served on several international conferences and was an editor for the proceedings of international conferences. He has served as a reviewer for the IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, the IEEE TRANSACTIONS ONNANOTECHNOLOGY, the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, the IEEE TRANSACTIONS ON
COMPUTER-AIDEDDESIGN OFINTEGRATEDCIRCUITS ANDSYSTEMS, the IEEE ELECTRON DEVICE LETTERS, and the IEEE TRANSACTIONS ON ELECTRON
DEVICES. He was the recipient of the 2002 Research Fellowship Award presented by the Pan Wen-Yuan Foundation, Taiwan, and the 2006 Outstanding Young Electrical Engineer Award presented by the Chinese Institute of Elec-trical Engineering, Taiwan.
Chih-Hong Hwang received the B.S. degree in
engi-neering and system science and M.S. degree in elec-tronics engineering from National Tsing Hua Univer-sity, Hsinchu, Taiwan, in 2001 and 2003, respectively, and is currently working toward the Ph.D. degree at National Chiao Tung University, Hsinchu, Taiwan.
He is currently with the Parallel and Scientific Computing Laboratory, Department of Communica-tion Engineering, NaCommunica-tional Chiao Tung University. His research interests focus on the modeling and simulation of semiconductor nanodevices and vari-ability of nanodevices and circuits.
