先進互補式金氧半電晶體及快閃式記憶元件中單一電荷效應之統計性研究

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國立交通大學

電子工程學系電子研究所

博士論文

先進互補式金氧半電晶體及快閃式記憶元件中單

一電荷效應之統計性研究

Statistical Study of Single Charge Phenomena in

Advanced CMOS and Flash Memory

研究生：邱榮標

指導教授：汪大暉教授

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先進互補式金氧半電晶體及快閃式記憶元件中單一電荷效

應之統計性研究

Statistical Study of Single Charge Phenomena in Advanced

CMOS and Flash Memory

研究生：邱榮標 Student：Jung-Piao Chiu

指導教授：汪大暉 Advisor：Tahui Wang

國立交通大學

電子工程學系電子研究所

博士論文

A Dissertation

Submitted to Department of Electronics Engineering and Institute of Electronics

College of Electrical and Computer Engineering National Chiao Tung University

in Partial Fulfillment of the Requirements for the Degree of

Doctor of Philosophy in

Electronics Engineering February 2013

Hsinchu, Taiwan, Republic of China

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先進互補式金氧半電晶體及快閃式記憶元件中單一電荷效應之統計性研究

學生：邱榮標

指導教授：汪大暉博士

國立交通大學電子工程學系電子研究所

摘

要

本篇論文主要著重在單電子效應於先進互補式金氧半電晶體 (advanced

CMOS)及快閃式記憶元件(flash memory)之應用。高介電閘極氧化層(high-k)之可

靠性議題，如電壓溫度引致不穩定(BTI)、隨機電報雜訊(RTN)之研究，亦有所探

討。更利用蒙地卡羅模擬進一步驗證理論及實驗。

第一章首先描述本論文中單電子效應之應用研究成果。首先探討高介電閘極

材料(high-k)金氧半電晶體元件中，藉由量測 NBTI 加速測試中，單一電荷捕捉及

釋放所造成的臨界電壓及特徵時間變化，進一步探討在奈米級元件的可靠性議

題。接下來吾人討論於 pMOSFET 中，同為單電子效應之 RTN 及 NBTI 的異同，

並利用 reaction-diffusion(RD)模型及蒙地卡羅方法模擬 NBTI 缺陷之產生。此外，

吾人於此篇論文最後，討論於快閃式記憶元件中寫入載子對於 RTN 之影響，主

要探討浮動閘極(floating gate)、平面(planar)及鰭狀(FinFET)氮化矽(SONOS)快閃

式記憶元件中，載子寫入前後 RTN 之變化。

在第二章中，吾人探討了在小面積 high-k 元件中，NBTI 造成之總臨界電壓

變化(



V

t

)分佈及其形成原因。吾人量測大量小面積元件之單電荷產生特徵時間及

其造成之臨界電壓變化。吾人發現單電荷產生之特徵時間有數 decade 之廣，並

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提出用 reaction-diffusion(RD)模型中之反應活化能角度詮釋此一現象，更進一步

由特徵時間分佈萃取出反應活化能分佈。最後吾人提出一統計模型，此模型基於

RD 模型之基礎加入反應活化能分佈及單電荷造成之臨界電壓變化分佈。最後以

蒙地卡羅模擬重現實驗



V

t

分佈及其和 NBTI 操作時間的關係。

第三章延續第二章之主題，探討小面積 high-k 元件中，NBTI 造成之總臨界

電壓變化(



V

t

)分佈及其形成原因。不同於其他可靠度議題，NBTI 在操作電壓移

除後有一特殊之回復現象。利用類似前一章的方法，吾人量測大量小面積元件之

單電荷逸散特徵時間及其造成之臨界電壓變化。吾人以「熱助穿隧」模型解釋，

並由缺陷能量分佈、空間分佈及反應活化能分佈進一步探討並萃取反應活化能分

佈。最後提出一統計模型，以熱助穿隧模型為基礎加上反應活化能分佈，完整解

釋並預測回復現象造成之



V

t

分佈及其和回復時間之關係。

單電子效應的應用除了 NBTI 之外，另一個重要的可靠度議題就是 RTN。這

兩種現象之機制確有相似之處，近年來甚至有人認為 NBTI 是 RTN 在特殊偏壓

條件下的產物。在第四章，吾人量測並比較製程產生之 RTN 缺陷(fresh RTN)、

NBTI 操作產生之 RTN 缺陷(post-NBTI stress RTN)、NBT 測試過程中之單電荷引

致臨界電壓變化，結果發現 NBTI 測試過程中之平均單電荷引致臨界電壓變化量

大於製程產生之缺陷。為此吾人用 RD 模型進行 3D 模擬，結果顯示因為 NBTI

測試產生之缺陷位置較容易出現在主要電流滲透路徑，進而產生較大之單電荷引

致臨界電壓變化。也間接證明 NBTI 之缺陷為新產生之缺陷，和製程產生之 RTN

缺陷不同。

在第五章中，吾人探討 SONOS 元件的寫入電荷對於 RTN 引致臨界電壓變化

量的影響。吾人量測並模擬 RTN 在浮動式閘極(floating gate)、平面式 SONOS、

鰭式 SONOS 之振幅大小，並記錄其在寫入/抹除前後的變化。研究發現 RTN 在

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平面式 SONOS 寫入/抹除前後有大量的變化，而浮動式閘極幾乎在寫入/抹除前

後擁有同樣大小之 RTN。主要是因為 SONOS 中氮化矽層儲存之電荷為一離散的

狀態，使寫入/抹除前後之電流滲透路徑改變，而浮動式閘極因為電荷儲存層為

導體，故 RTN 之大小不會因為寫入/抹除動作而有變化。最後吾人發現當 SONOS

由平面式結構進入鰭式結構，RTN 在寫入/抹除前後之變化量會被大幅度的壓

抑，主要是因為電流導通路徑的限縮，及高度之對稱性使得寫入電荷對於電流導

通路徑擁有等量的影響。

在第六章中，吾人研究了 nanowire-like 結構中的 RTN 振幅。在較寬的通道

寬度元件中，電流導通路徑主要由隨機參雜決定，RTN 振幅也由缺陷位置和電

流滲透路徑決定。但在 nanowire-like 結構，電流路徑被侷限於一個一維的通道，

一個參雜僅能改變區域導通瓶頸(導電率)，而無法改變導通路徑。在本章中，吾

人嘗試提出一個模型來描述 nanowire-like 結構的 RTN 振幅分佈。模型顯示 RTN

振幅的機率分佈遵守 Poisson 分佈，吾人亦利用蒙地卡羅模擬來證實理論。此外，

如上一章提到的，由於在 SONOS 元件中寫入載子和通道參雜對於電流滲透路徑

有一些類似的特性，此一理論亦可延伸並用於未來 nanowire-like 結構的 SONOS

快閃式記憶元件。

最後於第七章，吾人將對本論文做個總結。

關鍵字：蒙地卡羅模擬，先進互補式金氧半電晶體，氮化矽快閃式記憶元件，浮

動式閘極快閃式記憶元件，高介電閘極氧化層，負電壓溫度引致不穩

定，隨機電報雜訊，反應-擴散模型，熱助穿隧模型，單電荷產生，單

電荷散逸，反應活化能萃取，缺陷位置萃取，電流通道滲透效應，布瓦

松分佈

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Statistical Study of Single Charge Phenomena in Advanced CMOS and

Flash Memory

Student：Jung-Piao Chiu

Advisor：Dr. Tahui Wang

Department of Electronics Engineering & Institute of Electronics

National Chiao Tung University

ABSTRACT

This thesis will focus on single charge phenomena characterization and its

applications to advanced CMOS and non-volatile flash memory. The reliability issues,

such as negative bias temperature instability (NBTI) and random telegraph noise

(RTN) in advanced gate dielectric (high-k), are studied statistically. Monte Carlo

simulations are also performed to corroborate our model and experiment data.

In Chapter 1, applications of single charge phenomena statistics are firstly

addressed. The second and the third chapters are the investigations of threshold

voltage shifts arise from NBTI stress and post-NBTI recovery, respectively. And the

fourth chapter is the study of NBTI and RTN amplitude distributions in high-k gate

dielectric pMOSFETs. The program charge effect on RTN amplitude and its device

structural dependence in SONOS flash memory is investigated in Chapter 5. Finally,

an RTN amplitude distribution model is proposed in Chapter 6.

In Chapter 2, origins of a NBTI induced



V

t

distribution in small-area HfSiON

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trapped hole creation times and corresponding threshold voltage shifts during NBTI

stress in a large number of devices. Wide dispersion of trap creation characteristic

times in several decades is observed, which we attribute to an activation energy

distribution in the reaction-diffusion (RD) model. We extract an activation energy

distribution including a local electric field effect from measured characteristic times.

A statistical model for an NBTI



V

t

distribution by employing the RD model and

convolving extracted activation energy and a single trapped hole induced V

t

shift is

developed. Our model reproduces measurement results of an overall NBTI induced



V

t

distribution and its stress time evolutions well.

In Chapter 3, NBTI trapped charge characteristics and recovery mechanisms are

examined by a statistical study of individual trapped charge emissions in small-area

HfSiON/metal gate pMOSFETs. We measure trapped charge emission times in NBTI

recovery in a large number of devices. The characteristic time distributions of the first

three emitted holes are obtained. The distributions can be well modeled by using a

thermally-assisted tunnel (ThAT) detrapping model. NBTI trapped charge energy and

spatial distributions and its activation energy distribution in the ThAT model are

discussed and extracted. We develop a statistical NBTI recovery



V

t

model based on

the ThAT and an extracted activation energy distribution. Our model can reproduce a

recovery



V

t

distribution and its temporal evolutions in small-area devices very well.

RTN and NBTI stress induced threshold voltage (V

t

) fluctuations in high-k gate

dielectric and metal-gate pMOSFETs are investigated in Chapter 4. We measured

RTN amplitude distributions before and after NBTI stress. RTN in post-stressed

devices exhibits a broader amplitude distribution than the pre-stress one. In addition,

we trace a single trapped charge induced



V

t

in NBTI stress and find that the average



V

t

is significantly larger than a



V

t

caused by RTN. A 3D atomistic simulation is

performed to compare a single-charge induced



V

t

by RTN and NBTI. In our

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calculated from the reaction-diffusion model. Our simulation confirms that the NBTI

induced



V

t

indeed has a larger distribution tail than RTN due to a current-path

percolation effect.

Nitride program charge effect on the amplitude of RTN in SONOS flash cells is

investigated in Chapter 5. We measure and simulate RTN amplitudes in floating gate

flash, planar SONOS, and FinFET SONOS cells. We find that a planar SONOS has a

wide spread in RTN amplitudes after programming while a floating gate flash cell has

identical RTN amplitudes in erase and program states. The spread of program-state

RTN in a planar SONOS is attributed to a current-path percolation effect caused by

random discrete nitride charges. The RTN amplitude spread can be significantly

reduced in a surrounding gate structure, such as FinFET SONOS, due to a higher

degree of symmetry in a program charge distribution.

In Chapter 6, amplitudes of RTN in MOSFETs possessing a nanowire-like

channel are explored and modeled analytically. In large gate width MOSFETs,

conducting current paths are modulated by random substrate dopants and

large-amplitude RTN is attributed to a current path percolation effect. In ultra-thin

body and narrow gate width MOSFETs, a current flow is physically confined to a

one-dimension-like channel. A dopant charge does not alter a current path, but only

modulates

a local channel conductivity near the dopant. In this work, we attempt to

derive an analytical RTN model for circuit simulation based on random dopant

induced local conductivity modulation in a one-dimensional channel. We make an

assumption that RTN amplitudes are linearly dependent on the number of dopants in

the vicinity of an RTN trap. An influence range of a dopant charge is evaluated

approximately from the Thomas-Fermi screening theory. The validity of this

assumption is examined by numerical device simulation or experiment. Our model

shows that RTN induced threshold voltage shifts exhibit a Poisson distribution. A

Monte Carlo analysis of RTN induced



V

t

by using a 3D device simulator is

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performed to compare with our model. Reasonably good agreement between our

model and the Monte Carlo RTN simulation is obtained for various doping

concentrations and channel lengths.

Conclusions are finally made in Chapter 7.

Keyword: Monte Carlo simulation, advanced CMOS, SONOS, floating-gate flash,

high-k, NBTI, RTN, reaction diffusion (RD) model, thermally-assisted-tunneling

(ThAT) model, single charge creation, single charge emission, activation energy

extraction, percolation effect, trap position extraction, Poisson distribution

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ACKNOWLEDGEMENT

I would first like to express my deep gratitude to my advisor, Prof. Tahui Wang.

His insightful guidance and encouragement are indispensable to the accomplishment

of this dissertation.

I also show my appreciation to all of the committee members for their invaluable

comments and suggestions. Moreover, I would like to acknowledge Dr. Chih-Sheng

Chang and all the members in ATRD for their kindly support during my part-time job

at TSMC.

During my study, many important people have influenced me. I would like to

thank Dr. C. J. Tang, Dr. H. C. Ma, and Dr. C. C. Cheng for their guidance during my

initial stage of Ph.D. study. In particular, the assistance in executing routine

measurements and simulations from Mr. T. Y. Lin, Mr. C. Y. Wang, Mr. S. S. Liang

Mr. M. W. Wang, Mr. H. D. Hsieh and Mr. C. W. Li is also greatly appreciated. I am

also indebted to the Wang and Chung group members of Emerging Device and

Technology Lab, who had made life fun. Thanks to all who accompany me, their

encouragement made me become more aggressive.

Scholarship from the department of electronics engineering at NCTU and from

ZyXEL is deeply acknowledged for easing my financial pressure. I would also

appreciate the National Science Council for providing me the travel grants to present

papers in international conferences.

Finally, I would present my deepest love to my parents. Their love is the most

important power supporting me. This dissertation is dedicated to them.

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謝誌

首先，感謝指導教授汪大暉博士。沒有汪教授的教誨與鼓勵，這本論文將無

法完成。

特別感謝論文口試委員在百忙之中給予寶貴的建議與指教。另外，在台灣積

體電路製造公司工讀期間，前瞻技術研發部部經理張智勝博士及所有全體同仁在

研究與工作上的大力協助，在此由衷感謝。

在求學過程中，感謝學長唐俊榮博士、馬煥淇博士以及鄭志昌博士不吝分享

所學，讓我快速進入狀況。此外，感謝學弟東陽、志宇、書祥、明瑋、泓達以及

啟偉分擔實驗及模擬的工作。因為有你們的協助，使得這本論文更加充實。同時

也感謝前瞻元件與技術實驗室所有成員，他們為我的博士班生涯增色許多。感謝

所有陪伴過我的人，你們的支持鼓勵是我前進的動力。

感謝國立交通大學電子研究所及朱順一合勤科技提供獎學金，減輕我的經濟

壓力。在此向國科會(National Science Council) 致上誠摯的謝意，提供經費補助，

讓我前往國際會議發表論文。

最後，我要感謝長久以來支持我的家人，他們的愛是我的重要支柱。這本論

文，獻給他們。

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TABLE CAPTIONS

Chapter 2

Table 2.1 Comparison of trapped charge creation and emission characteristics in NBTI stress and NBTI recovery. i is a sequence number in trapped charge creation in NBTI stress or trapped charge emission in NBTI recovery.

24

Chapter 5

Table 5.1 Measured RTN correlation factors in FG flash, planar SONOS and FinFET SONOS cells.

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FIGURE CAPTIONS

Chapter 1

Fig. 1.1 Projections of gate leakage current and equivalent oxide thickness (EOT) from ITRS roadmap for low-standby-power applications.

6

Fig. 1.2 A typical two-level RTN waveform resulting from electron capture/emission at an oxide trap. c and e are electron capture and emission times, respectively.

Id is RTN amplitude.

7

Fig. 1.3 Typical Vt traces during NBTI stress (a) and recovery (b). Each step-like

“quantum jump” represents a single charge capture/emission.

8

Fig. 1.4 (a) Estimation of threshold voltage shift as a function of process node [1.39] (b) measured Vt distribution of a 4-level MLC with level enlarged [1.39] and (c)

noise distributions of 90nm, 70nm, and 50nm flash memory technologies [1.40].

9

Chapter 2

Fig. 2.1 Comparison between Id degradation traces in (a) nowadays (b) previous devices. 20

Fig. 2.2 Example Vt trace in NBTI stress in a high-k gate dielectric pMOSFET. 1, 2

and 3 are the 1st, the 2nd and the 3rd trapped hole creation times. vt,1, vt,2 and

vt,3 are the 1st, the 2nd and the 3rd trapped hole induced threshold voltage shifts.

The inset shows subthreshold Id−Vg before and after NBTI stress.

21

Fig. 2.3 The probability density function of a single trapped charge (hole) induced threshold voltage shift. The solid line represents an exponential fit.

22

Fig. 2.4 The probability distribution of a trapped hole creation time in NBTI stress collected from about 130 devices. 1, 2 and 3 are the 1st, the 2nd and the 3rd

trapped hole creation times, respectively. The solid line represents a Gaussian fit.

23

Fig. 2.5 Effective activation energy distributions extracted from measured trap creation times, 1, 2 and 3. The solid line represents a Gaussian-distribution fit to the

Eeff translated from 1.

25

Fig. 2.6 NBTI induced Vt versus number of trapped holes in a device at a stress time of

0.5sec (a) and 5sec (b). Each data point represents a device. The slope of a straight line represents an average vt caused by a single trapped hole.

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Fig. 2.7 The mean of the Vt distribution versus NBTI stress time from measurement

and from our model.

27

Fig. 2.8 The variance of the Vt distribution versus NBTI stress time from measurement

and from our model.

28

Fig. 2.9 A Monte Carlo simulation flowchart. M is the number of precursors in a device. A precursor density of 1x1012 cm-2 is assumed.

29

Fig. 2.10 Monte Carlo generated i distributions. Only i=1 to 4 are shown in the figure. 30

Fig. 2.11 Trapped charge creation time distributions from measurement (symbols) and from Monte Carlo simulation (lines) after the re-ordering. The Monte Carlo simulated <log(2)>−<log(1)> is 1.68 and <log(3)>−<log(1)> is 2.67.

31

Fig. 2.12 Complementary cumulative distribution functions (1-CDF) of NBTI induced Vt from measurement and from our model. The stress time is 0.01sec, 1sec and

100sec, respectively. The inset shows the probability distributions of Vt from

measurement and this model.

32

Fig. 2.13 Comparison of NBTI induced Vt distributions (1-CDF) calculated from this

model and from the Poisson model. The dots are measurement result. The inset shows trapped charge number distributions from the two models. The stress time is 100 sec.

33

Chapter 3

Fig. 3.1 Example Id and Vt traces in NBTI relaxation. 1, 2 and 3 are the 1st, the 2nd

and the 3rd trapped hole emission times, respectively. vt,i (i=1,2,3) represents a

single emitted charge induced threshold voltage shift.

46

Fig. 3.2 The magnitude distributions of vt,1, vt,2 and all collected vt,i from NBTI

recovery traces in 170 high-k/metal gate pMOSFETs. The solid line represents an exponential fit.

47

Fig. 3.3 The probability density distributions of a trapped charge (hole) emission time in a log() scale. 1, 2 and 3 are the 1st, the 2nd and the 3rd trapped hole emission

times, respectively. The mean (<log(i)>) and the standard deviation (i) of the

distributions are indicated in the figure. The symbols are measurement result and the solid lines are from Monte Carlo simulation. A Monte Carlo simulation procedure is given in Fig. 3.10.

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Fig. 3.4 Histogram of all trapped charge emission times in a log() scale collected from 170 devices. The occurrence number distribution is rather uniform in a period from 10-2s to 103s.

49

Fig. 3.5 Schematic representation of a band diagram of a high-k/metal gate pMOSFET in relaxation. xi and Et represent a trapped charge position and energy.

50

Fig. 3.6 Activation energy (Ea) distributions extracted from the 1, 2 and 3,

respectively. 0 in Eq. (4) is chosen such that the mean of the Ea is about 0.5eV.

The solid line is a Gaussian-distribution fit.

51

Fig. 3.7 The dependence of <1> on recovery temperature. The extracted activation

energy is about 0.5eV. Each data point is an average of ten readings.

52

Fig. 3.8 Dependence of trapped electron emission times on recovery gate voltage. 15 measurements are made for each recovery Vg to take average.

53

Fig. 3.9 A PDF plot of an emission time measured from an individual trap. 54 Fig. 3.10 An illustration of difference of trap energy between NBTI and RTN defects. 55 Fig. 3.11 A total Vt shift (Vt) versus number of emitted trapped holes in a device at a

recovery time of 0.1s, 10s and 1000s. Each data point represents a device. The slope of a straight line represents an average vt caused by a single trapped hole

emission.

56

Fig. 3.12 The evolution of Vt with a recovery time. The solid line represents an average

of measured Vt traces in 170 devices. The symbols are the mean of Monte

Carlo simulated Vt distributions. A logarithmic time dependence of Vt is

obtained.

57

Fig. 3.13 Simulation flowchart of a Monte Carlo based Vt distribution model for NBTI

recovery in small area devices.

58

Fig. 3.14 The probability density distributions of NBTI recovery Vt in 80nmx30nm

pMOSFETs from measurement and from a Monte Carlo simulation. The recovery time is 0.1s, 10s, and 1000s.

59

Fig. 3.15 The variance of a recovery Vt distribution versus a recovery time in

80nmx30nm pMOSFETs from measurement and from a Monte Carlo simulation.

60

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Fig. 4.1 (a) RTN measured at VD=−0.05V and a target ID of -500nA. The Vt waveform

is obtained from the measured drain current divided by a transconductance. (b) Threshold voltage trace in NBTI stress. The stress condition is |Vg−Vt|=1.5V

and the measurement condition is the same as RTN measurement.

68

Fig. 4.2 (a) Cumulative probability distribution of a single trapped charge induced vt in

RTN vs. NBTI. RTN is measured in fresh devices. (b) Cumulative probability distributions of a single-charge induced vt for RTN in fresh devices and in

post-NBTI stress devices. The minimum detectable vt is about 1mV.

69

Fig. 4.3 (a) RTN trap position distribution along the channel extracted from 124 devices. Ltrap is the distance of a trap from the source and LDS denotes a channel length.

(b) RTN trap position distribution along the channel extracted from 124 devices.

xt is the distance of a trap from the channel.

70

Fig. 4.4 RTN amplitude distributions versus trap vertical (a) and lateral (b) positions. 71 Fig. 4.5 Relative NBTI trap creation probability versus a local surface hole

concentration. A local hole concentration and a surface electric field are calculated from a 3D device simulation with random and discrete substrate dopants. In the calculation, E0 in Eq. (2) is 1.1MV/cm.

72

Fig. 4.6 Complementary cumulative probability distributions of RTN and NBTI amplitudes from 3D atomistic simulation. The simulated devices have a gate length of 30 nm and a gate width of 30nm. The NBTI trapped charge position in the simulation is selected according to its creation probability calculated from Eq. (4.2).

73

Fig. 4.7 Cumulative probability density distributions of RTN induced vt amplitude in

devices with W/L=30nm/30nm w/ and w/o random doping and W/L=40nm/40nm.

74

Fig. 4.8 Single charge induced vt distributions in different device sizes [4.2]. 75

Chapter 5

Fig. 5.1 An illustration of two different program charge storage characteristic resulting distinct outcome of percolation path. Continuous distribution in FG flash and random discrete distribution in SONOS flash.

84

Fig. 5.2 RTN amplitude versus drain current in a FG flash cell at two program window : 1V, 2V. The drain voltage in measurement is 0.7V and the gate voltage is

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varied.

Fig. 5.3 RTN amplitude versus drain current in a SONOS flash cell at two program window : 0.8V, 1.5V. The drain voltage in measurement is 0.7V and the gate voltage is varied.

86

Fig. 5.4 Measured program-state RTN amplitude versus erase-state RTN amplitude in 40 FG flash cells. The RTN amplitude is measured at Id=500nA @Vd=0.7V.

The device dimension is W/L=0.11m/0.09m. The program window is 1V or 2V.

87

Fig. 5.5 Measured program-state RTN amplitude versus erase-state RTN amplitude in 60 planar SONOS cells. The RTN amplitude is measured at Id=500nA

@Vd=0.7V. The SONOS cells have W/L=0.09m/0.08m, a 2.8nm tunnel

oxide, a 6nm Si3N4 and a 6nm top oxide.

88

Fig. 5.6 RTN amplitude versus drain current in a FG flash cell in three P/E cycles. The Vt window is 1V. The drain voltage in measurement is 0.7V and the gate

voltage is varied.

90

Fig. 5.7 RTN amplitude versus drain current in a SONOS cell in three P/E cycles. The Vt window is 1V. The drain voltage in measurement is 0.7V and the gate

voltage is varied.

91

Fig. 5.8 Measured RTN waveform and Id versus Vg plot (a) in erase-state and (b) in

program-state of a SONOS cell. Electron trapping at an interface trap is manifested by a current discontinuity in the Id-Vg plot.

92

Fig. 5.9 The waveform of two-level RTN current switching is observed in erase-state and 1st and 2nd program-state.

93

Fig. 5.10 Simulation flow chart of our 3D atomistic simulation for RTN amplitude at program state and erase state for both FG flash and planar SONOS flash.

94

Fig. 5.11 Simulated RTN amplitude versus drain current in a FG flash cell. Program-state and erase-state have the same placement of substrate random dopants. The RTN trap is placed in the middle of the device.

95

Fig. 5.12 Simulated RTN amplitude versus drain current in a planar SONOS cell. Program-state and erase-state have a fixed placement of substrate dopants. Ten different sets of random program charges are simulated. An RTN amplitude due to number fluctuation is calculated with continuous substrate doping and program charges.

96

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FinFET SONOS obtained from a 2D simulation.

Fig. 5.14 RTN amplitude versus drain current in a FinFET SONOS cell for two P/E cycles.

98

Fig. 5.15 Program-state RTN amplitude versus erase-state RTN amplitude in FinFET SONOS cells. The fin width is 10nm. (a) RTN is measured at Id=500nA and (b)

RTN is measured at Id=200nA.

99

Fig. 5.16 In a planar SONOS, percolation paths are widely distributed in the gate width direction. In a FinFET SONOS, conducting paths are confined to a small region in the corner of the Si fin.

100

Fig. 5.17 Measurement of the correlation factor in FinFET SONOS with two different fin width, 10 nanometer and 25 nanometer. The correlation factor increases from 0.82 to 0.94 as the fin width reduces from 25 nanometer to 10 nanometer.

101

Fig. 5.18 A 3D RTN simulation in planar SONOS with different channel width. The correlation factor is calculated based on a sample size of 40 devices.

102

Chapter 6

Fig. 6.1 3D atomistic simulation of an electron concentration distribution in a cylindrical channel MOSFET. The diameter of the channel is 6nm. (a) Electron concentration distributions in two cross-sections, A and B. B has a dopant charge at the center and A does not have a dopant charge. (b) An electron density distribution along the channel. The Thomas-Fermi screening length ( ) is shown in the figure.

112

Fig. 6.2 Illustration of a one-dimensional channel RTN simulation scheme. The simulated MOSFET has a double gate structure. The channel is divided into many 1nm slices. In simulation, a dopant charge is placed uniformly in a slice and an RTN charge is placed in a 1nm bar on top of the channel.

113

Fig. 6.3 Complementary cumulative distribution function (1-CDF) of RTN induced Vt

from a 3D atomistic simulation and from the 1D channel RTN simulation. The devices have a doping concentration of 1x1019/cm3 and a channel length of 40nm. The gate width is 20nm in (a) and 7nm in (b).

114

Fig. 6.4 1D channel Monte Carlo simulation of RTN induced Vt. The channel length is

40nm and each device has 14 dopants. A dopant number in the RTN trap section (n) is equal to 0, 1, 2 and 3, respectively. For each n, we simulate 100 devices.

115 1 2 2 4 _c kT n e    

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(a) RTN induced Vt shifts in totally 400 devices. (b) The distribution of RTN

induced Vt for each n.

Fig. 6.5 Average RTN amplitude and a standard deviation versus a dopant number in an RTN trap section (n).

116

Fig. 6.6 Measured average RTN induced Vt versus a CHE program window in 45

SONOS cells. A linear relationship between the Vt and a program Vt window

is obtained.

117

Fig. 6.7 Complementary cumulative distribution function of RTN induced Vt from 1D

channel Monte Carlo RTN simulation and from this analytical model. The doping concentration is 1x1019/cm3, 7x1018/cm3 and 5x1018/cm3 respectively. The gate length is 40nm.

118

Fig. 6.8 Complementary cumulative distribution function of RTN induced Vt from 1D

channel Monte Carlo RTN simulation and from this analytical model for two different gate lengths, Lc=30nm and 40nm. The doping concentration is

1x1019/cm3.

119

Fig. 6.9 Complementary cumulative distribution function of RTN amplitude distribution in FinFET SONOS cells with a fin width=10nm. A Poisson-like shape is obtained.

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LIST OF SYMBOLS



V

t Threshold voltage shift in total during stress/recovery



v

t Single charge induced threshold voltage shift during stress/recovery

s Standard deviation of NBTI stress induced



v

t

t Time

n Power factor in RD model

N Total number of stress created traps

Id Drain current shift in total during stress/recovery

gm Transconductance

SS Subthreshold swing

i Trap creation/emission sequence number

i Characteristic time of i-th charge creation/emission

 Mean value

i Standard deviation of i

Nt Bulk trap number

 Electric field acceleration parameter [1.28]

F Electric field

ED Activation energy combined for DH2, kH, and kH2 [1.28]

W Device channel width

L Device channel length

D0 Pre-factor of Arrhenius diffusivity in RD model KF0 Pre-factor of Arrhenius generation rate in RD model KR0 Pre-factor of Arrhenius recombination rate in RD model kB Boltzmann constant

T Temperature

Eeff Effective activation energy including a local electric field effect in stress

M Precursor number

r Standard deviation of NBTI recovery induced



v

t

Ea Effective activation energy of trap emission in NBTI recovery TIL Interfacial later thickness

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xi Distance of the i-th trapped charge from HK/IL interface

Et Trap energy

B HK/IL conduction band offset mIL* Effective mass of hole in IL mHK* Effective mass of hole in HK m0 Free electron mass

q Electronic charge

ħ Reduced Planck constant

d HK thickness

x Distance between adjacent trapped charges

c RTN capture time

e RTN emission time

0 Trap cross section

vth Thermal velocity f Correlation factor

Hfin Fin height of a FinFET SONOS

Wfin Fin width of a FinFET SONOS

l Thomas-Fermi screening length Si Dielectric constant of silicon C(N,n) Binomial coefficient

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Chapter 1 Introduction

1.1 Backgrounds

The dimensions of the smallest demonstrated prototypes of silicon based CMOS devices [1.1][1.2] have been rapidly approaching the physical limit. Continual downscaling boosts device performance to meet the Moore’s Law at the expense of growing leakage problems. The gate leakage currents [1.3] and the channel leakage currents [1.4] increase rapidly with decreasing gate dielectric thickness and with shorter channel length respectively. The resultant intolerable standby power consumption has made further scaling impractical. To resolve this issue, introduction of high permittivity (high-k) materials as the gate dielectrics [1.5][1.6] have been proposed to suppress gate leakage current due to physical thickness and keep the equivalent-oxide-thickness (EOT) reasonably small at the same time to maintain the high performance, as shown in Fig. 1.1. Part of this work thus concentrates on the high-k dielectric reliability.

In nowadays high-k technology, Hf-based materials are most promising and their film chemistry [1.7][1.8], process optimization [1.9][1.10], as well as reliability assessment and analysis [1.11]-[1.13] are being extensively studied. Recently, HfSiON has been successfully integrated into CMOS devices as gate dielectric for low power applications with good reliability, comparable mobility (as SiO2), and

greatly reduced gate leakage [1.9][1.11].

As one of the most important degradation modes in CMOS technologies, the negative bias temperature instability (NBTI) has been known since the 1970s [1.14].

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The reaction-diffusion (RD) model [1.14]-[1.17] and a charge trapping model [1.18]-[1.23] are commonly adopted for NBTI degradation. The RD model can well describe the mean of an NBTI induced Vt distribution, or a Vt in a large area

device. However, hydrogen back-diffusion [1.17] in the framework of the RD model was not able to explain a NBTI recovery phenomenon which shows a log(t) dependence of Vt on relaxation time [1.24][1.25]. Since it was suggested that RD

model cannot explain NBTI recovery transient and the shape of AC duty cycle dependence [1.21]. This apparent failure of RD framework has inspired a reintroduction of “well-based” charge trapping model [1.21]-[1.23][1.26]. However, the charge trapping model fails to explain the power-law dependence of Vt evolution

on stress time.

Aforementioned, unlike most reliability effects, NBTI Vt degradation recovers

partly after the removal of stress [1.27]. Wang et al used a fast transient technique to characterize NBTI recovery and found a log(t) dependence of Vt on relaxation time

[1.24]. A log(t) dependence was also reported in [1.25] where the authors proposed a dispersive transport model within the RD framework to overcome the apparent deficiency of the RD model in relaxation time dependence. Alam et al ascribed a log(t) recovery transient to a fast charge detrapping process on top of slower Nit

re-passivation as encapsulated by the RD model [1.28][1.29]. More recently, Grasser et al used a time dependent defect spectroscopy method to investigate NBTI recovery and concluded that NBTI recovery is due to thermally-assisted discharging of traps and no diffusion process is involved [1.23].

In addition to NBTI, random telegraph noise (RTN) phenomenon arising from charge emission and capture at an interface trap site [1.30]-[1.33] has been recognized as a new scaling concern in both advanced CMOS [1.34]-[1.36] and flash memory

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[1.37]-[1.42]. Typical two-level RTN pattern is shown in Fig. 1.2.

With respect to flash memory devices, they play an important role in VLSI industry with their wide applications. NOR-type flash memory is suitable for code storage applications, such as mobile phones and handheld devices. On the other hand, NAND-type flash memory is suitable for data storage applications, such as USB and solid-state-disk (SSD). Part of this work thus concentrates on the RTN effect on flash memory cells.

1.2 Description of the Problem

As device dimensions reduce to a nanometer scale, the number of traps generated by NBTI stress varies significantly from a device to a device due to stochastic process of trap generation and dispersion of activation energy in the RD model. In these nanoscale transistors, NBTI induced Vt scatters widely and it is no longer sufficient

to consider just the mean value of Vt in circuit simulation. An accurate model of an

entire Vt distribution and its stress time evolution is needed in a worst-case circuit

simulation to ensure that the tail of Vt distribution does not cross the reliability

criteria during the specified lifetime of an integrated circuit [1.43]-[1.45]. While the mean of an NBTI Vt distribution, or a Vt in a large area device, can be well

described by the RD model [1.14][1.16][1.17][1.28], the RD model alone is insufficient to predict an entire Vt distribution in small area devices with stress time.

On the other hand, the post-NBT recovery has the same issue that ThAT model alone is insufficient to predict an entire Vt distribution in small area devices with recovery

time. As a result, we develop statistical models for both NBTI stress and recovery by characterization of single charge creation/emission (Fig. 1.3) using fast transient measurement technique.

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Furthermore, as the technology node is scaled down, RTN also becomes a more and more important reliability issue in both CMOS and flash memory technologies. A single charge trapping/detrapping will induce a large fluctuation in read current and thus a read failure. As a result, the RTN amplitude and its trap positions are also studied in this dissertation.

In terms of charge storage devices, two state-of-the-art structures attract great attention. One is floating gate (FG) flash and the other is charge trapping (CT) flash. Recently, 3D structures have been proposed for flash memory arrays. Vt fluctuations

originated from a large-amplitude RTN tail will cause a read error and become a prominent issue in designing a multilevel-cell (MLC) flash memory in 45nm technology node and beyond, as shown in Fig. 1.4. We will thus focus on the RTN amplitude distributions and its dependence on program window in FG, planar SONOS and FinFET SONOS flash memory cells.

At present, RTN amplitude model is an empirical formula. However, the underlying RTN physical mechanism must be understood in order to make meaningful projection of device/circuit lifetime. Since it’s hard to derive a 3D RTN amplitude model directly, we start from 1D device structures which are also promising candidates in future VLSI technology. We use a 3D Monte Carlo simulation to verify our model.

1.3 Organization of this dissertation

This dissertation consists of seven chapters. The scope of the dissertation mainly focuses on the applications of single charge phenomena in advanced CMOS and SONOS flash memory. Following the introduction, the characterization and physical mechanisms of the NBTI degradation in a small-area high-k/metal-gate pMOSFET

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are described in Chapter 2. A statistical model for an NBTI induced Vt distribution

by employing the RD model and convolving extracted activation energy including a local electric field effect and a single trapped hole induced Vt shift is developed.

NBTI trapped charge characteristics and recovery mechanisms are proposed in Chapter 3 by a statistical study of individual trapped charge emissions in small-area HfSiON/metal-gate pMOSFETs. We develop a statistical NBTI recovery Vt model

based on the ThAT and an extracted activation energy distribution. In Chapter 4, we compare the RTN and NBT-stress induced Vt amplitude distributions. A 3D atomistic

simulation is performed to compare a single-charge induced Vt by RTN and NBTI.

In Chapter 5, nitride program charge effect on the amplitude of RTN in flash cells is investigated. We measure and simulate RTN amplitudes in floating gate flash, planar SONOS, and FinFET SONOS cells. In Chapter 6, an RTN amplitude distribution model in nanowire-like structures is developed. A Poisson distribution is proposed and partly verified using measurement in SONOS flash memory cells. Finally, conclusions are drawn in Chapter 7.

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Fig. 1.1 Projections of gate leakage current and equivalent oxide thickness (EOT)

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t

_c

t

_e

ΔI

_d

Dra

in

Cu

rr

ent

Time

empty trap state

occupied trap state

(a)

S

D

★

_Trap

Channel Electron

e

-(b)

Fig. 1.2 A typical two-level RTN waveform resulting from electron capture/emission

at an oxide trap. tc and te are electron capture and emission times, respectively. Id is

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10

-4

10

-3

10

-2

10

-1

10

0

10

1

10

2

360

380

400 |V

t

| (

mV)

Stress Time (s)

NBTI Stress

(a)

10

-3

10

-2

10

-1

10

0

10

1

10

2

10

3

360

380

400 |V

t

| (mV)

Elapsed Time after Stress (s)

NBTI Recovery

(b)

Fig. 1.3 Typical Vt traces during NBTI stress (a) and recovery (b). Each step-like

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T hre shol d vol ta ge s hi ft (V ) Process node (nm) 2.5 2.0 1.5 1.0 0.5 0 20 40 60 80 100 RTS

floating gate interference others

Limit of MLC

(a)

(b) (c)

Fig. 1.4 (a) Estimation of threshold voltage shift as a function of process node [1.39]

(b) measured Vt distribution of a 4-level MLC with level enlarged [1.39] and (c) noise

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Chapter 2 Statistical Characterization of Individual Charge Trapping

Times and Modeling of



V

t

Distribution by NBTI Stress

2.1 Preface

Negative bias temperature instability has been recognized as a major concern in scaled high-permittivity (high-k) gate dielectric pMOSFETs because of its significant impact on performance and reliability in digital and analog circuits [1.43][2.1]-[2.6]. NBTI caused noise margin degradation in a SRAM cell and frequency degradation in a ring oscillator have been reported [2.1]. NBTI severity aggravates as supply voltage reduces in device scaling. In addition to digital circuits, NBTI is of particular importance for analog applications where the ability to match device characteristics to a high precision is critical [2.3]. For instance, in digital-to-analog converters, NBTI can pose a serious reliability issue as a small Vt shift in bias current source can cause

large gain errors [2.4].

As device dimensions reduce to a nanometer scale, the number of traps generated by NBTI stress varies significantly from a device to a device due to stochastic process of trap generation and dispersion of activation energy in the RD model. In these nanoscale transistors, NBTI induced Vt scatters widely and it is no longer sufficient

to consider just the mean value of Vt in circuit simulation. An accurate model of an

entire Vt distribution and its stress time evolution is needed in a worst-case circuit

simulation to ensure that the tail of Vt distribution does not cross the reliability

criteria during the specified lifetime of an integrated circuit [1.43]-[1.45]. While the mean of an NBTI Vt distribution, or a Vt in a large area device, can be well

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described by the RD model [1.14][1.16][1.17][1.28], the RD model alone is insufficient to predict an entire Vt distribution in small area devices.

We first measured an Id degradation in a large-area device (Fig. 2.1(a)). As

compared with our earlier works [1.18], initial trap density is suppressed (from 50% to 20%) due to the improvement of device fabrication technique. Consequently, a RD model rather than a charge trapping model is more adaptable to our present measurement results.

A Vt shift in an NBTI stressed device can be expressed as the sum of each

individual trapped charge induced vt, i.e., ₁ v,

N t _i t i

V _

 



 , where N is a total number of stress created traps in a device and vt denotes a single trapped charge

caused Vt shift. Two factors affect a Vt distribution. One is the dispersion of vt and

the other is fluctuations in number of traps N in stressed devices. The origin and the magnitude distribution of vt have been investigated thoroughly [2.7][2.8]. Previous

characterization and 3D atomistic simulation show that a vt exhibits an exponential

distribution approximately, i.e., f(|vt|)=exp(−|vt|/s)/s, due to a random substrate

dopant induced current-path percolation effect [2.7][2.9]. To derive a Vt distribution,

we still need a distribution model for a trap number N. In literature, a Poisson distributed N was usually assumed [2.7][2.8][2.10]. The Poisson model is, however, based on a notion that individual trapped charge creations during NBTI stress are independent. In other words, each new trap creation in a device has the same probability regardless of how many traps have been created. Nevertheless, the RD model and measurement result show that NBTI degradation obeys a power-law dependence on stress time, i.e., t1/n with n~6 [1.28][2.11], implying that a new trap creation rate decreases with an increasing trapped charge number. Therefore, the use of a Poisson model is contradictory to the RD model and measurement result and may

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exaggerate N and a Vt distribution tail significantly. To resolve this discrepancy,

Alam et al simulated a trap number distribution by using a Markov Chain Monte Carlo method [2.12] to consider stochastic process of trap generation within a RD framework. However, they did not consider the dispersion of activation energy in the RD model. As a result, their simulated trap characteristic time distribution is much narrower than measurement result in [2.13].

In this work, we characterize NBTI trap creation and Vt shifts in small area

devices. Unlike a large-area device, NBTI induced Vt degradation proceeds in discrete

steps in small area devices [2.9][2.13]. Due to the discrete nature of a Vt evolution, we

are able to measure individual trapped charge creation times and each trapped charge induced Vt shift. An effective activation energy distribution including a local electric

field in the RD model will be extracted from measured trapped charge creation times. A Monte Carlo model employing the RD model and an extracted activation energy distribution will be developed to simulate an NBTI Vt distribution and its stress time

evolutions.

2.2 Characterization of Individual NBTI Trapped Charge Creation

2.2.1 Devices and Measurement Setup

The devices have a drawn gate length of 30nm, a gate width of 80nm and a high-k (HfSiON) gate dielectric with an equivalent oxide thickness of ~1nm. Similarly to [1.19], the characterization is performed in a stress-measurement-stress (SMS) sequence. In NBTI stress phase, Vgs=−1.8V and Vd=0V at room temperature.

In measurement phase, the drain voltage is −0.05V and the gate voltage is adjusted to have a drain current of about 500nA in a fresh device. Drain current variations are traced with a switch delay time less than 1s using Agilent B1500.

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2.2.2 Single Charge Creation Induced vt Distribution

A corresponding Vt trace is obtained from a measured Id divided by a

transconductance. An example Vt trace is shown in Fig. 2.2. To check on interface trap

creation, we monitor transconductance (gm) and subthreshold swing (SS) degradations

during the stress. The subthreshold Id−Vg characteristics before and after an NBTI

stress are shown in the inset of Fig. 2.2. An almost parallel shift after stress is observed, thus indicating that Vt degradation is mainly caused by fixed trapped charge

creation rather than interface trap creation. Both SS and gm degradations are less than

5% in the stress period. For simplicity, a constant transconductance is used when converting Id into a Vt trace in Fig. 2.2. Each abrupt Vt change (vt,i) in Fig. 2.2 is

due to a single trapped hole creation, where i denotes a trapped charge creation sequence number.

We collect all vt,i in about 130 devices. The magnitude distribution of vt is

plotted in Fig. 2.3. The solid line in Fig. 2.3 represents an exponential fit with a slope (s) of 3.3mV.

2.2.3 Characteristic Times for Trapped Charge Creation

In addition to vt, individual trapped charge creation times are clearly defined in

Fig. 2.2. We collect the first three trapped hole creation times, i.e., i, i=1,2,3, in about

130 devices. The probability density functions (PDFs) of log(i) are shown in Fig. 2.4.

It should be remarked that about 3% devices have less than 3 traps created in a stress period of 100sec. Table 2.1 shows the mean (<log(i)>) and the standard deviation (i)

of the three log(i) distributions. For comparison, the <log(i)> and i in NBTI

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between stress mode and recovery mode are noticed. We find that <log(i)>−<log(1)>~nlog(i) and the standard deviations1>2>3 in NBTI stress

while <log(i+1)>−<log(i)>~constant and the standard deviations1<2<3 in NBTI

recovery. The detail explanations for the features in NBTI recovery has been given in Chapter 3. In this Chapter, we are focused on the characteristics of stress.

The measured i spreads over several decades of time. There are two possible

reasons for the wide spread. One is the stochastic process of trap generation in the RD model and the other is the dispersion of activation energy including a local electric field effect (effective activation energy (Eeff) hereafter). Other parameters in the RD

model or other processes are unlikely to cause such wide spread. The stochastic process of trap generation has been investigated in [2.12] by using a Markov chain Monte Carlo method. Their simulated trap creation time distribution is much tighter than our measured result. Consequently, we attribute the wide spread of trap characteristic times mainly to the dispersion of activation energy arising from different local chemistry in the RD model. Furthermore, the fitting parameters vary a lot from Alam’s own publications. In other words, the stochastic process is negligible, as compared to the dispersion of activation energy. As a result, in the following, a statistical i distribution model considering only an activation energy distribution will

be developed.

According to the RD model, the stress time dependence of the number of NBTI generated traps in a device is shown below [1.28],

(2.1) and 1 2 exp( )exp[ ] , ~ 6, 3 D n t B E F N A t n k T



 

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(2.2)

where W is a gate width, L is a gate length, KF0, KR0 and D0 are the pre-factors of

forward and reverse reaction rate constants and diffusivity in a Arrhenius activation energy, respectively [2.11], and p is the local channel hole concentration. The effective activation energy (Eeff) in Eq. (2.1) is defined as

(2.3)

By re-arranging the terms in Eq. (2.1), the relationship between the i-th trapped charge creation time (i) and effective activation energy is shown below

(2.4)

From the above equation, the relationship of the mean of the log(i) is obtained,

(2.5)

n is about 5.6 in our measurement in an initial stress stage. Thus, we can therefore

obtain <log(2)>−<log(1)>=5.6log(2)=1.69 and <log(3)>−<log(1)>=5.6log(3)=2.67

without regard to activation energy. The calculated result from Eq. (2.5) is in reasonable agreement with the measurement result in Table 2.1.

2.2.4 Activation Energy Distribution

1 6 0 2 3 0 0 [ ][ ] [ F ] , R K SiH h A WLD pK  

log( )

log( ).

2.3

eff i B

nE

n

i

n

A

k T









1

log( )



_i

log( )



n

log( ),

i



  



2 . 3 eff D B E E 



Fk T

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In the following, we will extract an activation energy distribution from measured trap characteristic times. By re-arranging the terms in Eq. (2.4), effective activation energy can be readily obtained as follows,

(2.6)

We can translate the measured log(i) distribution into a relative activation

energy distribution by subtracting a term nlog(i) from it. Extracted Eeff distributions

from 1, 2 and 3, respectively, are shown in Fig. 2.5. Generally, the Eeff distributions

from the 1, 2 and 3 have a reasonable match. Note that the Eeff from the 1 is slightly

broader than the other two distributions, as pointed out in Table I. The pre-factor A in Eq. (2.6) is chosen such that an average value of Eeff is about 0.12eV [2.15]. The solid

line in Fig. 2.5 represents a Gaussian distribution fit to the Eeff of 1 witha mean of

0.12eV and a standard deviation of 0.015eV.

2.3 Modeling of an NBTI Induced V

t

Distribution

2.3.1 Measured NBTI Induced Vt Distribution

We measure NBTI induced Vt distributions at different stress times. We record

the number of generated traps and a total Vt shift in each device. Fig. 2.6 shows the

measurement result at a stress time of 0.5sec and 5sec. The y-axis is Vt and the

x-axis is the number of trapped holes. Each data point represents a device. The

measurement data points scatter along a straight line, as shown in Fig. 2.6. The slope of the line is about 3.3mV, i.e., an average single-charge induced Vt shift. A straight

line with a slope of 3.3mV is drawn as a reference father than a real average value. Vt and NBTI trap number distributions spread as stress time increases. We extract

2.3 [log( )

log( )

log( )].

B eff i

k T

E

n

i

n

A

n









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the mean and the variance of the Vt distributions. An average of Vt in 130 devices

is plotted in Fig. 2.7. The mean follows a power law dependence on stress time (t1/n) in five decades of time with n about 6. The variance of the Vt distribution also

increases with stress time, as shown in Fig. 2.8. In our earlier work, we reported a two-stage Vt degradation by BTI stress [1.18]. The first stage is ascribed to the

charging of pre-existing high-k dielectric traps and exhibits a log(t) dependence. The second stage degradation is caused by high-k dielectric trap creation and follows a power law dependence on stress time. In this work, we do not observe the stage of log(t) degradation in our stress period possibly because of fewer pre-existing traps in the current samples.

2.3.2 Monte Carlo Simulation Flow

A statistical model based on a Monte Carlo (MC) approach is developed to calculate the number of traps (N) and entire Vt distributions. A Monte Carlo

flowchart is shown in Fig. 2.9. In our MC simulation, a Poisson-distributed precursor number (M) in each device is assumed with a mean value of 24 in an 80nmx30nm device, which corresponds to a precursor density of 1012 cm-2 [2.16]. A sequence number (i) is assigned to each precursor in a device. The activation energy of each precursor is chosen according to the measured Eeff distribution in Fig. 2.5. A trapped

charge creation time is then computed from Eq. (2.4). The simulated log(i)

distributions are shown in Fig. 2.10. Each distribution has the same shape as the activation energy. Due to a significant overlap of the distributions, some precursors with a larger sequence number are converted to a trapped charge earlier than the ones with a smaller i. Thus, we re-order trapped charge creation sequence number in each device. The i distributions after the re-ordering are shown in Fig. 2.11. The measured

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result is also shown in the figure for comparison. Two points should be noted. First, after the re-ordering, the standard deviation of log(i) decreases with an increasing i.

This feature is consistent with the measurement result in Table 2.1. Second, The shape of the log(i) distribution with i=1 is least affected by the re-ordering. Consequently,

we used the measured result of 1 to extract an Eeff distribution in Fig. 2.5.

2.3.3 Monte Carlo Simulation Results and Discussion

For a stress time ts, the number of trapped charges N is computed by counting all

the precursors with i (i=1,2,...,M)less than ts. For each counted trapped charge, a vt

is selected based on an exponential distribution, f(|vt|)=exp(−|vt|/s/s, with s

=3.3mV. A Vt at a stress time ts can be computed by summing up all the vt,

i.e., _,

1 v

N t _i t i

V _

 



 In total, 5x105 devices are simulated. The mean and the variance of the simulated Vt distributions versus stress time are shown in Fig. 2.7 and Fig. 2.8,

respectively. Our simulation is in good agreement with measurement results. In addition, we compare measured and simulated Vt distributions at different stress

times. Complementary cumulative distribution functions (1-CDF) of NBTI induced Vt at a stress time of ts=0.01sec, 1sec and 100sec are plotted in Fig. 2.12. The inset

of the figure is the probability density function of Vt. Good agreement between our

model and measurement is obtained. We also compare our model with the Poisson distributed trap number model [2.7]. To examine the difference in a Vt distribution

tail, complementary cumulative distribution functions (1-CDF) of the two models at a stress time of 100sec are plotted in Fig. 2.13 with a logarithmic scale in y-axis. The probability distributions of a trapped charge number from the two models are plotted in the inset. The Poisson model apparently yields a broader distribution in trapped charge number (N) and thus a larger Vt tail. The difference between the two models

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increases with stress time as more trapped charges are created.

2.4 Summary

We characterize NBTI trap creation in a large number of high-k dielectric pMOSFETs. Origins of an NBTI induced Vt distribution have been identified. The

broad distribution of trap creation times is attributed to an activation energy distribution in the RD model. An activation energy distribution including a local electric field effect has been extracted from measured trap characteristic times. We develop a statistical model to simulate an NBTI induced Vt distribution in small area

devices. The correlation between an activation energy distribution and an NBTI Vt

distribution has been established. Our model can reproduce the measurement results of an NBTI Vt distribution and its stress time evolutions well.

先進互補式金氧半電晶體及快閃式記憶元件中單一電荷效應之統計性研究

國 立 交 通 大 學

電子工程學系電子研究所

博 士 論 文

先進互補式金氧半電晶體及快閃式記憶元件中單

一電荷效應之統計性研究

Statistical Study of Single Charge Phenomena in

Advanced CMOS and Flash Memory

研 究 生 ：邱榮標

指導教授 ：汪大暉 教授

先進互補式金氧半電晶體及快閃式記憶元件中單一電荷效

應之統計性研究

Statistical Study of Single Charge Phenomena in Advanced

CMOS and Flash Memory

研 究 生：邱榮標 Student：Jung-Piao Chiu

指導教授：汪大暉 Advisor：Tahui Wang

國 立 交 通 大 學

電子工程學系 電子研究所

博 士 論 文

先進互補式金氧半電晶體及快閃式記憶元件中單一電荷效應之統計性研究

學生：邱榮標

指導教授：汪大暉博士

國立交通大學 電子工程學系 電子研究所

摘

要

本 篇論文 主要 著重 在 單電 子效 應於 先進互 補式 金氧 半電晶 體 (advanced

CMOS)及快閃式記憶元件(flash memory)之應用。高介電閘極氧化層(high-k)之可

靠性議題，如電壓溫度引致不穩定(BTI)、隨機電報雜訊(RTN)之研究，亦有所探

討。更利用蒙地卡羅模擬進一步驗證理論及實驗。

第一章首先描述本論文中單電子效應之應用研究成果。首先探討高介電閘極

材料(high-k)金氧半電晶體元件中，藉由量測 NBTI 加速測試中，單一電荷捕捉及

釋放所造成的臨界電壓及特徵時間變化，進一步探討在奈米級元件的可靠性議

題。接下來吾人討論於 pMOSFET 中，同為單電子效應之 RTN 及 NBTI 的異同，

並利用 reaction-diffusion(RD)模型及蒙地卡羅方法模擬 NBTI 缺陷之產生。此外，

吾人於此篇論文最後，討論於快閃式記憶元件中寫入載子對於 RTN 之影響，主

要探討浮動閘極(floating gate)、平面(planar)及鰭狀(FinFET)氮化矽(SONOS)快閃

式記憶元件中，載子寫入前後 RTN 之變化。

在第二章中，吾人探討了在小面積 high-k 元件中，NBTI 造成之總臨界電壓

變化(



V

)分佈及其形成原因。吾人量測大量小面積元件之單電荷產生特徵時間及

其造成之臨界電壓變化。吾人發現單電荷產生之特徵時間有數 decade 之廣，並

提出用 reaction-diffusion(RD)模型中之反應活化能角度詮釋此一現象，更進一步

由特徵時間分佈萃取出反應活化能分佈。最後吾人提出一統計模型，此模型基於

RD 模型之基礎加入反應活化能分佈及單電荷造成之臨界電壓變化分佈。最後以

蒙地卡羅模擬重現實驗



V

分佈及其和 NBTI 操作時間的關係。

第三章延續第二章之主題，探討小面積 high-k 元件中，NBTI 造成之總臨界

電壓變化(



V

)分佈及其形成原因。不同於其他可靠度議題，NBTI 在操作電壓移

除後有一特殊之回復現象。利用類似前一章的方法，吾人量測大量小面積元件之

單電荷逸散特徵時間及其造成之臨界電壓變化。吾人以「熱助穿隧」模型解釋，

並由缺陷能量分佈、空間分佈及反應活化能分佈進一步探討並萃取反應活化能分

佈。最後提出一統計模型，以熱助穿隧模型為基礎加上反應活化能分佈，完整解

釋並預測回復現象造成之



V

分佈及其和回復時間之關係。

單電子效應的應用除了 NBTI 之外，另一個重要的可靠度議題就是 RTN。這

兩種現象之機制確有相似之處，近年來甚至有人認為 NBTI 是 RTN 在特殊偏壓

條件下的產物。在第四章，吾人量測並比較製程產生之 RTN 缺陷(fresh RTN)、

NBTI 操作產生之 RTN 缺陷(post-NBTI stress RTN)、NBT 測試過程中之單電荷引

致臨界電壓變化，結果發現 NBTI 測試過程中之平均單電荷引致臨界電壓變化量

大於製程產生之缺陷。為此吾人用 RD 模型進行 3D 模擬，結果顯示因為 NBTI

測試產生之缺陷位置較容易出現在主要電流滲透路徑，進而產生較大之單電荷引

致臨界電壓變化。也間接證明 NBTI 之缺陷為新產生之缺陷，和製程產生之 RTN

缺陷不同。

在第五章中，吾人探討 SONOS 元件的寫入電荷對於 RTN 引致臨界電壓變化

量的影響。吾人量測並模擬 RTN 在浮動式閘極(floating gate)、平面式 SONOS、

鰭式 SONOS 之振幅大小，並記錄其在寫入/抹除前後的變化。研究發現 RTN 在

平面式 SONOS 寫入/抹除前後有大量的變化，而浮動式閘極幾乎在寫入/抹除前

後擁有同樣大小之 RTN。主要是因為 SONOS 中氮化矽層儲存之電荷為一離散的

狀態，使寫入/抹除前後之電流滲透路徑改變，而浮動式閘極因為電荷儲存層為

導體，故 RTN 之大小不會因為寫入/抹除動作而有變化。最後吾人發現當 SONOS

由平面式結構進入鰭式結構，RTN 在寫入/抹除前後之變化量會被大幅度的壓

國立交通大學

博士論文

研究生：邱榮標

指導教授：汪大暉教授

研究生：邱榮標 Student：Jung-Piao Chiu

國立交通大學

電子工程學系電子研究所

博士論文

國立交通大學電子工程學系電子研究所

本篇論文主要著重在單電子效應於先進互補式金氧半電晶體 (advanced