Low-Noise Amplifier Design With Dual Reactive
Feedback for Broadband Simultaneous
Noise and Impedance Matching
Chang-Tsung Fu, Member, IEEE, Chien-Nan Kuo, Member, IEEE, and Stewart S. Taylor, Fellow, IEEE
Abstract—The simultaneous noise and impedance matching
(SNIM) condition for a common-source amplifier is analyzed. Transistor noise parameters are derived based on the more com-plete hybrid- model, and the dominant factors jeopardizing SNIM are identified. Strategies for narrowband and broadband SNIM (BSNIM) are derived accordingly. A dual reactive feedback circuit along with an LC-ladder matching network is proposed to achieve the BSNIM. It includes a capacitive and an induc-tive feedback, where the former utilizes the transistor parasitic gate-to-drain capacitance and the latter is formed by transformer coupling. This circuit topology has been validated in 0.18- and 0.13- m CMOS technologies for a 3–11-GHz ultra-wideband (UWB) and a 2.4–5.4-GHz multistandard application, respec-tively. The 3–11-GHz UWB low-noise amplifier is detailed as a design example.
Index Terms—Broadband input matching, capacitive feedback,
low-noise amplifier (LNA), low power, noise optimized design, si-multaneous noise and impedance matching (SNIM), transformer feedback, ultra-wideband (UWB).
I. INTRODUCTION
A
LOW-NOISE amplifier (LNA) in a wireless receiver is expected to have high gain and low noise figure (NF) for a sufficient signal-to-noise ratio to demodulate signals. Among various MOSFET LNA circuit topologies, the common-source (CS) based amplifier is generally preferred, as it has better noise performance within limited power consumption. It is especially popular for extreme applications in which ultra-low power or very high frequency is demanded. It is well known that gain and noise performance of a linear two-port amplifier can be op-timized by fulfilling the condition of simultaneous noise and impedance matching (SNIM) at the input [1], [2]. SNIM is aManuscript received July 16, 2009; revised November 11, 2009. First pub-lished March 15, 2010; current version pubpub-lished April 14, 2010. This work was supported jointly by the National Science Council, Taiwan, under Grant NSC 98-2220-E-009-064, the MediaTek Center, National Chiao-Tung Univer-sity (NCTU), and the Industrial Technology Research Institute Joint Research Center.
C.-T. Fu was with the Department of Electronic Engineering, National Chiao-Tung University, Hsinchu, 300 Taiwan. He is now with the Intel Laboratory, Intel Corporation, Hillsboro, OR 97124 USA (e-mail: ctfu@ieee.org; chang-tsung.fu@intel.com).
C.-N. Kuo is with the Department of Electronic Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan (e-mail: cnkuo@mail.nctu.edu.tw).
S. S. Taylor is with the Intel Laboratory, Intel Corporation, Hillsboro, OR 97124 USA (e-mail: stewart.s.taylor@intel.com).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2010.2041570
Fig. 1. SNIM approaching for a CS LNA.
condition that the input impedance and the conjugate of the noise optimized source impedance of the entire am-plifier are simultaneously matched to the source impedance , i.e., , as shown in Fig. 1. As such, the NF of the amplifier approaches the minimum NF .
The concept of SNIM was first brought up in [2] with a com-plete two-port analysis on feedback amplification, yielding a series of matrices suitable for computer-aided design in which the design is accomplished by an iterative graphical maneuver on a Smith chart. However, since limited circuit insight can be directly obtained from such an approach [2]–[6], optimization methods by analyzing simplified transistor noise models were proposed [7]–[14], in which most of them are specifically for the inductive source degenerated CS amplifier. While van der Ziel’s analysis is widely adopted to explain the -to- mis-match of a MOS transistor, it was found, however, that induced gate noise is not the dominant cause of this mismatch. The noise from gate resistance was mentioned, but not included in SNIM analysis. Hence, there is a gap between the analysis and prac-tical design that relies on iterative steps to resolve. At this point the approaches by [7] and [8] provide more consistent results with simulation.
For a broadband SNIM (BSNIM) LNA design, frequency dependency of the noise parameters should be considered. Whereas the and derived in the literatures have different frequency dependency, BSNIM seems difficult to achieve. This is observed in the broadband amplifier realized by employing a multiorder LC matching network [15], of which the noise performance is still band-limited. In 2006, two ultra-wideband (UWB) LNAs utilizing distinct transformer feedback structures were reported [16], [17], both showing a broadband noise performance. In [16], we demonstrated the first BSNIM LNA by employing a dual reactive feedback topology. We infer the work in [17] might also achieve BSNIM as two reactive feedback paths are employed in the first stage, although this was not discussed. To the best of the authors’
knowledge, an effective BSNIM LNA design approach has not been revealed yet.
In this paper, we provide a design approach for a BSNIM LNA in CMOS based upon transistor noise parameter analysis and provide an example. It is the theoretical extension of our ear-lier papers [16], [18]. Starting in Section II, we first analyze the practical mechanisms jeopardizing the ideal SNIM condition in-side a CMOS transistor, including the effects of the gate resis-tance, gate-to-drain capaciresis-tance, and induced gate noise. Based on the derived four noise parameters, the strategies to achieve SNIM are proposed for both narrowband and broadband appli-cations as design guidelines. In Section III, a dual reactive feed-back amplifier with an LC ladder matching network achieving BSNIM is introduced as a solution. Section IV demonstrates the design example of an UWB LNA implemented in a TSMC 0.18- m CMOS process [16], along with the experiment re-sults. Section V summarizes and concludes this paper. In the Appendix, the noise analysis to obtain the input-referred noise sources for noise parameters is presented. The effect of noise contributed by the succeeding stages following an LNA is also briefly discussed in the Appendix.
II. SIMULTANEOUSNOISE ANDINPUT MATCHING: ANALYSIS ANDSOLUTION
In traditional microwave theory, a CS amplifier can be de-signed to be either gain optimized by impedance matching or noise optimized by noise matching [1]. Whereas the latter is more critical in an LNA design, input impedance matching is necessary to minimize the variation in the voltage standing-wave ratio (VSWR) with transmission line length, and the ac-companying variation in gain and linearity. However, as shown later, SNIM is not “gain optimized” since it can only be achieved by employing feedback techniques with the gain somewhat re-duced. This may not be a practical problem as modern scaled technology usually has adequate or excess gain. The approach for SNIM optimizes the noise performance first, and then de-signs with feedback for a small input reflection. The gain re-sponse is typically dominated by the output network of a CS amplifier and has limited correlation with SNIM.
The development of BSNIM design requires an accurate derivation of input-referred noise sources for the noise param-eters. In this paper, it is obtained with the developed analysis technique, as in the Appendix. After the noise parameter equations are obtained, a simplification is made and validated numerically. By comparing and , the strategies for BSNIM is derived.
A. Mismatch Between and of a CS MOS Amplifier
The noise model employed for the transistor noise analysis is shown in Fig. 2, in which is the channel thermal noise and
is the induced gate noise. Their values are formulated as (1) (2)
Fig. 2. Noise model employed for transistor noise analysis.
Fig. 3. Ideal case of a CS amplifier satisfying SNIM condition at all frequency.
Here, is the drain-to-source channel conductance with zero . is the intrinsic gate-to-source capacitance via the channel, and is the extrinsic parasitic gate-to-source capacitance from metal overlap, roughly equal to . and constitute . The noise contribution of is condition-ally ignored here and will be discussed in the Appendix. and in (1) and (2) are derived as 2/3 and 4/3, respectively, for long channel MOS transistors [9]. Since and are introduced by the same channel resistance, they are partially correlated to each other with the correlation factor defined as
(3)
where is derived as for long channel devices and the imaginary unit comes from the capacitive coupling by . The directions of and in Fig. 2 decide the sign of the correlation factor. is the associated noise source of gate resistance , whose value is
(4) The metal overlap parasitic capacitances such as and are included in this model for analysis.
The mismatch between and of a CS amplifier is well known. To identify the factors causing this mismatch, we start with the ideal case that always meets the SNIM condition, i.e., . Consider the ideal hybrid- model of a MOS transistor, shown in Fig. 3, which includes and a noiseless gate resistor . By applying the noise analysis technique in the Appendix, of this ideal transistor can be shown to be
(5) and is
(6) Obviously is equal to at all frequency. Therefore, and can both be tuned and matched to in Fig. 1 simul-taneously with a lossless matching network to meet the SNIM condition.
Fig. 4. Simplified MOS transistor noise models testing effects of: (a) associated noise of gate resistance, (b)C , and (c) the induced gate noise.
In practice, as shown in Fig. 2, and are found to differ from each other by three major factors, referred to as -to- discrepancy factors, which are: 1) independent
noise sources at the gate; 2) gate-to-drain capacitance; and 3) induced gate noise. Effects of these three factors can be observed individually by the three test cases, as shown in Fig. 4. The first factor is the independent noise source at the gate port. Typically, this is the gate resistance noise . Using the noise model shown in Fig. 4(a), the analysis of is signifi-cantly changed to be
(7)
where . In comparison to (5), the noise source increases the real part of with a frequency-dependent term, and thus makes larger than . This factor is found to be the primary factor in -to- discrepancy in most CMOS LNA design. The noise from a nonideal input matching network also has the same effect.
The second factor results from parasitic feedback via gate-to-drain capacitance . Consider the simplified transistor noise model with , as shown in Fig. 4(b). In comparison with
the ideal case in Fig. 3 with , the
inclusion of changes due to the effect of feedback such that
(8) Via feedback, the loading impedance affects signif-icantly. In contrast, impacts only by its loading effect ( itself) such that
(9) The change of loading impedance has no effect on .
The third factor is the induced gate noise. Consider the noise model with , as shown in Fig. 4(c). , , and are ignored. The derived is approximately as
(10) It is beneficial to define the output noise contribution ratio of
to as
(11) in (10) can then be simplified as
(12) By comparing this with the corresponding , equal to , the induced gate noise is found to reduce the effective capacitance of and introduces a frequency-dependent real part on .
With all of the three factors considered, it can be shown that
(13) where
(14) and
(15) With typical device parameters in 0.18- m CMOS
tech-nology, and are about and ,
respectively. More than 99.5% of comes from the second term in (13). Hence, can be approximated as
(16) where the effect of the induced gate noise, represented by in the above equations, can be ignored. From (16), has a
frequency-independent quality factor equal to . Hence, on the Smith chart, the curve roughly follows the constant- contour, different from the behavior of a physical
RC network.
The other noise parameters are easily obtained. The -pa-rameter representation of the noise factor is
(17)
Here, and are
Fig. 5. Equation verification ofZ and the analysis of discrepancy factor effects on Smith chart. Frequency swept from 1 to 20 GHz with 1-GHz step.
and
(19) Equation (19) corresponds to Fukui’s empirical equation of
[19]. We can see not only introduces -to-discrepancy, but also increases . is identified as a dominant noise contributor to an LNA. On the other hand, is derived as
(20) The accuracy of (13)–(15) was verified with several test cases by MATLABand Agilent ADS. The calculated ( -parameter of ) agrees closely with the simulated . Representative results are plotted in Fig. 5. In this test case, the component pa-rameters in the model of Fig. 2 were extracted from a 0.18- m NMOS transistor operated in strong inversion in the saturation region. These were applied to (13) and the model in Fig. 2 for the calculation and simulation, respectively. Noise from is not included in the test case. The simulation result employing the foundry noise model is also included as a reference. Different test conditions are applied to analyze the effect of different factors. As can be seen, the calculation result fits the simulation results very well. The curve behaves as a constant- curve, showing a strongly frequency-dependent , not matched to the curve. dominates the real part discrepancy, whereas induced gate noise has a marginal effect on .
Different values of are applied in Fig. 5 to show the effect of feedback on . It can be observed that is sig-nificantly affected by a resistive because of feedback, while is also slightly affected, as predicted by (20). In addition, if a reactive is applied, a capacitive provides an
additional noiseless resistance, whereas an inductive results in positive feedback, causing an unstable resonance. The former can be utilized for BSNIM as described in Section II-B. With ap-proximate equations (16), (18), and (19), one can quickly eval-uate transistor noise parameters of sufficient accuracy by ac sim-ulation or vector network analyzer (VNA) measurement results. By comparing and in (16) and (20), respectively, their differences are summarized as follows.
• For the real part, the noise contributed by makes much larger than by a frequency-dependent amount.
• For the imaginary part, with a resistive , the feed-back makes smaller than . When rep-resented by a series capacitance, the equivalent series ca-pacitance in is larger than that in .
An important insight, if noise from the succeeding stages is ignored, is that feedback changes only by its loading effect, whereas it changes due to feedback, as shown in (8) and (9). The same phenomenon applies to other lossless feedback topologies such as source inductive degeneration [14]. Hence, one can manipulate the difference between and with lossless feedback to achieve SNIM.
Another important consideration is the gain of the CS am-plifier. If it is not sufficiently high, the noise parameters will be significantly affected by the noise of succeeding stages. As shown in the Appendix, this increases as well as , and reduces the discrepancy between and . Care should be taken, noting that lower gain may degrade noise performance while satisfying the condition for SNIM.
B. Strategies to Achieve BSNIM
With the mechanism of -to- discrepancy identified, strategies to achieve BSNIM for minimized NF can be pursued. Since is smaller than , the difference can be compensated by introducing a noiseless resistance with a reac-tive feedback technique. It is critically important to minimize the series capacitance expansion of induced by and the real part of . From (20), it is necessary to meet the following condition:
and (21)
The proposed SNIM strategy first matches to the source impedance with the loading effect of the feedback compo-nents included, but without feedback loop gain, then to adjust the loop gain to match to without affecting and . Consider the source inductive degenerated LNA as an ex-ample. When matching to , make and combine the inductance of the source inductor to the gate matching inductor such that the loading effects of and are included, but the loop gain of and feedback are equal to zero. Then adjust and increase , with reduced corre-spondingly, to adjust the feedback loop gain to match to . The loop gain adjustment does not affect and .
For a narrowband LNA at frequency , the design criteria for SNIM are summarized as follows.
1) Apply the smallest channel length for the best transistor performance. From (19), increases roughly with
, which can usually be minimized with the shortest channel length.
2) The real part of should be as small as possible to avoid increasing the difference between and . This difference introduces a frequency offset between the impedance and noise matching.
3) Given a specified drain current, co-design the transistor size and matching network to make match to the source impedance at with the loading effect of feed-back components included.
4) Increase to match without adding noise and changing with appropriate lossless feedback. A well-known feedback technique is inductive source
degeneration.
For a prescribed dc drain current (power constraint), is adjusted by varying the transistor size. If the transistor size is increased, increases, decreases, and decreases. From (16) and (19), decreases, but increases. Nonetheless, the increase is generally insignificant com-pared to the noise factor improvement from noise matching.1 For applications of , this adjustment leads to an ex-tremely low transistor current density (biasing at weak inver-sion), which may increase sensitivity from process variation and degrade linearity. In this case, an external capacitor in parallel with the transistor to lower is an alternative choice. This increases slightly, but helps maintain noise matching with a transistor in moderate inversion.
For broadband applications, both and need to be close to over the entire bandwidth. A broadband response requires a high-order input matching network. Equation (16) and (20) show that the frequency dependencies of
and are different. Hence, the reactive feedback, as de-scribed in 4) above, needs to increase by a
frequency-dependent amount. This can be realized by employing multiple reactive feedback to make close to in dif-ferent frequency regions. Consequently, the design criteria for BSNIM are proposed as follows.
1) Same as above 1) in narrowband cases. 2) Minimize or employ a capacitive .
3) With the drain current specified, the transistor size is chosen to make of the transistor close to the source impedance at the center frequency of the passband. Apply a high-order input matching network (typically a ladder LC network structure) to make close to over the entire band.
4) Increase to match by employing multiple
re-active feedback.
While multiple reactive feedback is necessary for BSNIM, the loop gain actually results in a higher order impedance function of than that of such that and behave differently with frequency. Nevertheless, this difference can be accommo-dated with a high-order input matching network if both
and are designed close to in the passband. The procedure described above enables a BSNIM LNA design, which provides power-efficient noise performance. In
1If a large amount of dc power is applied such that theG in (20) is very
small, the noise matching is less critical for noise performance [6]. However, this is not the power efficient case that the SNIM approach strives for.
Fig. 6. Proposed BSNIM amplifier.
Section III, an exemplary dual reactive feedback technique is proposed as a BSNIM solution, which has been demonstrated to be effective for broadband LNA design from 3 to 11 GHz (fractional bandwidth larger than 130%). In comparison to the area-saving, but power-hungry, resistive/source-follower feedback amplifier [20]–[23], an SNIM/BSNIM LNA saves a considerable amount of power.
III. PROPOSEDBSNIM AMPLIFIER
As discussed above, a BSNIM LNA necessitates a high-order matching network and multiple reactive feedback networks. The proposed BSNIM solution is an LC-ladder matching network [24] along with a dual reactive feedback topology, composed of capacitive shunt feedback and inductive series feedback, as shown in Fig. 6. The LC-ladder matching network and the dual reactive feedback are co-designed following the BSNIM design criteria in Section II-B. Each feedback network attains SNIM in different frequency regions for BSNIM. They are seamlessly combined by employing an inductor at the transistor drain port to obtain different loading conditions for each feedback structure. To quantitatively illustrate the design concept, a 3.1–10.6-GHz UWB LNA designed in 0.18- m CMOS is employed as an example.
A. Proposed Dual Reactive Feedback Topology
The proposed dual reactive feedback structure and the LC ladder input matching network results in , represented by the equivalent circuit, as shown in Fig. 7. The -to-matching bandwidth is extended by the second-order bandpass
LC-ladder structure. The choice of component values follows
the guideline as
(22) where is located at 5.76 GHz, the geometric mean of 3.1 and 10.6 GHz in this design. Bandwidth expansion is determined by the L/C ratios, where the preliminary values can be obtained by traditional filter design such as a Chebyshev filter. Slight trim-ming of LC values can compensate for the frequency depen-dency of . For the optimal broadband matching result, is, in general, designed slightly less than to make the curve circling the Smith chart center over the entire passband. The design of and also takes into account the gain re-sponse, as will be described later.
While broadband noise matching is achieved, the input impedance is also matched to by the proposed dual reactive feedback circuit, as shown via the dashed-line box of Fig. 6. A similar circuit structure was demonstrated with broadband
Fig. 7. Equivalent-circuit presentation ofZ to the circuit in Fig. 6.
Fig. 8. Input impedance changed among the two feedbacks with frequency. (a) Capacitive shunt feedback in lower frequency region. (b) Inductive series feedback in higher frequency region.
input impedance matching [25]. In contrast to [25], the pro-posed approach here utilizes each reactive feedback in different frequency regions. This configuration can minimize the differ-ence between and over a wide frequency range, and therefore enable BSNIM. In the frequency region much lower than the series resonance frequency, the tank behaves like a capacitor to the transistor. Hence, can be represented by the equivalent circuit shown in Fig. 8(a), where
(23) (24) and
(25) Two noiseless resistances can be found: from the series inductive feedback of , and from the shunt capaci-tive feedback of with . Since in (25) is usually much larger than , the branch of dominates the input impedance in this frequency region such that is the noise-less resistance contributing to to match with .
In the higher frequency region close to the reso-nance, the output appears as a short circuit at the drain. can be represented by the equivalent circuit, as shown in Fig. 8(b). The branch becomes open because the feedback loop
Fig. 9. Gain response of the circuit with dual reactive feedback in Fig. 6. The low-frequency gain is suppressed byL and the high-frequency gain is en-hanced byL .
gain is approximately zero. The series inductive feedback is sig-nificant under this condition and is the dominant noiseless resistance in this frequency region.
As shown in (16), of the transistor is inversely propor-tional to frequency. Its variation is larger than 70% over the entire frequency range of interest. To make match with , is designed to be about half of , accommo-dating the required variation. In practice, the branch in Fig. 8(a) has a low- property such that the capac-itive feedback is active over a larger portion of the frequency range.
The choice of , , and is made in consideration of , making close to over the entire frequency range. In practice, results in two resonance frequencies with the transistor circuit. At low frequencies, and consti-tute a resonance tank with the resonance frequency of
(26) For the inductive feedback, the resonance frequency is located at a higher frequency
(27) Therefore, the frequency dependence of turns out to be an order higher than that of . In this design and are located at 5 and 9 GHz, respectively. As to the choice of , it is expected to tune out to accommodate the inductive feedback (28) As the input matching is sensitive to the output impedance with feedback, the proposed BSNIM amplifier is not uncon-ditionally stable. An unwanted resonance could occur whereas behaves inductive at frequency higher than . This can be controlled by making a quality factor of network lower than a certain value. Here, is the effective output resis-tance of the transistor to be discussed in Section III-B. Mean-while, a good output-to-input isolation should be provided in the succeeding stage for good overall stability. To meet this re-quirement, we employ a cascode amplifier as the second stage, as will be shown in Section IV.
B. Gain Response
As mentioned in Section II-A, a sufficiently high gain over the entire band is necessary to reduce the noise contribution of succeeding stages. The proposed BSNIM amplifier is expected
Fig. 10. Equivalent circuit for gain derivation atf .
to fulfill this gain requirement. This design concept is shown in Fig. 9. The gain response is mainly shaped by the drain network in Fig. 6 as the input network is a broadband structure. Based on the low-pass response by (the gray curve in Fig. 9), creates series gain peaking at the frequency
(29) which is higher than in (27). The voltage gain at this fre-quency can be derived with the circuit approximation, as shown in Fig. 10, where is the effective output resistance of the tran-sistor at frequency higher than as
(30) The gain in the lower out-of-band frequency is suppressed by the input shunt inductor . As a result, a gain peak is formed at the lower band edge. The magnitude of this peak is designed close to the peak gain at the higher band edge such that the ex-pected gain response is the solid curve in Fig. 9. With this design approach, the voltage gain is determined at , which is de-signed at 11 GHz.
The gain response of this amplifier is composed of the two gain peaks at both band edges. If a flat gain over a very wide bandwidth is desired, an additional mid-band gain peak by the next stage is necessary to compensate the mid-band sag. This case applies to our 3–11-GHz UWB LNA. On the other hand, if the required bandwidth is moderate, such as the 2–6-GHz ap-plication in [18], a flat gain response is obtainable by this stage itself as the two gain peaks can be designed fairly close to each other.
C. Transformer for Inductive Series Feedback
The proposed dual reactive feedback amplifier, as shown in Fig. 6, requires four inductors that may occupy a large die area. To reduce the inductor number and die area, transformer feed-back is proposed to replace the three inductors , , and , as shown in Fig. 11(a). With transformer feedback, and overlap, sharing the same die area with mutual inductance to constitute a transformer. The mutual inductance senses the drain current and contributes series voltage feedback at the input similar to the series-series feedback function of in an inductive source degenerated amplifier. By neglecting the feedback effect and the transformer feed-forward coupling at the frequency of interest, the input impedance can be approximately represented by the equivalent circuit, as shown in Fig. 11(b), in
which and
(31)
Fig. 11. (a) Inductive source degeneration feedback can be substituted by the transformer feedback. (b) Their equivalent circuit for input impedance.
Fig. 12. Proposed dual reactive feedback amplifier with transformer feedback.
which provides the wanted noiseless resistance similar to in (23). The above assumption is valid for the general source inductive degenerated amplifier design.
This transformer feedback topology is also beneficial in that the transistor source is connected to ground directly. This allows the amplifier to be implemented with a CMOS inverter structure, which employs both NMOS and PMOS to reuse drain current for high transconductance. The final schematic diagram of the proposed BSNIM amplifier is shown in Fig. 12. Here, the mu-tual inductance is represented by the coupling factor with the
relation .
Since is generally much smaller than and , the cou-pling factor is much smaller than 1. Design simulations show that the optimal value is slightly less than 0.2. Possible layout schemes that facilitate a weakly coupled transformer include common-centric coils and overlapped coils, as shown in Fig. 13. Generally, the common-centric coils have a better quality factor, but occupy more die area. In the design example in Section IV, the common-centric coil was adopted for better performance.
IV. DESIGNEXAMPLE: 3–11-GHz UWB LNA A design example of a 3–11-GHz UWB LNA employing the proposed BSNIM amplifier is shown in Fig. 14 [16]. In this pro-totype design, the inverter amplifier is self-biased with a 10-k feedback resistor. of plays the role of in Fig. 12. between and further increases the gain peak at the higher band edge. The body of is biased to its source with a 10-k resistor. and provide voltage gain with a low- peak at the center frequency to compensate the mid-band gain dip by the first stage. and constitute the
Fig. 13. Possible layout schemes of a weak coupling transformer. (a) Common-centric coil. (b) Overlapping coil.
Fig. 14. 3–11-GHz UWB LNA as a design example of the proposed BSNIM amplifier.
TABLE I
DEVICEVALUES OF THE3–11-GHz UWB LNA
Note: The values here are of the practical devices, which in some degree deviate from the theoretical values with the device parasitic effects.
output buffer and the 0.1-nH output inductor improves the 50-output match. The detailed design parameters of the devices are listed in Table I.
Simulation were performed with Agilent Technologies’ Advanced Design System (ADS). and of the LNA is shown on the Smith chart on the left side of Fig. 15. On the right side of Fig. 15 is the result without and to show how the dual reactive feedback enables BSNIM.
can be observed to decrease as the frequency increases. At low frequencies, the plot shows that appears close to over a large frequency range, but begins to deviate around 7.5 GHz. The resonance due to the transformer feedback helps reduce this deviation. As shown in the plot, however, the improvement is limited to a small frequency region up to 11 GHz.
and in the higher frequency region are slightly larger than the expected because of the parasitic capacitance of . With the addition of and , the order of matching network is increased such that and both move toward the center of Smith chart, achieving broadband matching. With this high-order matching network, the noise
Fig. 15. On the left is the simulatedS and S of the designed UWB LNA. The bold face section of each curve represents the results in frequency range from 3 to 11 GHz. On the right is the result withoutL and C .
Fig. 16. Gain response trimming in the second stage. a: High-band expansion byL . b: Mid-band compensation by L and R . The bold black curve is the expected result.
matching and input matching performance are also robust with process variations.
The second stage of the LNA is a CS–common gate (CG) cas-code amplifier providing output-to-input isolation for the good circuit stability. It also compensates the LNA gain for a flat in-band response: further peaks the gain response at the higher band edge with series peaking, and and provide low- shunt peaking at mid-band, as shown in Fig. 16. The third stage is an output buffer.
This LNA was designed in a TSMC 0.18- m CMOS process with aluminum metal. It was designed to achieve 15-dB re-turn loss, 4-dB maximum in-band NF, 10-dB power gain with less than 0.5-dB in-band variation, and 0.1-ns maximum group-delay variation while consuming 10 mW of power from a 1.5-V supply. The broadband noise performance is mainly limited by the input matching network where the resistive losses substantially increase .
Figs. 17–20 show the simulation and measurement results. Also included are the post-layout simulation results with the transistor model in the slow–slow (SS) corner, which are found closer to the measured results. Fig. 17 shows the measured and from an ATN NP-5 noise parameter analysis system. Both have good in-band matching to 50 . Fig. 18 shows the power gain . The measured closely matches simula-tions with a transistor model from the SS corner, but is about 5-dB lower than that in the typical–typical (TT) corner. The NF and circuit minimum NF are shown in Fig. 19, where the NF is very close to in the passband. The measured in-band NF is less than 5 dB. Fig. 20 shows the noise param-eter . As can be observed in Figs. 19 and 20, the broadband noise matching maintains the NF even as varies. The
mea-Fig. 17. Measured and simulatedS and S .
Fig. 18. Measured and simulatedS . The simulation is with the transistor model of the SS corner.
Fig. 19. Measured and simulated NF andNF . The simulations are with the transistor model of the SS corner.
Fig. 20. Measured and simulatedR .
sured third-order intermodulation intercept point (IIP3) is about 12 dBm. Linearity is degraded by the voltage gain of the first stage driving the gate of (Fig. 14). The power consumption without the output buffer is 9 mW from a 1.5-V supply. The per-formance is summarized and compared with other UWB LNAs
in Table II. The simulation and measurement results validate the proposed BSNIM solution.
V. CONCLUSION
The SNIM technique is important for power-efficient noise performance of an LNA. A successful approach for broadband simultaneous noise and impedance matching (BSNIM) on a CS amplifier has been demonstrated. The root causes of -to-discrepancy of a MOS transistor were analyzed and the SNIM/ BSNIM design criteria were proposed. Reactive feedback to equalize the real part of and are essential for SNIM. The proposed BSNIM technique employs dual reactive feed-backs and an LC ladder matching network to accommodate a wide bandwidth. Band handover between the two reactive feed-back paths is facilitated by a drain inductor . Transformer feedback is employed to provide the same series-series feed-back with a reduced die area.
The design example of a 3–11-GHz UWB LNA shows a ro-bust BSNIM condition is achieved for an application having over 130% fractional bandwidth. The noise contribution of the nonideal input matching network is found to be as significant as that of the transistor. The low NF up to 11 GHz is maintained on a 0.18- m CMOS process. Another design example in 0.13- m CMOS [18] also shows the benefit of low power and low noise employing the proposed BSNIM technique.
APPENDIX
The input-referred noise sources are obtained by calculating the corresponding output noise voltages for a short-circuited input and the open-circuited input cases, and then divide them by the signal gain to obtain the input-referred voltage and cur-rent noise sources, respectively [26]. This method, however, makes the equations very complicated, making the effects of device components on , as well as the correlation of equiv-alent noise sources, confusing.
The noise analysis developed in this study includes noise model simplification and the equivalent noise source conver-sion. The model simplification is for a CS amplifier with noise-less feedback networks, as illustrated in Fig. 21(a), in which and contribute no noise. is the equivalent voltage noise source at the gate representing the noise contribution from and , where the latter is a drain-referred noise current source of the succeeding stages,2including the noise by . is equal to
(A1)
Here, is equal to , where is the
equivalent feedback transimpedance of the total feedbacks from drain current to gate voltage via and . With , the noise model in Fig. 21(a) can be simplified to the model in Fig. 21(b) by simply observing that and load the transistor gate, where is in series and is in
2By the two-port noise theory, noise contribution of the succeeding stages can
be represented as a pair of correlated voltage and current noise sources at output of the CS-Amp. With the given output impedance (Z and C ), the two noise sources can be further merged as one current noise sourcei .
TABLE II
COMPARISON OFBROADBANDLOW-NOISECS AMPLIFIER
Differential LNA.
Fig. 21. Developed simplification technique for noise parameters deriva-tion. (a) General case for the CS amplifier with lossless feedback networks. (b) Equivalent circuit for noise analysis.
parallel with . This is based on the principle that the equiv-alent input referred noise sources of a feedback amplifier are equal to those of same amplifier with the feedback loop opened [26]. In our derivation of the input-referred voltage and current noise sources with the input shorted and opened, respectively, this simplification is valid with the condition that
and , which is usually satisfied.
With this simplified model, the derivation of input referred noise sources can simply start from the input of the voltage-con-trolled current source, i.e., in Fig. 21(b). When this model is applied to the transistor noise model in Fig. 2, plays the role of , is equal to 0, and is not included. The effect of will be discussed at the conclusion of this Appendix. Note that the equivalent circuit in Fig. 21(b) is only for noise analysis and should not be used for input impedance analysis.
When referring these noise sources in Fig. 21(b) to the input, the equivalent noise source conversion, a derivative concept from the equivalent noise four-poles [27], can be applied. As shown in Fig. 22(a), the shunt current noise source after a passive device in series with the input port has input-re-ferred noise sources including the original and a series
Fig. 22. Two elementary cases of equivalent noise sources conversion over pas-sive devices: (a) in series and (b) in parallel to the input port.
voltage noise source fully correlated to , whereas the series voltage noise source remains unchanged at the input. The total input-referred voltage noise source can be obtained by combining and . Note that the direction of the noise sources in Fig. 22 carries the correlation information between noise sources. In comparison with [27], the opposite direction of current sources is adopted such that the correlation factor is positive when is resistive.
and should be combined by employing the 3-D vector operation, as shown in Fig. 23. Assume any vector along the direction of unit vector is uncorrelated to , then can be seen as a combination of two orthogonal vectors: one along and the other on the -plane, a complex plane perpen-dicular to . Any complex vector on the -plane is fully corre-lated to . Here, is defined as the direction in phase with
Fig. 23. 3-D vector operation to combine the two partially correlated voltage noise sources in Fig. 22(a).
. The correlation factor between and is equal to , in which is the absolute value of the cor-relation factor and is the phase difference between and , as shown in Fig. 23. In Fig. 23, all the ’s and are on the -plane. After the vector addition of and , the total input-referred noise voltage can be obtained with the correlation to equal to , where is the phase difference between and .
The equivalent noise source conversion for a passive device in parallel with the input port can be derived in the same manner as shown in Fig. 22(b). The noise contribution from and in Fig. 22 can be included in and , respectively. By alternately applying conversions as in Fig. 22(a) and (b), the input referred noise sources can be obtained. Noise parameters such as , (or , ), and can be derived with the two-port noise theory introduced in [1].
The effect of on noise parameters depends on the feed-back, as shown in (A1) with . The more feedback, represented by the larger , results in the lower gain of LNA and the less attenuation of noise from the succeeding stages, yields to the larger . One can replace in
(13)–(19) with to
in-clude into the noise parameters. It is found that both and increase and , and decrease . The de-crease of reduces the discrepancy between and . We observe that feedback loop gain affects noise parame-ters only when is included in the analysis because is outside the feedback loop. Nonetheless, if the CS amplifier has sufficiently high gain such that the effect of is negligible compared to , the loop gain has almost no effect on the noise parameters.
ACKNOWLEDGMENT
The authors wish to thank the National Center for High-Per-formance Computing (NCHC), Hsinchu, Taiwan, for software support, the Chip Implementation Center (CIC), Hsinchu, Taiwan, for software support and chip fabrication and the Radio Frequency Technology Center (RFTC), National Nano Device Laboratory (NDL), Hsinchu, Taiwan, for measurement.
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Chang-Tsung Fu (S’00–M’09) received the B.S.
de-gree in communication engineering, and the M.S. and Ph.D. degrees in electrical engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1996, 2001, and 2009, respectively. His doctoral research concerned broadband low-noise amplification theory and circuit techniques for RF front-ends.
In 2006, he was with the Intel Corporation, Hills-boro, OR, as an Intern, during which time his research was focused on CMOS WiFi T/R switch design. He is currently with the Intel Laboratory, Intel Corpora-tion, as a Research Scientist dedicated to pathfinding wireless front-end design in advanced CMOS technology.
Chien-Nan Kuo (S’93–M’97) received the B.S.
degree in electronic engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1988, the M. S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1990, and the Ph.D. degree in electrical engineering from the University of California at Los Angles (UCLA), in 1997.
In 1997, he joined ADC Telecommunications, San Diego, CA, as a Member of Technical Staff with the Mobile System Division, where he was involved in wireless base-station design. In 1999, he joined Broadband Innovations Inc.
In 2001, he joined the Microelectronics Division, IBM. In 2002, he joined the faculty of National Chiao Tung University, Hsinchu, Taiwan, as an Assistant Professor. His research interests include reconfigurable RF circuit and system integration design, low-power design for the application of wireless sensor net-works, and development of circuit-package co-design in the system-in-package (SiP) technique.
Dr. Kuo was the recipient of the Best Paper Award presented at the 13th IEEE International Conference on Electronics, Circuits, and Systems in 2006.
Stewart S. Taylor (S’74–M’77–SM’99–F’08) received the Ph.D. degree in electrical engineering from the University of California at Berkeley, in 1978.
He is a Senior Principal Engineer with the Intel Laboratory, Intel Corporation, Hillsboro, OR, where he has been since January 2003. His current research focus is on radio architecture and circuit design that leverages the strengths and compensates for the weaknesses of CMOS technology. Prior to joining the Intel Corporation, he was with Tektronix, TriQuint, and Maxim. He has taught part-time at Portland State University, Oregon State University, and the Oregon Graduate Institute for 30 years, and has served on the graduate committees of seven Ph.D. students. He has authored or coauthored over 50 publications. He holds 51 patents with 17 pending.
Dr. Taylor served on the Program Committee of the International Solid-State Circuits Conference for ten years, chairing the Analog Subcommittee for four years. He was the conference program chair in 1999. He was an associate ed-itor of the IEEE JOURNAL OFSOLID-STATECIRCUITS. He was the recipient of the IEEE Third Millennium Medal for Outstanding Achievements and Contri-butions from the IEEE Solid-State Circuits Society.
