Design of Compact ESD Protection Circuit for
V-Band RF Applications in a 65-nm
CMOS Technology
Chun-Yu Lin, Member, IEEE, Li-Wei Chu, Student Member, IEEE,
Shiang-Yu Tsai, and Ming-Dou Ker, Fellow, IEEE
Abstract—Nanoscale CMOS technologies have been widely used
to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, an on-chip ESD protection design must be included in the RF circuits. As the RF circuits operate in the higher frequency band, the parasitic effect from ESD protection circuit must be strictly limited. To pro-vide the effective ESD protection for a 60-GHz low-noise amplifier with less RF performance degradation, two new ESD protection circuits were studied in a 65-nm CMOS process. Such compact ESD protection circuits have been successfully verified in silicon chip to achieve the 2-kV human-body-model ESD robustness with the low insertion loss in small layout area. With the better perfor-mances, the proposed ESD protection circuits were very suitable for V-band RF ESD protection.
Index Terms—CMOS, electrostatic discharge (ESD) protection,
radio frequency (RF), V-band.
I. INTRODUCTION
A
S CMOS technologies advanced, the radio-frequency (RF) integrated circuits have been widely designed and fabricated in CMOS processes due to the advantages of high integration and low cost for mass production [1]–[3]. However, nanoscale CMOS technologies seriously degraded the electro-static discharge (ESD) robustness of integrated circuits. ESD protection must be taken into consideration during the design phase of integrated circuits, especially the RF circuits [4], [5]. In the RF circuits, the input and output pads are usually connected to the gate terminal or silicided drain/source ter-minal of the metal–oxide-semiconductor field-effect transistor (MOSFET), which leads to a very low ESD robustness if noap-Manuscript received September 26, 2011; revised February 7, 2012; ac-cepted February 9, 2012. Date of publication February 17, 2012; date of current version August 30, 2012. This work was supported in part by Taiwan Semiconductor Manufacturing Company, Ltd., by National Science Council, Taiwan, under Contract NSC 100-2221-E-009-048, and by the “Aim for the Top University Plan” of National Chiao Tung University and Ministry of Education, Taiwan.
C.-Y. Lin, S.-Y. Tsai, and M.-D. Ker are with the Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: cy.lin@ieee.org; mdker@ieee.org).
L.-W. Chu is with the Department of Photonics and Display Institute, National Chiao Tung University, Hsinchu 30010, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TDMR.2012.2188405
Fig. 1. Conventional ESD protection design with double diodes and power-rail ESD clamp circuit for LNA.
propriate ESD protection design is applied. Once the RF circuit is damaged by ESD event, it cannot be recovered and the RF functionality is lost. Therefore, on-chip ESD protection design must be provided for all input and output pads in RF circuits.
Adding ESD protection causes RF performance degradation with several undesired effects [6]–[9]. Parasitic capacitance of ESD protection device is one of the most important design con-siderations for RF circuits. A typical specification for a giga-Hz low-noise amplifier (LNA) on human-body-model (HBM) ESD robustness and the maximum parasitic capacitance of ESD protection device are 2 kV and 200 fF, respectively [9]–[11]. As the operating frequencies of RF circuits increase, the parasitic capacitance was more strictly limited. In order to fulfill such a tight specification, diodes had been commonly used for RF ESD protection [12]. The conventional double-diode ESD protection design for LNA is shown in Fig. 1, where two ESD diodes (DP and DN) at input pad are assisted with the power-rail
ESD clamp circuit to prevent LNA from ESD damage [13]. When DP and DN are under forward-biased condition, they
can provide efficient discharging paths from input pad to VDD
and from VSS to input pad, respectively. Besides, the
power-rail ESD clamp circuit provides the ESD current paths between
VDDand VSS.
The conventional ESD protection circuit in Fig. 1 can provide the corresponding current discharging paths under ESD events. Under positive-to-VDD mode (PD-mode) and negative-to-VSS
mode (NS-mode) ESD stresses, ESD current is discharged through the forward-biased DPand DN, respectively. To avoid
the ESD diodes from being operated under breakdown condi-tion under positive-to-VSS mode (PS-mode) and negative-to-VDD mode (ND-mode) ESD stresses, which results in
sub-stantially lower ESD robustness, the power-rail ESD clamp circuit is applied between VDDand VSSto provide ESD current
paths between the power rails. Thus, ESD current is discharged from the input pad through the forward-biased DP to VDD,
and discharged to the grounded VSS pad through the turn-on
efficient power-rail ESD clamp circuit during PS-mode ESD stresses. Similarly, ESD current is discharged from the VDDpad
through the turn-on efficient power-rail ESD clamp circuit and the forward-biased DN to the input pad under ND-mode ESD
stresses.
To mitigate the performance degradation caused by ESD protection devices, some design techniques had been developed to reduce the parasitic capacitance of ESD protection devices [14]. The parasitic capacitance of ESD protection devices can be tuned out by using inductors [15]–[17]. The Inductors exhibit higher impedance at higher frequencies, and they can block the RF signals [18]. The ESD protection circuit with reduced parasitic capacitance can be easily combined or co-designed with RF circuits [19], [20]. In this paper, two new designs of the compact ESD protection circuits for V-band RF applications are proposed [21]. Such ESD protection designs have been implemented in cell configuration and reached 50-Ω input/output matching, which can be directly applied to the 60-GHz RF LNA. Therefore, the proposed ESD protection cell in this paper is suitable for RF circuit designer for them to easily apply ESD protection for V-band RF applications.
This paper consists of six Sections. The impacts of ESD protection on RF performance of LNA are calculated in Section II. The proposed ESD protection designs are presented in Section III. The circuit realization and measurement results in silicon are presented in Section IV. The simulation results of appling the proposed ESD protection circuit to a 60-GHz LNA are presented in Section V. Section VI concludes this work.
II. IMPACTS OFESD PROTECTION ONRF PERFORMANCE
In the circuit of Fig. 1, the parasitic effects of ESD protection diodes caused RF performance degradation. Some equations can be calculated to describe this condition [22]. The insertion loss of ESD protection diodes (ILESD) can be expressed as
ILESD= 1 + Z0 2ZESD =S21,ESD1 (1) where Z0 is the 50-Ω normalization impedance, and ZESD is
the parasitic impedance of ESD protection diodes. Using the expression in dB, the insertion loss (ILESD) is equal to the
absolute value of S21-parameter (S21,ESD).
Fig. 2. LNA with parasitic impedance of input pad and ESD protection diodes for calculating the power gain.
The power gain of an RF LNA with the parasitic effects of ESD protection device has been calculated from the schematic circuit diagram, as shown in Fig. 2. A simple expression for the input impedance (Zin,LNA) of the inductively degenerated
LNA at resonance is Zin,LNA= s(Ls+Lg)+ 1 sCgs + gm Cgs Ls≈ωTLs= Z0 (2)
where ωT is the unity-gain frequency of the MOS transistor.
The overall input impedance (Zin) of the RF LNA with ESD
protection diodes is
Zin= ZESD//Zin,LNA≈ ZESD//Z0. (3)
Therefore, the overall transconductance (Gm) of the LNA is
Gm= ZESD ZESD+ Z0 ωT s(Z0+ Zin) = ωT sZ0 1 2 + Z0 ZESD . (4)
To analyze the overall power gain of the LNA, the feedback capacitor Cgd of the MOS transistor was neglected first, and
the input and output were assumed to be conjugately matched to get a simpler expression for the power gain. The transducer power gain (GT) is GT = PL Pavs = 1 8|VsGm|2(Ro//Z0) 1 8 |Vs|2 Z0 = ω 2 T(Ro//Z0) 4ω2 oZ0IL2ESD (5)
where PL is the average power delivered to the load, Pavs is
the average power available from the source, Rois the output
impedance of the cascoded NMOS transistors, and ωo is the
operating frequency of input RF signal. From (5), the insertion loss of ESD protection is disadvantageous to the transducer power gain of LNA. Therefore, ESD protection circuit with low insertion loss is needed for RF applications.
Fig. 3. Proposed ESD protection design A and power-rail ESD clamp circuit.
If the parasitic impedance of ESD protection diodes (ZESD)
can be increased, the power gain of the RF LNA can be improved. The device dimensions of ESD protection diodes should be reduced to decrease (increase) the parasitic capaci-tance (resiscapaci-tance), which in turn reduces RF performance degra-dation caused by the parasitic impedance of the ESD protection diodes. However, ESD robustness needs to be maintained, so the minimum device dimensions of ESD protection diodes cannot be shrunk unlimitedly. The parasitic impedance of the ESD diodes, even with limited device sizes, still generates the
ZESDinto above equations.
As the operating frequency of RF circuits increases, the
ZESDwill be decreased due to capacitive component. As ZESD
decreases, the insertion loss in (1) will be increased, and the transducer power gain in (5) will be decreased. Therefore, how to design an effective on-chip ESD protection circuit for RF circuits operating in higher frequency bands with minimum RF performance degradation is a challenge, which must be solved for safe mass production of RF integrated circuits.
III. PROPOSEDESD PROTECTIONDESIGNS
Fig. 3 shows the circuit of one proposed ESD protection design, where a pair of the ESD protection diodes (DPand DN)
and a series inductor and capacitor (LN and CN) are placed
beside the input pad. The ESD protection diodes provide the ESD current paths between input and VDD/VSS. The power-rail
ESD clamp circuit is also needed to provide the ESD current paths between VDDand VSS.
The inductor in series with the capacitor can block the dc leakage path from input pad to VSS under normal circuit
operating conditions. Besides, the series inductor and capacitor are designed to resonate at low frequency. As the frequency is lower (higher) than the resonant frequency of the series inductor and capacitor, the capacitance (inductance) dominated the impedance. The equivalent inductance of the series inductor and capacitor (Leq) can be expressed as
Leq= LN −
1
ω2C
N
. (6)
At operating frequency of input RF signal, the inductance (Leq) can be used to eliminate the parasitic capacitance of ESD
protection diodes (CDiodes).
The resonant frequency of parallel Leqand CDiodes, which
is designed to be the operating frequency of RF circuit, can be obtained by ωo= 1 LeqCDiodes . (7)
From (6) and (7), the equations can be held once the inductor, capacitor, and ESD protection diodes satisfy
ωoLN− 1 CN = 1 CDiodes . (8)
Once the design parameters have been chosen, including the size of ESD protection diodes and operating frequency of RF circuit, the required inductor and capacitor for resonation can be calculated. Therefore, the RF input port will see a large impedance from the ESD protection circuit (ZESD), where the
parasitic capacitance (CDiodes) has been eliminated, and the
parasitic resistance (RDiodes) remains large.
To reduce the inductance used in LN, another supplement
capacitor (CS) can be added between RF input and VSS. In
other words, the parasitic capacitance of ESD protection diodes (CDiodes) is increased by adding the parallel capacitor (CS). It
is better to add the supplement capacitor rather then increase the diode size, because the supplement capacitor provides a purely capacitive device, while increasing diode size lowers the parasitic resistance, which leads to the lower parasitic impedance and higher insertion loss. With this structure, the LN
with smaller radius can be used to reduce the cell area. Since the CDiodes depend on the required ESD robustness, the sizes
of CN and CScan be designed to optimize the cell area and RF
performances.
The power-rail ESD clamp circuit, which consists of the RC-inverter-triggered NMOS, is used to provide ESD current paths between VDDand VSSunder ESD stress conditions. The R1 (∼10 kΩ) and C1 (∼10 pF) with the time constant of
0.1 µs∼ 1 µs can distinguish the ESD transients from the normal circuit operating conditions. The NMOS (MESD) with ∼2000-µm width is used as the main ESD clamp device. As
positive ESD stress from VDD to VSS, the large-sized NMOS
(MESD) is turned on to provide ESD current path from VDDto VSS. As negative ESD stress from VDD to VSS, the parasitic
diode in large-sized NMOS (MESD) also provides the ESD
current path from VSSto VDD. Since the power-rail ESD clamp
circuit is placed between VDDand VSS, it does not contribute
parasitic effects to RF input port.
As the ESD stress to the input pin of RF LNA, the ESD current path of PD-mode (NS-mode) consists of one ESD protection diode DP (DN). Besides, the PS-mode (ND-mode)
ESD current is discharged through the DP (DN) and the
power-rail ESD clamp circuit.
Fig. 4 shows the circuit of another proposed ESD protection design. A pair of the ESD protection diodes (DP and DN) is
Fig. 4. Proposed ESD protection design B and power-rail ESD clamp circuit.
Fig. 5. Simulated S21-parameter of proposed design.
and capacitor (LP and CP) are placed between RF input and
VDD. The operation of proposed design B is similar to that of
proposed design A. The design parameters can be calculated by
ωoLP− 1 CP = 1 CDiodes . (9)
The proposed designs are simulated by using the ideal de-vices. A 0.11-nH inductor and a 300-fF capacitor are used for the series inductor and capacitor. The ESD protection diodes are simplified to be an 80-fF capacitor. Since the ideal devices are used, the proposed designs A and B have the same sim-ulation results. The simulated S21-parameter (S21,ESD) of the
proposed design is shown in Fig. 5. The S21value at 60 GHz
can be designed to be 0 dB, which means that insertion loss from ESD protection circuit is also 0 dB.
IV. VERIFICATION INSILICON
A. Test Circuits
The test circuits of the proposed ESD protection designs have been fabricated in a 65-nm CMOS process. Both proposed designs are split to 4 test circuits with different sizes of ESD protection diodes. The device dimensions of the test circuits
Fig. 6. RF-NMOS emulator to verify ESD robustness of proposed ESD protection designs.
Fig. 7. Layout top view of test circuit A4.
are listed in Table I. The width of DP or DN in test circuits
A1 (B1), A2 (B2), A3 (B3), and A4 (B4) are split as 8, 15, 23, and 30 µm, respectively, while the length of DP or DN
are kept at 0.6 µm. In this configuration, the CDiodes of test
circuits A1 (B1), A2 (B2), A3 (B3), and A4 (B4) are 21 fF, 40, 61, and 80 fF, respectively. The LN and LP are chosen as
0.11 nH for designs A and B. Therefore, the CN and CP are
designed as 300 fF, and the CSwith 60, 40, and 20 fF are added
to the test circuits A1 (B1), A2 (B2), and A3 (B3), respectively. To facilitate the on-wafer RF measurement, one set of these test circuits are arranged with G–S–G style in layout. Be-sides, another set of the test circuits are implemented with the RF-NMOS emulator [23], as shown in Fig. 6. The ESD ro-bustness of ESD-protected RF circuits can be estimated by the ESD protection design with RF-NMOS emulator. All test circuits have been fabricated for RF and ESD verifications. Part of the layout top view of one test circuit is shown in Fig. 7. The test circuit A4 with 0.11 nH LN, 300 fF CN, and
30× 0.6 µm2 D
P (DN) is drawn in a compact layout area of
130× 100 µm2. The same layout areas are used to draw the
other test circuits, since almost same components are used in every test circuits.
B. RF Performances
With the on-wafer measurement, the RF characteristics of the test circuits have been extracted. The two-port S-parameters of the test circuits from 0 to 67 GHz were measured by using the vector network analyzer. During the S-parameter measurement, the port 1 and port 2 were biased at 0.5 V, which is VDD/2
in the given 65-nm CMOS process. The dc bias of 1-V VDD
TABLE I
DEVICEPARAMETERS OFPROPOSEDESD PROTECTIONDESIGNS
Fig. 8. Measured S21-parameters of proposed design A within (a) 0–67 GHz and (b) 57–63 GHz.
intrinsic characteristics of the test circuits in high frequencies, the parasitic effects of the G–S–G pads have been removed by using the de-embedding technique [24]. The source and load resistances to the test circuits are kept at 50 Ω.
Fig. 9. Measured S21-parameters of proposed design B within (a) 0–67 GHz and (b) 57–63 GHz.
The measured S21-parameters versus frequencies among the
test circuits are shown in Figs. 8 and 9. As shown in Fig. 8, the proposed design A can reduce the insertion loss at designed frequency band. The insertion loss of the proposed design
TABLE II
COMPARISON ONEXPERIMENTALRESULTSAMONGESD PROTECTIONCIRCUITS INSILICON
Fig. 10. Dependence of HBM ESD robustness and measured S21-parameters at 60 GHz of ESD protection circuits on different DP or DNsize.
cannot be ideally 0 dB, since the parasitic resistance of ESD protection diodes (RDiodes), which cannot be eliminated by
inductance, also loses the RF signals. At 60 GHz, the test circuits A1, A2, A3, and A4 have about 1.3, 1.4, 1.6, and 1.8-dB insertion loss, respectively, which are summarized in Table II. Table II also lists the measured S11-parameters. All test circuits
exhibit good input matching (S11<−15 dB) at 60 GHz.
The proposed design B can also reduce the insertion loss at 60 GHz, as shown in Fig. 9. At 60 GHz, the test circuits B1, B2, B3, and B4 have about 1.4, 1.6, 2.0, and 2.3-dB insertion loss, respectively. The slightly increased insertion loss in this design may be due to the more complex metal routing in layout when the series inductor and capacitor connected to VDD.
Under the same bias condition, the noise figures of the ESD protection cells are measured around 60 GHz. At 60 GHz, the
Fig. 11. Simulation results on (a) S11-parameters, and (b) S21-parameters, of 60-GHz LNA with and without ESD protection.
test circuits A1, A2, A3, and A4 (B1, B2, B3, and B4) have 0.9, 1.2, 1.6, and 2-dB (0.9, 1.3, 1.7, and 2.2-dB) noise figures, respectively.
C. ESD Robustness
ESD robustness of the ESD test circuits with RF-NMOS emulators are evaluated by the ESD tester. The ESD pulses are stressed to each test circuit under PS-mode, PD-mode, NS-mode, and ND-mode ESD stress conditions. The failure criterion is defined as the I–V characteristics seen at RF input shifting over 30% from its original curve after ESD stressed at every ESD test level. The PS-mode, PD-mode, NS-mode, and ND-mode human-body-model (HBM) ESD robustness of all ESD test circuits are measured, as listed in Table II. The HBM ESD robustness of all ESD test circuits can be obtained from the lowest level of PS-mode, PD-mode, NS-mode, and ND-mode ESD robustness. The test circuits A1, A2, A3, and A4 (B1, B2, B3, and B4) have 0.25, 1.25, 1.75, and 2-kV (0.25, 1, 1.75, and 2.25-kV) HBM ESD robustness, respectively.
To investigate the turn-on behavior and the I–V character-istics in high-current regions of the ESD protection cells, the transmission line pulsing (TLP) system with a 10-ns rise time and a 100-ns pulse width is used. The secondary breakdown current (It2), which indicated the current-handling ability of
ESD protection circuit, can also be obtained from the TLP-measured I–V curve. Under PS-mode stress, the test circuits A1, A2, A3, and A4 (B1, B2, B3, and B4) can achieve It2
of 0.4, 0.9, 1.2, and 1.4 A (0.4, 0.7, 1.2, and 1.5 A), re-spectively. To evaluate the effectiveness of the ESD protection cells in faster ESD-transient events, another very fast TLP (VF-TLP) system with 0.2-ns rise time and 1-ns pulse width is also used in this study. The test circuits A1, A2, A3, and A4 (B1, B2, B3, and B4) can achieve VF-TLP-measured It2 of
0.8, 1.5, 1.8, and 2.0 A (0.8, 1.2, 1.8, and 2.1 A), respectively.
D. Comparison
The HBM ESD robustness and the measured S21-parameters
at 60 GHz of the proposed ESD protection designs are com-pared in Fig. 10. Among the proposed designs A and B, the test circuit A4 (B4) can achieve 2-kV HBM ESD robustness with 1.8-dB (2.3-dB) insertion loss.
The comparison among the proposed designs A and B and the reference design [25] is also provided in Table II. The layout area of the proposed designs can be significantly reduced from 110× 220 µm2to 100× 130 µm2. Besides, the test circuit A4
can also provide the required 2-kV HBM ESD robustness with the low insertion loss. Therefore, the compact ESD protection circuit for V-band RF applications can be realized by using the test circuit A4. The proposed design can easily be used for ESD protection in the 60-GHz RF LNA.
V. EXAMPLE OFESD PROTECTION DESIGNAPPLIED TOLNA
The LNA circuit shown in Fig. 1 is simulated. Besides, by using the extracted RF characteristics in Section IV, the LNA
with the proposed ESD protection design is also simulated. The measured S-parameters of the test circuit A4 are inserted at the input port of the 60-GHz LNA.
Fig. 11 shows the simulated S-parameters of the 60-GHz LNA. As shown in Fig. 11(a), both the stand-alone LNA and the LNA with proposed ESD protection circuit achieve good input matching (S11<−15 dB) at operating frequency. The
LNA without ESD protection circuit achieves 14.6-dB gain (S21) at 60 GHz, as shown in Fig. 11(b). With the ESD
protection circuit A4 adding in the LNA, the simulated gain becomes 12.8 dB at 60 GHz. Although the ESD protection circuit slightly degrades the RF performances of LNA, it can provide suitable ESD protection. The proposed ESD protection design in this work has been proved to achieve the required ESD robustness in a compact layout size with little RF performance degradation.
VI. CONCLUSION
The new compact ESD protection circuits for V-band RF applications have been designed, fabricated, and character-ized in a 65-nm CMOS process. These ESD protection cir-cuits are developed to support RF circuit designers for them to easily apply ESD protection in the 60-GHz RF circuits. The proposed ESD protection design uses the inductor, ca-pacitor, and ESD protection diodes, which devices are all provided in the commercial CMOS process. Such compact ESD protection circuits can achieve the 2-kV HBM ESD robustness with 1.8-dB insertion loss and small layout area, which is the useful solution for on-chip ESD protection design for 60-GHz RF applications. Thus, the proposed com-pact ESD protection design can be used for V-band RF ESD protection.
ACKNOWLEDGMENT
The authors would like to thank the review meet-ings of Taiwan Semiconductor Manufacturing Company (TSMC) during circuit design and measurement, where the participants included M.-H. Song, C.-P. Jou, T.-H. Lu, J.-C. Tseng, M.-H. Tsai, T.-L. Hsu, P.-F. Hung, T.-H. Chang, and Y.-L. Wei.
REFERENCES
[1] C. Chang, C. Chao, J. Chern, and J. Sun, “Advanced CMOS technology portfolio for RF IC applications,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1324–1334, Jul. 2005.
[2] H. Bennett, R. Brederlow, J. Costa, P. Cottrell, W. Huang, A. Immorlica, J. Mueller, M. Racanelli, H. Shichijo, C. Weitzel, and B. Zhao, “De-vice and technology evolution for Si-based RF integrated circuits,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1235–1258, Jul. 2005. [3] P. Mak and R. Martins, “High-/mixed-voltage RF and analog CMOS
cir-cuits come of age,” IEEE Circir-cuits Syst. Mag., vol. 10, no. 4, pp. 27–39, Fourth Quarter, 2010.
[4] S. Voldman, ESD: RF Technology and Circuits. Hoboken, NJ: Wiley, 2006. [5] G. Boselli, V. Reddy, and C. Duvvury, “Impact of scaling on the high current behavior of RF CMOS technology,” IEEE Trans. Device Mater. Reliab., vol. 4, no. 3, pp. 542–548, Sep. 2004.
[6] M. Tsai and S. Hsu, “A 24 GHz low-noise amplifier using RF junction varactors for noise optimization and CDM ESD protection in 90-nm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 7, pp. 374– 376, Jul. 2011.
[7] M.-D. Ker and C.-M. Lee, “Interference of ESD protection diodes on RF performance in giga-Hz RF circuits,” in Proc. IEEE Int. Circuits Syst. Symp., 2003, pp. I-297–I-300.
[8] K. Gong, H. Feng, R. Zhan, and A. Wang, “A study of parasitic effects of ESD protection on RF ICs,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 393–402, Jan. 2002.
[9] C. Richier, P. Salome, G. Mabboux, I. Zaza, A. Juge, and P. Mortini, “Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 µm CMOS process,” J. Electrostat., vol. 54, no. 1, pp. 55–71, Jan. 2002.
[10] D. Linten, S. Thijs, M. Natarajan, P. Wambacq, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Donnay, and S. Decoutere, “A 5-GHz fully inte-grated ESD-protected low-noise amplifier in 90-nm RF CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1434–1442, Jul. 2005.
[11] M.-D. Ker, J.-J. Peng, and H.-C. Jiang, “ESD test methods on integrated circuits: An overview,” in Proc. IEEE Int. Conf. Electron., Circuits Syst., 2001, pp. 1011–1014.
[12] K. Bhatia, N. Jack, and E. Rosenbaum, “Layout optimization of ESD protection diodes for high-frequency I/Os,” IEEE Trans. Device Mater. Reliab., vol. 9, no. 3, pp. 465–475, Sep. 2009.
[13] M.-D. Ker, “Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI,” IEEE Trans. Electron Devices, vol. 46, no. 1, pp. 173–183, Jan. 1999.
[14] M.-D. Ker, C.-Y. Lin, and Y.-W. Hsiao, “Overview on ESD protection designs of low-parasitic capacitance for RF ICs in CMOS technologies,” IEEE Trans. Device Mater. Reliab., vol. 11, no. 2, pp. 207–218, Jun. 2011. [15] S. Hyvonen, S. Joshi, and E. Rosenbaum, “Cancellation technique to provide ESD protection for multi-GHz RF inputs,” Electron. Lett., vol. 39, no. 3, pp. 284–286, Feb. 2003.
[16] S. Hyvonen, S. Joshi, and E. Rosenbaum, “Comprehensive ESD protec-tion for RF inputs,” in Proc. EOS/ESD Symp., 2003, pp. 1–7.
[17] S. Hyvonen and E. Rosenbaum, “Diode-based tuned ESD protection for 5.25-GHz CMOS LNAs,” in Proc. EOS/ESD Symp., 2005, pp. 1–9. [18] S. Thijs, K. Raczkowski, D. Linten, M. Scholz, A. Griffoni, and
G. Groeseneken, “CDM and HBM analysis of ESD protected 60 GHz power amplifier in 45 nm low-power digital CMOS,” in Proc. EOS/ESD Symp., 2009, pp. 1–5.
[19] W. Soldner, M. Streibl, U. Hodel, M. Tiebout, H. Gossner, D. Schmitt-Landsiedel, J. Chun, C. Ito, and R. Dutton, “RF ESD protection strategies—Codesign vs. low-C protection,” Microelectron. Reliab., vol. 47, no. 7, pp. 1008–1015, Jul. 2007.
[20] V. Vassilev, S. Thijs, P. Segura, P. Leroux, P. Wambacq, G. Groeseneken, M. Natarajan, M. Steyaert, and H. Maes, “Co-design methodology to provide high ESD protection levels in the advanced RF circuits,” in Proc. EOS/ESD Symp., 2003, pp. 1–9.
[21] C.-Y. Lin, L.-W. Chu, S.-Y. Tsai, M.-D. Ker, T.-H. Lu, T.-L. Hsu, P.-F. Hung, M.-H. Song, J.-C. Tseng, T.-H. Chang, and M.-H. Tsai, “Mod-ified LC-tank ESD protection design for 60-GHz RF applications,” in Proc. Eur. Conf. Circuit Theory Des., 2011, pp. 57–60.
[22] D. Pozar, Microwave Engineering. Hoboken, NJ: Wiley, 2005. [23] Y.-W. Hsiao and M.-D. Ker, “Low-capacitance ESD protection design for
high-speed I/O interfaces in a 130-nm CMOS process,” Microelectron. Reliab., vol. 49, no. 6, pp. 650–659, Jun. 2009.
[24] H. Yen, T. Yeh, and S. Liu, “A physical de-embedding method for silicon-based device applications,” PIERS Online, vol. 5, no. 4, pp. 301–305, 2009. [25] C.-Y. Lin, L.-W. Chu, and M.-D. Ker, “Design and implementation of con-figurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process,” Microelectron. Reliab., vol. 51, no. 8, pp. 1315–1324, Aug. 2011.
Chun-Yu Lin (S’06–M’09) received the B.S.
degree from the Department of Electronics Engi-neering, National Chiao Tung University, Hsinchu, Taiwan, in 2006 and the Ph.D. degree from the Insti-tute of Electronics, National Chiao Tung University, in 2009.
Since 2009, he has been a Postdoctoral Researcher with the Institute of Electronics. His current research interests include electrostatic discharge (ESD) pro-tection designs and biomimetic circuit designs.
Dr. Lin has also served as the Secretary-General of Taiwan ESD Association since 2010.
Li-Wei Chu (S’10) received the B.S. degree from
the Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, in 2006 and the M.S. degree from the Institute of Electro-Optical Engineering, National Chiao Tung Univer-sity, Hsinchu, Taiwan, in 2008, where he is currently working toward the Ph.D. degree in the Department of Photonics and Display Institute.
His current research interests include the periph-eral circuits integrated on panel for flat panel display applications and the design of 60-GHz ESD protec-tion circuits in CMOS process.
Shiang-Yu Tsai received the B.S. degree from the
Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, in 2010, where he is currently working toward the M.S. de-gree in the Institute of Electronics.
His current research interests include ESD protec-tion circuit designs.
Ming-Dou Ker (S’92–M’94–SM’97–F’08) received
the Ph.D. degree from the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, in 1993.
He was the Department Manager with the VLSI Design Division, Computer, and Communication Re-search Laboratories, Industrial Technology ReRe-search Institute, Hsinchu. Since 2004, he has been a Full Professor with the Department of Electronics En-gineering, National Chiao Tung University, where he is currently the Distinguished Professor. During 2008–2011, he was rotated to be the Chair Professor and Vice President of I-Shou University, Kaohsiung, Taiwan. He was the Executive Director of National Science and Technology Program for System-on-Chip, Taiwan, during 2010–2011 and is currently the Executive Director of National Science and Technology Program on Nano Technology, Taiwan (2011–2014). In the technical field of reliability and quality design for microelectronic circuits and systems, he has published over 450 technical papers in international journals and conferences. He has proposed many solutions to improve the reliability and quality of integrated circuits (ICs), which have been granted with 190 U.S. patents and 166 Taiwan patents. He had been invited to teach and/or to consult the reliability and quality design for ICs by hundreds of design houses and semiconductor companies in the worldwide IC industry. His current research interests include reliability and quality design for nanoelectronics and gigascale systems, high-speed and mixed-voltage I/O interface circuits, on-glass circuits for system-on-panel applications, and biomimetic circuits and systems for intelligent prosthesis.
Dr. Ker has served as a member of the Technical Program Committee and the Session Chair of numerous international conferences for many years. He ever served as the Associate Editor for the IEEE TRANSACTIONS ONVERYLARGE
SCALEINTEGRATION(VLSI) SYSTEMS, 2006–2007. He was selected as the Distinguished Lecturer in the IEEE Circuits and Systems Society (2006–2007) and in the IEEE Electron Devices Society (2008–present). He was the President of Foundation in Taiwan ESD Association. In 2009, he was awarded as one of the top ten Distinguished Inventors in Taiwan.
