Modeling and Small-Signal Analysis of a
Switch-Mode Rectifier With Single-Loop
Current Sensorless Control
Hung-Chi Chen, Member, IEEE, Zen-How Wu, and Jhen-Yu Liao
Abstract—The conventional multiloop control with one inner
current loop and one outer voltage loop is often applied to a single-phase boost-type switch-mode rectifier where the output of the voltage loop is a current amplitude signal. In the duty phase control (DPC) proposed recently, the output of the voltage loop is a phase signal used to generate the switching signals without current loop and sensing current. To improve the clamped current waveform of DPC, a single-loop current sensorless control (SLCSC) with some nominal parameters had also been proposed to compensate for the voltage drops across the switch, diodes, and inductor resistance. In this paper, the effect of the differences between nominal and real circuit parameters on the input current waveforms of SLCSC are addressed in detail. The results are helpful in the design of SLCSC. From the simulated and experimental results, we can find that the output voltage is well regulated by the only voltage loop and the input current harmonics are significantly improved.
Index Terms—AC–DC power conversion.
I. INTRODUCTION
T
HE USE of ac/dc conversion has increased in a wide di-versity of applications: power supplies for microelectron-ics, household electric appliances, electronics ballasts, battery charging, motor drives, power conversion, etc., which also re-sults in the increase of input harmonic currents. Current har-monics have a negative effect on the electrical system and sev-eral standards have introduced important and stringent limits on harmonics.Switching-mode rectifiers (SMRs) are an effective means to perform the qualified ac/dc conversion [1], [2], including input current shaping and output voltage regulation. Among all the power circuit topologies of SMR, the boost-type SMR, as shown in Fig. 1, is the most popular one for its continuous current in the boost inductors [2]. However, the qualified ac/dc functions must be met by adequately turning on and turning off the only controllable power switch in the boost-type SMR. According to the control structures, the SMR controls can be divided into two groups, where one is multiloop control [3]–[10] and the other single-loop control [11]–[17].
In the conventional multiloop control, as shown in Fig. 1, the inner current loop and the outer voltage loop work together to Manuscript received February 25, 2009; revised May 20, 2009. Current version published January 29, 2010. This work was supported by the Na-tional Science Council of Taiwan under Grant NSC97-2221-E-009-184. Rec-ommended for publication by Associate Editor K. Ngo.
The authors are with the Department of Electrical and Control Engineer-ing (ECE), National Chiao Tung University (NCTU), Hsinchu 30010, Taiwan (e-mail: hcchen@cn.nctu.edu.tw; kevin14_0922@hotmail.com; popoid1003@ hotmail.com).
Digital Object Identifier 10.1109/TPEL.2009.2024420
Fig. 1. Boost-type SMR with multiloop control.
decide the conduction ratio of the only controllable switch. The former loop shapes input current waveform and the latter loop regulates the output voltage, respectively. In [3] and [4], a robust voltage control loop had been proposed to remove the effect of voltage ripple on the current command. Several intelligent current sampling algorithms proposed in [5] and [6] can sense current correctly, and many feedforward current controllers [3], [7], [8] had been used to help the current loop to obtain the large-variation control signal. Some sensorless multiloop controls for boost-type SMRs had been proposed in [9] and [10].
Furthermore, we can find that the output voltage loop is the only loop in the group of single-loop control [11]–[17] and all of them can be seen as sensorless controls, where [11]–[14] elimi-nate the senses of input voltage and [14]–[17] exclude the sens-ing of current. It is noted that the inductor currents in [11]–[14] are sensed and used in their single voltage loops. However, an es-sential zero-current detector is necessary to ensure the inductor current flowing at the boundary condition, which contributes to the variable switching frequency in [11]. On the contrary, fixed switching periods can be found in [12]–[17]. Additionally, all the outputs of the voltage loops in [12]–[15] adjust the amplitudes of the fixed-frequency carrier signals. Only a fixed-frequency fixed-amplitude carrier signal is used in [16] and [17]. It is noted that due to the digital resolution, implementing a fixed-amplitude carrier signal is easier than a variable–fixed-amplitude in digital signal processor (DSP)/field-programmable gate array (FPGA) based systems.
The duty phase control (DPC) with the single voltage loop is plotted in Fig. 2 [16], where the switching signal is obtained from the comparison of a control signal at “−” terminal and 0885-8993/$26.00 © 2010 IEEE
Fig. 2. Boost-type SMR with DPC [16].
Fig. 3. Boost-type SMR with SLCSC [17].
a fixed-amplitude carrier signal at “+” terminal. The output of voltage controller is a phase signal, instead of the current amplitude in conventional multiloop control in Fig. 1. The per-formance of the proposed DPC had been evaluated and demon-strated from the simulated and experimental results in [16].
However, due to the real circuit elements, the resulting input current returns to zero early before the zero-crossing points of input voltage (i.e., clamped current). In order to improve the clamped input current waveform, a single-loop current sensor-less control (SLCSC), plotted in Fig. 3, had also been proposed in [17] by adding two additional loops with nominal parameters to compensate for the voltage drops across the circuit elements. All the single-loop control methods can be summarized in Table I.
In [17], the sensitivity of the inductance parameter had even been studied by some simulation results. However, the follow-ing works here show that the input current waveform can be represented in terms of the circuit parameter and the parame-ter error. Consequently, the effect of parameparame-ter error on input current and the small-signal transfer function of output voltage response can be modeled, which also leads to this paper.
In this paper, the effect of the differences between nominal and real circuit parameters on the input current waveforms, and the modeling and small-signal analysis of SLCSC are addressed
TABLE I
SUMMARIZEDRESULT FORVARIOUSSINGLE-LOOPCONTROLS[11]–[17]
in detail. The result shows that the input current waveform of SLCSC is highly dependent on the circuit parameter error, not on the control parameters, whereas in multiloop control, the control parameters dominate the input current waveforms. Addition-ally, we understand that the parameter error would contribute to not only a clamped current but also a nonzero current at the zero-crossing points of input voltage (i.e., a hard-commutation current), which are helpful in the design of SLCSC.
Simply speaking, [17] is focused on the design and devel-opment of single-loop current control, and this paper has em-phasized on the effect of parameter error and the small-signal transfer function between output voltage and control signal.
The paper is organized as follows. Initially, the input current of SLCSC is analyzed. The input current waveforms of SLCSC can be divided into three groups: sinusoidal currents, clamped currents, and hard-commutation currents. The model and small-signal analysis of the case of sinusoidal currents are derived. Fi-nally, some simulated and experimental results have been given to illustrate the performances of the proposed SLCSC.
II. SINGLE-LOOPCURRENTSENSORLESSCONTROL(SLCSC)
A. Boost-Type SMR
As shown in Fig. 1, the power circuit of the boost-type SMR mainly consists of a diode bridge rectifier and a boost-type dc/dc converter. When the switch SW is turned on, the input current flows through two rectifier diodes and the inductor L, and returns to the source. Similarly, the input current flows through two rectifier diodes, inductor L and diode D, and returns to the source when the power switch SW is turned off.
Due to the boost-type topology, the inductor current must be either positive or clamped to zero (i.e., no negative current). In steady state, the inductor current must be periodic with each half line cycle, and can be expressed as a sum of infinite base current waveform iL n(t− nT/2) iL(t) = n = +∞ n =−∞ iL n t− nT 2 (1) where T is the period of input line cycle and
iL n(T /2) = iL n(0). (2)
From the circuit topology shown in Fig. 1, the input current isis equal to positive inductor current iL and negative inductor
current−iL, when the input voltage vs = Vspsin (ωt) is positive
represented [10] by
is(t) = sign(vs(t))iL(t) = sign(sin ωt)iL(t) (3)
where sign(•) is the sign operator and is defined as sign(X) =
+1, when X≥ 0
−1, when X < 0. (4)
In order to model the behavior of a boost-type SMR in a simplified way, the following assumptions are initially made.
1) Power switch SW is assumed to operate at a switching frequency approaching infinity.
2) The small phase signal θ≈ 0 in radians is assumed and it follows that the approximations sin θ≈ θ and cos θ ≈ 1 can be used.
3) A bulk capacitor Cdis assumed in the power circuit, which
contributes to the steady-state output voltage Vd equal to
voltage command Vd∗.
4) Both nominal sums of the conduction voltages in the loop of “switch SWON” and “switch SWOFF” are assumed to be equal to VF.
B. SLCSC
The configuration of the proposed SLCSC with the only volt-age loop is plotted in Fig. 3. Like DPC in Fig. 2, the duty signal GT is also generated from the comparison between a fixed
trian-gle signal vtri at “+” (the inverted commas have been retained for consistency) terminal and a control signal vcontat “−” ter-minal and the output of voltage controller is a phase signal θ. To compensate for the effect of inductor resistance and conducting voltages on the input current waveform, the control signal vcont in SLCSC is obtained by vcont= Vsp Vd∗ |sin (ωt − θ)| − θrˆL ω ˆL|sin (ωt)| − ˆ VF Vsp (5) where ˆrLand ˆL represent the nominal circuit values, and ˆVF is
the sum of all the nominal conduction voltages.
The differences between nominal values and real values can be represented as
∆rL = ˆrL− rL (6)
∆L = ˆL− L (7)
∆VF = ˆVF − VF (8)
where rL and L are the real values in the boost-type SMR and
VF is the sum of the real conduction voltages. With assumed
infinite switching frequency, the average duty ratio signal ¯d over one switching period can be represented in terms of the control signal vcont
¯
d = 1− vcont. (9)
Replacing vcontin (9) by (5), the average duty ratio signal ¯d can be obtained as ¯ d = 1−Vsp Vd∗ |sin (ωt − θ)| + θ Vsp Vd∗ ˆ rL ω ˆL|sin (ωt)| + ˆ VF Vd∗. (10)
Then, we can write two Kirchhoff’s voltage law (KVL) equa-tions according to the conduction state of the power switch SW
LdiL
dt = Vsp|sin (ωt)| − iLrL− VF when SW is “ON” (11) LdiL
dt = Vsp|sin (ωt)| − V
∗
d − iLrL− VF when SW is “OFF”
(12) Multiplying (11) and (12) by the turn-ON time ¯dTs and the
turn-OFFtime (1− ¯d)Ts, respectively, yields the following
av-eraged equation: LdiL
dt = Vsp|sin (ωt)| − (1 − ¯d)V
∗
d − iLrL− VF (13)
where Tsis the switching period. Therefore, by substituting ¯d in
(10) into (13) and rearranging the other terms, we can obtain the following time-differential equations for inductor current iL:
LdiL dt = Vsp |sin (ωt)| − |sin (ωt − θ)| + θrˆL ω ˆL|sin (ωt)| − rLiL+ ( ˆVF − VF). (14)
Then, using the assumed sin θ≈ θ, cos θ ≈ 1 and the common trigonometric identity sin(A− B) = sin A cos B − sin B cos A, we obtain the following approximation of (14):
LdiL
dt + rLiL ≈ Vsp
|sin (ωt)| − |sin (ωt) − θ cos (ωt)| + θ rL + ∆rL
ω(L + ∆L)|sin (ωt)|
+ ∆VF.
(15) Due to the assumption of small phase signal θ≈ 0, the term |sin (ωt)| − |sin (ωt) − θ cos (ωt)| in (15) can be replaced by θsign(sin (ωt)) cos (ωt)
LdiL
dt + rLiL ≈ Vspθ
sign sin (ωt) cos (ωt)
+ rL + ∆rL
ω(L + ∆L)|sin (ωt)|
+ ∆VF
(16) where the function of sign(X) had been defined in (4).
C. Input Current Waveforms
As shown in (1), the steady-state inductor current is repeated with each half line cycle and can be represented by the sum of base currents iL n(t− nT/2). Thus, only considering the first
half line cycle (0∼ T/2) contributes to the following equalities sign(sin (ωt)) = 1,|sin (ωt)| = sin (ωt), and
LdiL n dt + rLiL n ≈ Vspθ cos (ωt) + rL+ ∆rL ω(L + ∆L)sin (ωt) + ∆VF. (17)
Fig. 4. Illustrated waveforms for: (a) sinusoidal input current, (b) clamped input current, and (c) hard-commutation input current.
Then, solving (17) yields the base current iL n(t) during the
first half line cycle 0∼ T/2 iL n(t) ≈ Vspθ ωL sin (ωt) + iL n(0)e − ω Q Lt+∆VF rL (1− e−Q Lω t) + kVspθ
ωL sin αL[− cos (ωt + αL) + cos αLe
− ω Q Lt)] × u(t)− u t−T 2 (18) where ω(T /2) = π, QL denotes the quality factor of inductor L
QL =
ωL rL
= cot (αL) (19)
and the factor k represents the equivalent parameter error k = L∆rL − rL∆L
rL(L + ∆L)
. (20)
It is noted that the zero equivalent parameter error k = 0 implies
∆rL
rL
= ∆L
L . (21)
Due to the effects of parameter errors ∆rL, ∆L, and ∆VF
on (18), the operation of SMR with SLCSC can be divided into three cases according to the input current waveforms plotted in Fig. 4.
III. SMALL-SIGNALMODEL
A. Sinusoidal Input Current
With the condition of zero equivalent parameter error k = 0 and zero conduction voltage ∆VF = 0, the base current in (18)
becomes iL n(t)≈ Vspθ ωL sin (ωt) + iL n(0)e − ω Q Lt u(t)− u t−T 2 (22) and from (2), obviously, the initial value iL n(0) in this case must
be zero. From (1), the inductor current iL becomes a rectified
sinusoidal waveform iL(t)≈ n = +∞ n =−∞ Vspθ ωL sin (ωt− nπ) × u t− nT 2 − u t− nT 2 − T 2 =Vspθ ωL |sin ωt| . (23) From (3), the input current is(t) can be expressed as
is(t)≈
Vspθ
ωL sin (ωt) = Ispsin (ωt). (24) We can find that the input current isis automatically shaped
to a sinusoidal waveform in phase with the input voltage vs, as
shown in Fig. 4(a). The current amplitude Isp is proportional
to the controllable phase θ. Obviously, the input power Ps is
controllable by the only voltage controller in SLCSC.
The transfer function between the output voltage perturbation ∆Vd and the phase perturbation ∆θ can be obtained from the power balance between input power Ps, output power Pd, and
capacitor power PC. The input power Pswith small perturbation ∆Psbecomes Ps+ ∆Ps= Vsp2(θ + ∆θ) 2ωL = Vsp2θ 2ωL + Vsp2∆θ 2ωL . (25)
The output power Pd with small perturbation ∆Pd can be
represented by the load perturbation ∆RLand the output voltage
perturbation ∆Vd Pd+ ∆Pd = (Vd∗+ ∆Vd)2 RL+ ∆RL ≈(Vd∗)2 RL +(V ∗ d)2 RL −∆RL RL +2V ∗ d∆Vd RL . (26) The small perturbation ∆PC of capacitor power can be
rep-resented by the output voltage perturbation ∆Vd ∆PC = dC 2(Vd∗+ ∆Vd)2 dt ≈ CV ∗ d d∆Vd dt . (27) The balance between the power perturbations ∆Ps= ∆PC + ∆Pdcan yield the following two small-signal transfer functions
for the sinusoidal current case Gs(s) = ∆Vd ∆θ = V2 sp 2CVd∗ωL 1 s + 2/(CRL) (28) Gd(s) = ∆Vd ∆RL = V ∗ d CR2 L 1 s + 2/(CRL) . (29)
Obviously, the behavior of output voltage can be seen as a first-order model, and thus, the desired output voltage can be well regulated by using simple plus integral (PI) type controller. The equivalent small-signal model of SLCSC with sinusoidal input current is plotted in Fig. 5.
B. Clamped Input Current
In a boost-type SMR, the inductor current must be either positive value or zero value. Thus, when the values ∆VF, ∆rL,
Fig. 5. Equivalent small-signal model of SLCSC with sinusoidal input current. TABLE II
GENERALTRENDS OFINPUTCURRENTWAVEFORMS INTERMS OFkAND∆VF
from a positive value to a negative value, the real inductor current must be clamped to zero until the arrival of the next half line cycle, as shown in Fig. 4(b).
Due to the clamped current, the initial value of current is also zero iL n(0) = 0. Obviously, the current in (18) will be
clamped to zero when equivalent parameter error k≤ 0 and ∆VF ≤ 0 because the functions 1 − e−
ω
Q Ltand cos αLe− ω Q Lt− cos (ωt + αL) are positive at the end of each half line period.
The general trends of input current waveforms in terms of k and ∆VF are tabulated in Table II.
Applying zero initial current iL n(0) = 0, and substituting sin αL = 1/ (1 + Q2 L) and cos αL = QL/ (1 + Q2 L) into
(19), the clamped base current iL n(t) can be rewritten as
iL n(t)≈ Vspθ ωL 1 + k 1 1 + Q2 L sin ωt− k QL 1 + Q2 L cos ωt + k QL 1 + Q2 L e−Q Lω t [u(t)− u(t − tc)] +∆VF rL (1− e−Q Lω t)[u(t)− u(t − tc)] (30) where tcdenotes the current clamping instant smaller than the
half line period 0 < tc≤ T/2.
Because the last term (1− e−Q Lω t)[u(t)− u(t − tc)] is not a function of control signal θ, error ∆VF has no effect on the
small-signal transfer function ∆Vd/∆θ. In order to simplify
the analysis, zero parameter error ∆VF is assumed here in the
derivation of small-signal transfer function. It follows that from (1) and (3), the simplified clamped input current is,c(t) can be
expressed as shown (31), at the bottom of this page.
By expressing is,c(t) as fourier series, the component Is,cof
fundamental current in phase with the input voltage Vspsin(ωt)
can be expressed as Is,c=
Vspθ
ωL Fc(k, QL) (32)
where (33), as shown at the bottom of this page.
Then, the small perturbation ∆Ps resulting from phase
per-turbation ∆θ now becomes
∆Ps= Fc(k, QL)
V2
sp
2ωL∆θ. (34)
By following the steps in (26)–(28), we can obtain the small-signal transfer function Gc(s) for clamped input current case in
terms of Gs(s) in (28) Gc(s) = Fc(k, QL) V2 sp 2CVd∗ωL 1 s + 2/(CRL) = Fc(k, QL)Gs(s). (35)
Obviously, small-signal transfer function Gc(s) for clamped
current can be seen as Gs(s) with a modified factor Fc(k, QL).
In addition, the response ∆Vddue to the load perturbation ∆RL
is the same as (29) because the equivalent parameter error only contributes to the input power perturbation.
However, in the former two cases of sinusoidal input current and clamped input current, both the initial values of repeated cur-rent are zero, and thus, the curcur-rent commutation operates at zero current and can be regarded as soft-commutation operations. However, in the following case, the current commutation oper-ates at nonzero current and must be seen as a hard-commutation operation. is,c(t) = Vspθ ωL n = +∞ n =−∞ 1 + k 1 1 + Q2 L sin ωt u t− nT 2 − u t− tc− n T 2 −k QL 1 + Q2 L cos ωt u t− nT 2 − u t− tc− n T 2 +k QL 1 + Q2 L
sign (sin ωt)e−ω t−n T / 2Q L u t− nT 2 − u t− tc− n T 2 (31) Fc(k, QL) = 1 + k 1 1 + Q2 L 2tc T − 1 2πsin 2ωtc − k QL 1 + Q2 L 1− cos 2ωtc 2π +2 πk Q2 L (1 + Q2 L) 2(QL − QLcos ωtce− ω t c Q L − sin ωt ce− ω t c Q L ) . (33)
C. Hard-Commutation Input Current
Alternatively, the values ∆VF, ∆rL, and ∆L may result in a
positive inductor current at the end of each half line cycle, which would force the current commutating from two bridge diodes to the other ones at the zero-crossing points of the input voltage. Substituting (18) into (2) and solving the equation yields the initial current value of hard-commutation input current
iL n(0) = ∆VF rL + kVspθ ωL QL 1 + Q2 L 1 + e−Q Lπ 1− e−Q Lπ . (36) Substituting (36) into (18), the base current for hard-commutation current becomes
iL n(t) ≈ Vspθ ωL 1 + k 1 1 + Q2 L sin ωt− kVspθ ωL QL 1 + Q2 L cos ωt +kVspθ ωL QL 1 + Q2 L 2 1− e−Q Lπ e−Q Lω t+∆VF rL × u(t)− u t−T 2 . (37)
Because the constant ∆VF/rL in (37) is not a function of
control signal θ, the parameter error ∆VF has no effect on the
small-signal transfer function. In order to simply the analysis, the parameter error ∆VF is assumed to be zero here in the
fol-lowing derivation for hard-commutation current case. From (1) and (3), the simplified hard-commutation input current is,h(t)
can be expressed as shown (38), at the bottom of this page. By expressing is,h(t) as a fourier series, the component Is,hof
fundamental current in phase with the input voltage Vspsin(ωt)
can be obtained as Is,h = Vspθ ωL Fh(k, QL) (39) where Fh(k, QL)= 1 + k 1 1 + Q2 L + k4 π Q3 L (1 + Q2 L) 2 1 + e−Q Lπ 1− e−Q Lπ . (40) Then, the input power perturbation ∆Ps resulting from ∆θ
now becomes
∆Ps= Fh(k, QL)
V2
sp∆θ
2ωL . (41)
By following the steps in (26)–(28), we can obtain the small-signal transfer function for hard-commutation
TABLE III
SIMULATEDCIRCUITPARAMETERS
input current Gh(s) = Fh(k, QL) V2 sp 2CVd∗ωL 1 s + 2/(CRL) = Fh(k, QL)Gs(s). (42)
Obviously, small-signal transfer function Gh(s) for clamped
current can be seen as Gs(s) with a modified factor Fh(k, QL).
However, we can find that in the former two cases, all the bridge diodes turn off with zero current switching (ZCS), but in this case, the bridge diodes turn off with a nonzero current, which would contribute to excess loss and reduce the overall efficiency. In addition, the sudden current change would also result in larger current harmonics than in the former two cases.
IV. SIMULATIONS
In this section, we begin with a series of computer simula-tions to demonstrate the results of analysis. All simulated circuit elements are listed in Table III, and a simple PI controller is used as the only voltage controller to adjust the phase signal.
A. Sinusoidal Input Current
By choosing the nominal parameters equal to the real ones (i.e., ∆VF = ∆rL = ∆L = 0), the simulated input currents and
output voltages under various output power are shown in Fig. 6, respectively. We can find that the output voltage is well regulated to the voltage command Vd∗= 300 V and the sinusoidal input currents are in phase with the input voltage. Therefore, the pro-posed SLCSC can obtain high-quality ac/dc performance with only one voltage loop.
Additionally, substituting the simulated parameters in Table II into the equivalent model (28) yields the following s-domain
is,h(t) = Vspθ ωL n = +∞ n =−∞ 1 + k 1 1 + Q2 L sin ωt u t− nT 2 − u t−T 2 − n T 2 −k QL 1 + Q2 L cos ωt u t− nT 2 − u t−T 2 − n T 2 +sign(sin ωt)k QL 1 + Q2 L 2 1− e−Q Lπ e −ω t−n T / 2Q L ut− nT 2 − u t−T 2 − n T 2 . (38)
Fig. 6. (a) Simulated input voltage and input current. (b) Output voltage under various load conditions.
Fig. 7. Output voltage response due to the step change of phase signal.
transfer function where the phase signal is in radians Gs(s) =
109915
s + 31.9. (43)
The response of the output voltage Vd due to the step change
of phase signal ∆θ = 0.2◦is plotted in Fig. 7, where the transfer function in (43) is also included for comparison. We can find that the behavior of (43) is close to the average value response of the simulated output voltage Vd, which also demonstrates the
developed equivalent model in Fig. 5.
B. Clamped and Hard-Switching Input Currents
In order to understand the effect of parameter error, several current waveforms are plotted in Fig. 8, where the used nom-inal values are tabulated in Table IV. Cases (i) and (ii) yield the same value k =−0.5 from (19), and thus, contribute to the same clamped current waveforms shown in Fig. 8(a). Likewise, cases (iii) and (iv) have the same value k = 0.25 from (19), and thus, they contribute to the same hard-commutation current waveforms in Fig. 8(b). Fig. 8(c) and (d) plots the input current waveforms corresponding to the overcompensation ∆VF > 0
and undercompensation ∆VF < 0 of conduction voltages,
respectively.
Case (vii) is a special case where zero nominal values ˆrL =
0, ˆVF = 0 (i.e., k =−1) are used and longer time of clamped
current can be found in Fig. 8(e). In fact, SLCSC with zero nominal values in Fig. 3 can be seen as DPC in Fig. 2. However,
Fig. 8. Simulated input currents with various nominal values tabulated in Table IV.
TABLE IV
SIMULATEDCASES FORVARIOUSNOMINALVALUES
all the input currents in Fig. 8 can be found stable, and SLCSC is able to operate stably.
C. Transient Response
In order to understand the transient response of the proposed SLCSC, the simulated waveforms of sudden load change with-out parameter error and with parameter error are plotted in Fig. 9(a) and (b), respectively. To meet the change of load, the input current magnitude increases from about 6 to about 10 A by SLCSC.
Fig. 9. Simulated waveforms during load regulation: (a) ∆rL= 0, ∆L = 0,
∆VF = 0. (b) ∆rL = 0.5rL, ∆L =−0.5L, ∆VF = 0.5VF.
In Fig. 9(a), we can find that the sinusoidal current is in phase with the input voltage during the transient period. Although the input current in Fig. 9(b) is clamped to zero due to the parameter error, the output voltage is still well regulated.
D. Comments
The sinusoidal input current case is not practical because we cannot determine the real values exactly. However, it is better to keep in clamped current than hard-commutation current. That is, it is preferred to select a larger nominal value of inductance ( ˆL > L), smaller nominal values of resistance (ˆrL < rL), and
nominal conduction voltage ( ˆVF < VF) to operate SMR
effi-ciently with clamped input current during the design of SLCSC. V. EXPERIMENTALRESULTS
In this paper, SLCSC had been digitally implemented in an FPGA-based system using Xilinx XC3S200, where the DPC and SLCSC in [16] and [17] were implemented in DSP TMS320F240. Due to the measurement uncertainty, it is not easy to obtain the real values. In practice, some circuit param-eters, such as inductance, resistance, and conduction voltages, may have small fluctuation with the instantaneous input current. However, we measure the parameters as exact as we can. All the measured circuit parameters have been listed in Table III and can be regarded as the nearly exact parameters.
Fig. 10. Experimental input voltages and currents at 675 W. (a) For an SMR without turning on the power switch. (b) For a DPC-controlled SMR. (c) For an SLCSC-controlled SMR with nearly exact parameter.
Turning off the single power switch in a boost-type SMR obtains the pulse current waveform plotted in Fig. 10(a). The input current harmonics are tabulated in Table V, where the load resistance is decreased to about 30 Ω to yield the rated power 675 W. The input current is highly discontinuous and the peak current is high up to 20 A.
Fig. 10(b) plots the input current, where SLCSC with zero nominal values (i.e., DPC case in Table IV) is used to turn on and turn off the power switch to regulate the output voltage with the rated power of 675 W. We can find that the peak value of the clamped current decreases from 20 to about 12 A, and the total harmonic distortion factor (THD) decreases to the half of Fig. 10(a). However, due to the larger phase between the input voltage and input fundamental current in Fig. 10(b) than that in Fig. 10(a), the displacement power factor (DPF) decreases from 0.978 lagging to 0.908 leading.
Fig. 10(c) plots the input current where SLCSC with nearly exact parameters are used to regulate the output voltage. Due to the fluctuation of the circuit parameter with temperature and current, the input current is not a pure sinusoidal waveform, but is continuous. Due to the increase of DPF in Fig. 10(c), the peak current decreases to about 10 A, the power factor increases from 0.758 to 0.982, and THD decreases from 76.4% to 12.4%.
TABLE V
INPUTCURRENTHARMONICS AND THELIMITS OFIEC-61000-3-2
Fig. 11. Experimental waveforms when the load is suddenly changed. (a) From 450 to 675 W. (b) From 675 to 450 W.
Because of the continuous current, less current harmonics are found in Fig. 10(c) than those in Fig. 10(b).
All the current harmonics are tabulated in Table V, where the harmonic limits of IEC-61000-3-2 class A are also listed for comparison. It is noted that the input current waveform in (18) is highly dependent on the parameter errors and the quality factor QL in (19), especially when zero nominal values are
included in DPC. The PI parameter of voltage loop can improve the response, but does not dominate the compliance of the IEC-61000-3-2 class A. Due to the absence of design optimization in the experiment, the input current harmonics in Fig. 10(c) are compliant to the limit of class A, but those in Fig. 10(b) are not. To verify the dynamic performance of the proposed SLCSC with nearly exact parameters, some waveforms are plotted in Fig. 11 where the load condition is suddenly changed between 450 and 675 W. During the regulation, the input current is in
phase with the input voltage, thus clearly showing that the pro-posed SLCSC also possesses good performance of regulation.
VI. CONCLUSION
In this paper, the effects of nominal parameter error on the input current waveforms and the small-signal model for a boost-type SMR with SLCSC have been addressed. The results also show that the parameter errors and the quality factor of in-ductor have a great effect on the input current waveform, and therefore, dominate the compliance of harmonic limits, not the control parameters. Due to the concerns of efficiency and cur-rent harmonics, it is better to keep SMR operating with clamped current than with hard-commutation current.
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Hung-Chi Chen (M’06) was born in Taichung,
Taiwan, in June 1974. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineer-ing (EE), National TsEngineer-ing-Hua University (NTHU), Hsinchu, Taiwan, in June 1996 and June 2001, respectively.
From October 2001, he was a Researcher at the Energy and Resources Laboratory (ERL), Industrial Technology Research Institute (ITRI), Hsinchu. In August 2006, he joined the Department of Electrical and Control (ECE), National Chiao-Tung University (NCTU), Hsinchu, where he is currently an Assistant Professor. His current research interests include power electronics, power factor correction, motor and inverter-fed control, DSP/microcontroller unit/FPGA-based implementation of digital control.
Zen-How Wu was born in Taoyuan, Taiwan, in
September 1985. He received the B.S. degree from the Department of Electrical Engineering (EE), Yuan Ze University (YZU), Taoyuan, in June 2007. He is currently working toward the M.S. degree at the Electrical and Control (ECE) Department, National Chiao-Tung University (NCTU), Hsinchu, Taiwan.
His current research interests include power elec-tronics and control, power factor correction, and FPGA-based implementation of digital control.
Jhen-Yu Liao was born in Taoyuan, Taiwan, in
August 1986. He received the B.S. degree from the Mechatronic Technology Department, National Taiwan Normal University (NTNU), Taipei, Taiwan, in June 2008. He is currently working toward the M.S. degree at the Electrical and Control (ECE) De-partment, National Chiao-Tung University (NCTU), Hsinchu, Taiwan.
His current research interests include power elec-tronics and control, power factor correction, and FPGA-based implementation of digital control.
![Fig. 2. Boost-type SMR with DPC [16].](https://thumb-ap.123doks.com/thumbv2/9libinfo/7678171.142005/2.891.65.434.117.486/fig-boost-type-smr-with-dpc.webp)
