New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance

New Transient Detection Circuit for On-Chip

Protection Design Against System-Level

Electrical-Transient Disturbance

Ming-Dou Ker, Fellow, IEEE, and Cheng-Cheng Yen, Member, IEEE

Abstract—A new transient detection circuit for on-chip pro-tection design against system-level electrical-transient distur-bance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simula-tion and verified in silicon chip. The experimental results in a 0.18-µm complementary-metal–oxide–semiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immu-nity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.

Index Terms—Electrical-fast-transient (EFT) test, electromag-netic compatibility, electrostatic discharge (ESD), system-level ESD test, transient detection circuit.

I. INTRODUCTION

C

OMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR (CMOS) integrated circuits (ICs) have been widely used in industrial electronic products, such as motor drives, robot system, uninterruptible power supply, and global positioning system, etc. [1]–[5]. With increasing electromagnetic emission sources in a microelectronic system, such as radio-frequency transmitters, high-speed digital devices, mobile phones, etc., the environment where these CMOS ICs are located has more system-level electrical-transient disturbance than before. Therefore, electrical-transient disturbance has become a primary reliability issue in industrial electronic products equipped with CMOS ICs [6]–[9]. With more circuit blocks being integrated into a chip, such as mixed signal, mixed voltage, system on chip, etc., CMOS devices will suffer more electrical transients coming from the interior of CMOS ICs.

Manuscript received March 4, 2009; revised June 2, 2009, August 3, 2009, and September 27, 2009; accepted December 7, 2009. Date of publication February 5, 2010; date of current version September 10, 2010. This work was supported in part by the National Science Council (NSC), Taiwan, under Contract NSC 98-2221-E-009-113-MY2, by the “Aim for the Top University Plan” of National Chiao Tung University and the Ministry of Education, Taiwan, and by Himax Technologies Inc., Taiwan.

M.-D. Ker is with the Department of Electronic Engineering, I-Shou Uni-versity, Kaohsiung 84041, Taiwan, and also with the Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan (e-mail: mdker@ ieee.org).

C.-C. Yen is with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan.

Digital Object Identifier 10.1109/TIE.2009.2039456

With the scaled clearance between PMOS and NMOS de-vices in advanced semiconductor technology, it has been proven that such electrical-transient noises can cause transient-induced latchup (TLU) failure on the inevitable parasitic silicon-controlled rectifier in CMOS ICs [10], [11]. The reliability issue of system-level electrical-transient disturbance results from not only the progress of more integrated circuit blocks into a single chip but also from the strict requirements of reliability performance requested by the IC industry, such as the system-level electrostatic-discharge (ESD) test of the IEC 61000-4-2 standard [12] and the electrical-fast-transient (EFT) test of the IEC 61000-4-4 standard [13].

It has been observed during system-level ESD and EFT tests that the ESD-generated or EFT-induced transient volt-ages are quite large (with amplitudes of up to hundreds of volts), fast (with periods of several tens of nanoseconds), and randomly exist on the power, ground, and input/output (I/O) pins of the ICs inside the microelectronic system. High-voltage electrical fast transients often cause the CMOS ICs inside the equipment under test (EUT) to be upset or frozen after system-level electrical-transient disturbance. It has been re-ported that system-level electrical-transient disturbance cou-pled to the power and ground pins of a super-twisted nematic liquid-crystal-display (LCD) driver circuit had been reported to cause abnormal function of the LCD panel [14]. The CMOS ICs inside the microelectronic products are very susceptible to system-level electrical-transient disturbance [15]–[17], even though they have passed the component-level ESD specifica-tions, such as the human-body model of±2 kV, the machine model of±200 V, and the charged-device model of ±1 kV.

In order to protect the microelectronic system against tran-sient disturbance events, the traditional solution used in mi-croelectronic products is to add some discrete noise-bypassing components or board-level noise filters into the printed circuit board (PCB) to decouple, bypass, or absorb the electrical-transient energy under system-level electrical-electrical-transient dis-turbance conditions [18]–[20]. The immunity of CMOS ICs against the system-level electrical-transient disturbance test can be significantly enhanced by choosing the proper noise filter networks added into the PCB together. However, the additional discrete noise-bypassing components substantially increase the total cost of microelectronic products. Therefore, the chip-level solutions to meet the high-transient-disturbance immunity specification for microelectronic products without additional discrete noise-decoupling components added on the PCB are highly desired by the IC industry [21]–[23].

Fig. 1. Previous on-chip transient detection circuits composed of (a) a latch circuit and (b) a latch circuit with additional capacitors (C_{P 1} andC_{P 2}) to enhance the detection sensitivity.

In previous works, two on-chip transient detection circuits have been proposed to detect transient noise, as shown in Fig. 1(a) and (b). The circuit structure in Fig. 1(a) is composed of a latch circuit [15]. The detection sensitivity was adjusted by the device ratio between PMOS and NMOS in the latch circuit. The modified design in Fig. 1(b) was realized with additional capacitors (C_{P 1}andC_{P 2}) located betweenVDD/VSS power lines and the I/O nodes of the latch circuit to enhance its detection sensitivity [21]. However, the detection sensitivity could be degraded by the large on-chip decoupling capacitors between power lines in the CMOS IC products.

In this paper, a new on-chip transient detection circuit is proposed to detect the positive and negative electrical transients under system-level ESD or EFT tests [24]. By using a longer time delay in theRC circuit during system-level ESD and EFT tests, the proposed transient detection circuit can memorize the occurrence of electrical-transient disturbance events. It had been proven that the hardware/firmware codesign can effec-tively improve the electrical-transient disturbance robustness of CMOS ICs in microelectronic products [15]. When system-level electrical-transient disturbance happens, the detection re-sults from the proposed transient detection circuit can be stored as a firmware index to start the system recovery procedure after the disturbance events. The circuit function to detect different positive or negative electrical transients has been investigated by HSPICE simulation and verified by silicon chip. The TLU measurement method [25], the system-level ESD gun [26], and the EFT generator with an attenuation network and a capacitive coupling clamp [27] are used to evaluate the detection function of the proposed transient detection circuit. The experimental results in a 0.18-μm CMOS process have verified that the proposed transient detection circuit can successfully detect and memorize the occurrence of electrical transients during system-level ESD or EFT testing conditions.

Fig. 2. Equivalent circuit of the ESD gun used in the system-level ESD test [12].

Fig. 3. MeasuredVDDandVSSwaveforms of the microcontroller ICs inside the keyboard under system-level ESD test [22].

II. TESTS OFSYSTEM-LEVELELECTRICAL-TRANSIENT

DISTURBANCE

A. System-Level ESD Test

The standard of IEC 61000-4-2 defines the immunity re-quirements and test methods for microelectronic products to a system-level ESD event [12]. Under system-level ESD tests, the ESD energy is released from the ESD gun. The equivalent circuit of the ESD gun used in the system-level ESD test is shown in Fig. 2. Different discharge tips are used for two different discharge test modes. The round tip of the ESD gun is used for the air-discharge test and brought close to the EUT. The sharp tip of the ESD gun is used for the contact-discharge test and held in contact with the EUT. The ESD gun has a charging (energy-storage) capacitor of 150 pF and a discharging resistor of 330 Ω. It has been reported that a robust CMOS IC product with high component-level ESD level could still be very susceptible to the system-level ESD test [15]. The inset of Fig. 3 shows an EUT (keyboard) that was stressed by an ESD gun with a charged voltage of +1 kV zapping on the horizontal coupling plane (HCP). During the system-level ESD test, the power/ground lines of the microcontroller IC inside the keyboard no longer maintain their normal voltage levels, but an

Fig. 4. Simplified circuit diagram of the EFT generator [13].

underdamped sinusoidal voltage with an amplitude of several tens of volts occurred, as shown in Fig. 3.

B. EFT Test

The standard of IEC 61000-4-4 defines the immunity require-ments and test methods for electronic equipment to repetitive fast transients [13]. The EFT is a test with repetitive burst string consisting of a number of fast pulses, coupled to the power supply, control, signal, and ground ports of microelectronic products. The characteristics of EFT are high amplitude, short rise time, and high repetition rate of the transients. The EFT test is intended to demonstrate the immunity of microelectronic products to transient disturbances, such as those originating from switching transients (interruption of inductive loads, relay contact bounce, etc.).

According to the standard of IEC 61000-4-4, the simplified circuit diagram of the EFT generator is shown in Fig. 4, with an impedance-matching resistor R_m of 50 Ω and a dc-blocking capacitor C_d of 10 nF. The charging capacitor C_c is used to store the charging energy, andRc is the charging resistor.

ResistorRsis used to shape the pulse duration.

The standard of IEC 61000-4-4 defines the test voltage waveforms of these fast transients with repetition frequencies of 5 and 100 kHz. The use of 5-kHz repetition rate is the traditional EFT test, and 100 kHz is closer to reality. For an EFT pulse with a repetition frequency of 5 kHz, there are 75 pulses in each burst string, and the burst duration time is 15 ms. For an EFT pulse with a repetition frequency of 100 kHz, there are 75 pulses in each burst string, and the burst duration time is only 0.75 ms. For both repetition rates, the burst string repeats every 300 ms.

For EFT pulses with a repetition frequency of 5 kHz, the measured+200- and −200-V voltage waveforms on the 1-kΩ load are shown in Fig. 5(a) and (b), respectively. Because the output loading (1 kΩ) is larger than impedance-matching resistor Rm (50Ω), the measured output pulse peak is close

to the input EFT voltage pulse. As shown in Fig. 5(a) and (b), the measured output pulse peaks on the 1-kΩ load are approx-imately+200 and −200 V, respectively. For an EFT repetition frequency of 5 kHz, the time interval between each pulse is 0.2 ms. Under EFT tests, the application time should not be less than 1 min, and both polarities have to be tested.

With the 1-kΩ load, the voltage waveforms of a single pulse with EFT voltages of+200 and −200 V are shown in the inset of Fig. 5(a) and (b), respectively. The EFT waveforms of a single pulse have a rise time of∼5 ns and a pulse duration (time interval at half of the peak EFT voltage) of∼50 ns.

Fig. 5. Measured voltage waveforms under EFT tests with EFT voltages of (a)+200 V and (b) −200 V on a 1-kΩ load with a repetition rate of 5 kHz.

III. NEWTRANSIENTDETECTIONCIRCUIT

The transient detection circuit is designed to detect the posi-tive or negaposi-tive fast electrical transients after system-level ESD or EFT tests. Under normal power supply condition (VDD= 1.8 V), the output state (VOUT) of the proposed transient detection circuit is kept at 0 V as logic “0.” After transient disturbance, the output state(VOUT) of the proposed transient detection circuit will transit from 0 to 1.8 V as logic “1.” Therefore, the proposed transient detection circuit can mem-orize the occurrence of transient disturbance events.

A. Circuit Implementation

Fig. 6 shows the proposed transient detection circuit. An NMOS (Mnr) is used to provide the initial reset function to set the initial voltage level to 0 V at node V1 and the output node (VOUT). CP is the parasitic capacitance on node V1 of

the transient detection circuit. In Fig. 6, nodeVX is biased at VDDduring the normal operating condition. Under system-level ESD or EFT tests, the transient voltage coupled to theVDDline has a fast rise time on the order of nanoseconds. The voltage level ofV_Xhas a much slower voltage response than the voltage

Fig. 6. New proposed on-chip transient detection circuit. TABLE I

DEVICEDIMENSIONSUSED IN THEPROPOSED

TRANSIENTDETECTIONCIRCUIT

level atVDDbecause theRC circuit has a time constant on the order of microseconds. Due to the longer delay of the voltage increase at nodeV_X, the PMOS device(M_{P 1}) can be turned on by the overshooting transient voltage atVDDto pull up the voltage level at nodeV1. Therefore, the logic level stored at node V1 can be changed during transient disturbance events. Finally, the output voltage of the proposed transient detection circuit can transit from 0 to 1.8 V to memorize the occurrence of system-level electrical-transient disturbance after system-level ESD or EFT tests. The device dimensions(W/L) used in the proposed transient detection circuit are listed in Table I.

B. HSPICE Simulation

1) System-Level ESD Testing Conditions: From the

mea-sured electrical-transient waveforms shown in Fig. 3, the un-derdamped sinusoidal voltage waveform on the power line of the CMOS IC during system-level ESD stress has been observed. There, a sinusoidal time-dependent voltage source with a damping factor parameter given by

V (t) = V0+ Va· sin (2πf(t − td)) · exp (−(t − td)Da) (1)

is used to simulate an underdamped sinusoidal voltage on the power lines of the proposed transient detection circuit. With the proper parameters (including applied voltage amplitudeVa,

initial dc voltageV0, damping factorDa, frequencyf, and time

delaytd), the underdamped sinusoidal voltage can be used to

simulate the electrical-transient waveforms under system-level ESD tests. In HSPICE simulation with positive- or negative-going underdamped sinusoidal waveforms, the same parame-ters of Da= 2 × 107 s−1, f = 50 MHz, and td= 300 ns

are used (which is corresponding to the measured transient waveforms in Fig. 3). For the positive-going (negative-going) underdamped sinusoidal waveform, the polarity ofV_a parame-ter is positive (negative).V0is the initial voltage of the applied

Fig. 7. SimulatedVDDandVOUTwaveforms of the new proposed on-chip transient detection circuit under system-level ESD test with (a) positive-going and (b) negative-going underdamped sinusoidal voltages.

transient waveform. When the transient waveform is applied to

VDD(VSS), V0is set to 1.8 V (0 V) in the simulation.

The simulated VDD and VOUT waveforms of the proposed transient detection circuit with a positive-going underdamped sinusoidal voltage on the VDD line are shown in Fig. 7(a). The positive-going underdamped sinusoidal voltage with an amplitude of +2.5 V is used to simulate the coupling ESD transient noise under system-level ESD test. From the simulated waveforms, VDD begins to increase rapidly from 1.8 to 4 V.

VOUTalso acts with a positive-going underdamped sinusoidal voltage waveform during the simulated transient disturbance on theVDDline. After this disturbance duration,VDDreturns to its normal voltage level of 1.8 V, and the output state(VOUT) of the proposed transient detection circuit is changed from 0 to 1.8 V, as shown in Fig. 7(a). As a result, the proposed transient detection circuit can detect the occurrence of positive-going ESD-induced underdamped sinusoidal transient disturbance on theVDDline.

The simulated VDD and VOUT waveforms of the proposed transient detection circuit with a negative-going underdamped sinusoidal voltage onVDDare shown in Fig. 7(b). The negative-going underdamped sinusoidal voltage with an amplitude of

−3 V is used to simulate the coupling ESD transient noise

simulated waveforms,VDDbegins to decrease rapidly from 1.8 to−1 V. VOUT also acts with a negative-going underdamped sinusoidal voltage waveform during the simulated transient disturbance on the VDD line. After this disturbance duration,

VDD returns to its normal voltage level of 1.8 V, and the output state(VOUT) of the proposed transient detection circuit is changed from 0 to 1.8 V, as shown in Fig. 7(b). Therefore, the proposed transient detection circuit can detect the occurrence of negative-going ESD-induced underdamped sinusoidal transient disturbance on theVDDline.

2) EFT Testing Conditions: For microelectronic products,

the shielding plate is often designed into microelectronic prod-ucts to bypass or reduce the EFT-induced electrical-transient disturbance. Therefore, the electrical transients injected into the CMOS ICs inside the microelectronic products can be degraded with smaller amplitude compared with the original testing voltage. Therefore, the EFT-induced transients with different degraded amplitudes are taken into considerations in HSPICE simulation on the proposed transient detection circuit.

From the measured electrical-transient waveforms shown in Fig. 5(a) and (b), the approximated exponential voltage pulse waveforms during EFT tests have been observed. There, an exponential pulse time-dependent voltage source with rise/fall-time constant parameters is used to simulate EFT-induced tran-sient disturbance on the proposed trantran-sient detection circuit. The rising edge of this exponential time-dependent voltage pulse is expressed as Vp(rise)(t) = V1+ (V2− V1) ×  1 − exp  −t − td1 τ1  , whentd1 ≤ t ≤ td2. (2)

The falling edge of this exponential time-dependent voltage pulse is expressed as Vp(fall)(t) = V1+ (V2− V1) ×  1 − exp  −t − td1 τ1  + (V1− V2)  1 − exp  −t − td2 τ2  , when t ≥ td2. (3)

With the proper parameters (including rise-time constantτ1, fall-time constantτ2, rise-time delaytd1, fall-time delaytd2,

initial dc voltage valueV1, and exponential pulse voltage value

V2), the exponential voltage pulse can be constructed to simu-late the EFT-induced disturbance under EFT tests. In HSPICE simulation with positive or negative exponential voltage pulse waveforms, the same parameters of τ1= 3 ns, τ2= 25 ns, andtd2− td1= 10 ns are used [which is corresponding to the

measured transient waveforms in Fig. 5(a) and (b)].

For the positive exponential voltage pulse, the value ofV2 parameter is larger than the value of V1 parameter. For the negative exponential voltage pulse, the polarity of V2− V1 parameter is negative. In addition, V1 is 1.8 V as the initial dc voltage on theVDDline of the proposed transient detection circuit.

The simulatedVDD andVOUT waveforms of the proposed transient detection circuit with a positive exponential pulse transient disturbance on the VDD line are shown in Fig. 8(a).

Fig. 8. SimulatedVDDandVOUTwaveforms of the new proposed on-chip transient detection circuit under EFT tests with (a) positive and (b) negative exponential voltage pulse waveforms coupled toVDD.

The exponential voltage pulse with an amplitude of +2.5 V is used to simulate the coupling positive transient disturbance under EFT test. From the simulated waveforms, VDD begins to increase rapidly from 1.8 to +4 V. VOUT also acts with a positive exponential voltage pulse waveform during the simu-lated transient disturbance on theVDD line. After the transient disturbance duration,VDDreturns to its normal voltage level of 1.8 V, and the output state(VOUT) of the proposed transient de-tection circuit transits from 0 to 1.8 V, as shown in Fig. 8(a). As a result, the proposed transient detection circuit can detect the occurrence of positive EFT-induced exponential pulse transient disturbance.

The simulated VDD andVOUT waveforms of the proposed transient detection circuit with a negative exponential pulse transient disturbance on the VDD line are shown in Fig. 8(b). The exponential voltage pulse with an amplitude of −3.5 V is used to simulate the coupling negative transient disturbance under EFT test. From the simulated waveforms,VDDbegins to decrease rapidly from 1.8 to−1 V. VOUTalso acts with a neg-ative exponential voltage pulse during the simulated transient disturbance on the VDD line. After the transient disturbance duration,VDDreturns to its normal voltage level of 1.8 V, and the output state (VOUT) of the proposed transient detection

circuit transits from 0 to 1.8 V, as shown in Fig. 8(b). As a result, the proposed transient detection circuit can detect the occurrence of negative EFT-induced exponential pulse transient disturbance.

From the aforementioned simulation results shown in Fig. 8(a) and (b), the proposed transient detection circuit can successfully memorize the occurrence of positive or negative EFT-induced exponential pulse transient disturbance.

C. Consideration With Leakage

The voltage level at nodeV1 of the proposed transient de-tection circuit will be charged high after ESD/EFT electrical transitions, such as those shown in the aforementioned simula-tion results to get the output node voltage changing from 0 V to 1.8 V. However, after electrical transition,MP 1andMN 1will

be switched to OFF state again. The charged voltage at node

V1 would be leaked down due to the parasitic drain junction diodes of the transistors in the circuit. If the leakage current of the parasitic diodes of the transistors connecting to parasitic capacitance(C_P) on node V1 is taken into consideration, the discharge time of the chargedV1with this parasitic capacitance to cause the output nodeVOUTto return to 0 V due to leakage can be estimated from the following:

CP×



V1(max)−VDD₂ 

= ILeakage× Δt (4)

where ILeakage is the leakage current. The logic threshold voltage of the buffer stage is often designed about half of the supplied voltage. The maximum voltage staying on node V1 will be aroundVDDplus the threshold voltage of theMP 1

de-vice. The higher voltage charged to nodeV1will be discharged back to VDD through the channel current of the MP 1 device

after ESD/EFT electrical transitions. The parasitic capacitance (CP) is about 0.3 pF in this design, with the device dimensions

being listed in Table I. If the leakage current is assumed to be 30 pA (process-dependent parameter), the estimated discharge time is about 10 ms, which is long enough for the firmware to execute system autorecovery procedures. After that, nodeV1 will be reset to 0 V again for detecting the next events of ESD or EFT transitions.

IV. EXPERIMENTALRESULTS

The proposed transient detection circuit has been designed and fabricated in a 0.18-μm 1P5M CMOS process. The fabri-cated chip for transient disturbance tests is shown in Fig. 9.

A. TLU Test

With the system-level ESD test, it can only judge whether the EUT passes the required criterion through its abnormal function (e.g., EUT shuts down). Nevertheless, it is hard to directly evaluate the system-level ESD immunity of a single IC inside the EUT. To solve this problem, a component-level TLU measurement setup was reported [28] with the following two advantages. First, the TLU immunity of a single IC can be evaluated by the measured voltage and current waveforms

Fig. 9. Die photograph of the new proposed on-chip transient detection circuits fabricated in a 0.18-µm CMOS process.

Fig. 10. Measurement setup for TLU [25].

through an oscilloscope. Second, with the ability of generating an underdamped sinusoidal voltage, how an IC inside the EUT is disturbed by the ESD-generated noise during the system-level ESD test can be accurately simulated. Fig. 10 shows such a component-level TLU measurement setup. An ESD simulator is used to generate the TLU-triggering source(VCharge) to pro-duce an underdamped sinusoidal voltage stimulus. By applying a positive (negative) charged voltage VCharge, the intended positive-going (negative-going) underdamped sinusoidal volt-age can be generated similarly with that generated from the ESD gun during the system-level ESD test.

In the measurement setup shown in Fig. 10, a charging capacitance of 200 pF is used to store charges for the TLU-triggering source(VCharge), and then, these stored charges are discharged to the device under test (DUT) through a relay. The intended underdamped sinusoidal voltage can be produced to simulate the transient voltage on the power pins of CMOS ICs under system-level ESD test, no matter which polarity (positive or negative) the ESD voltage is. Moreover, a small current-limiting resistance of 5Ω is recommended to protect the DUT from electrical-overstress damage during a high-current (low-impedance) latchup state [25]. A supply voltage of 1.8 V is used as VDD, and the triggering source is directly connected to the DUT through the relay in the measurement setup.

Fig. 11(a) and (b) shows the measured VDD and VOUT transient responses of the proposed transient detection circuit under TLU test withVCharge’s of +8 and −1 V, respectively.

Fig. 11. MeasuredVDDandVOUTwaveforms on the new proposed on-chip transient detection circuit under TLU tests withVCharge’s of (a)+8 V and (b)−1 V.

As shown in Fig. 11(a), under TLU test with aVChargeof+8 V,

VDDbegins to increase rapidly from 1.8 V with positive-going underdamped sinusoidal voltage waveform. During the TLU test, VOUT is influenced simultaneously with positive-going underdamped sinusoidal voltage coupled to theVDDpower line. After the TLU test with aVChargeof+8 V, the output voltage (VOUT) of the proposed transient detection circuit can transit from 0 to 1.8 V. In Fig. 11(b), under TLU test with aVChargeof

−1 V, VDDbegins to decrease rapidly from 1.8 V with negative-going underdamped sinusoidal voltage waveform. During the TLU test, VOUT is influenced simultaneously with negative-going underdamped sinusoidal voltage coupled to the VDD power line. After the TLU test with a VCharge of −1 V, the output voltage (VOUT) of the proposed transient detection circuit can transit from 0 to 1.8 V.

From the TLU test results, the proposed transient detection circuit can successfully memorize the occurrence of electrical transients. With positive or negative underdamped sinusoidal voltages coupled to the VDD power line, the output voltages (VOUT’s) of the proposed transient detection circuit can be changed from 0 to 1.8 V after TLU tests.

Fig. 12. Measurement setup for a system-level ESD test with indirect contact-discharge test mode [12] to evaluate the detection function of the fabricated on-chip transient detection circuit.

B. System-Level ESD Test

In IEC 61000-4-2, two test modes have been specified, which are the air- and contact-discharge test modes. In the case of air-discharge test mode, the round discharge tip should be approached as fast as possible to touch the EUT. The air discharge is actuated by a spark to the EUT, and the ESD energy holding time is at least 5 s. The contact discharge is applied to the conductive surfaces of the EUT (direct application) or to the horizontal or vertical coupling planes (indirect application). Fig. 12 shows the measurement setup of the system-level ESD test standard with indirect contact-discharge test mode. The measurement setup of the system-level ESD test consists of a wooden table on the grounded reference plane (GRP). In addition, an insulation plane is used to separate the EUT from the HCP. The HCP is connected to the GRP with two 470-kΩ resistors in series. When the ESD gun zaps the HCP, the electromagnetic interference coming from the ESD gun will be coupled into all CMOS ICs inside the EUT. The power lines of the CMOS ICs inside the EUT will be disturbed by the ESD-coupled energy.

According to the IEC 61000-4-2 standard, under system-level ESD test with direct contact-discharge test mode, the discharge tip should apply to the metallic shell or accessi-ble connector/surface of microelectronic products. The ESD-induced transient disturbance can couple into the CMOS ICs inside the microelectronic products. Therefore, under system-level ESD with direct/indirect contact-discharge modes, the CMOS ICs inside the microelectronic products are suffering the coupled ESD-induced electrical-transient disturbance. By using the insulation plane between the EUT and HCP, the indirect contact-discharge mode can couple ESD transient noise into the test chip inside the PCB. Therefore, in this paper, the indirect contact-discharge mode is used as the test mode to evaluate the detection function/performance of the proposed transient detection circuit.

By using a digital oscilloscope, the transient responses on the power lines and output signals of CMOS IC products can be recorded and analyzed. Before each system-level ESD test, the initial output voltage (VOUT) of the proposed transient detection circuit is reset to 0 V. After each system-level ESD test, the output-voltage(VOUT) level is monitored to check the

Fig. 13. MeasuredVDDandVOUTtransient voltage waveforms of the new proposed on-chip transient detection circuit under system-level ESD tests with ESD voltages of (a)+0.2 kV and (b) −0.2 kV.

final voltage level and to verify the detection function. Thus, the circuit function of the proposed transient detection circuit can be evaluated by the system-level ESD test.

The measuredVDD and VOUT waveforms of the proposed transient detection circuit under system-level ESD test with an ESD voltage of +0.2 kV zapping on the HCP are shown in Fig. 13(a). VDD begins to increase rapidly from the normal voltage of+1.8 V. Meanwhile, VOUTis disturbed under such a high-energy ESD stress. During the period with positive-going ESD-induced electrical-transient disturbance,VDD and

VOUTare influenced simultaneously. Finally, the output voltage (VOUT) of the proposed transient detection circuit transits from 0 to 1.8 V. Therefore, the proposed transient detection circuit can sense the positive-going electrical transient on the power line and memorize the occurrence of system-level ESD event.

The measuredVDDandVOUTtransient voltage waveforms of the proposed transient detection circuit with an ESD voltage of

−0.2 kV zapping on the HCP under system-level ESD test are

shown in Fig. 13(b). During the negative-going ESD-induced electrical-transient disturbance on theVDDpower line,VOUTis disturbed simultaneously. After the system-level ESD test with

Fig. 14. Measurement setup for an EFT test combined with an attenuation network.

an ESD voltage of−0.2 kV, VOUTtransits from 0 to 1.8 V. The detection function of the transient detection circuit after system-level ESD tests has been verified by the experimental results in silicon chip and HSPICE simulation.

C. EFT Test

In order to simulate the EFT-induced transient disturbance on CMOS ICs inside the microelectronic products, the attenuation network with −40 dB degradation is used in this paper. The amplitude of EFT-induced transients can be adjusted through the attenuation network.

The measurement setup for the EFT test combined with the attenuation network is shown in Fig. 14. The EFT generator is connected to the DUT through the attenuation network with a

VDD of 1.8 V. TheVDD andVOUTtransient responses of the proposed transient detection circuit are monitored by a digital oscilloscope. Before each EFT test, the initial output voltage (VOUT) of the proposed transient detection circuit is reset to 0 V. After each EFT test, the output-voltage (VOUT) level is monitored to check the final voltage level and to verify the detection function.

Fig. 15(a) and (b) shows the measured VDD and VOUT transient responses of the proposed transient detection circuit under EFT tests with input EFT voltages of+200 and −300 V, respectively. As shown in Fig. 15(a), under EFT test with a positive voltage of+200 V, VDDbegins to increase rapidly from 1.8 V with positive exponential voltage pulse. During the EFT test,VOUTis influenced simultaneously with positive exponen-tial voltage pulse coupled to the VDD power line. After the EFT test, the output voltage(VOUT) of the proposed transient detection circuit transits from 0 to 1.8 V. In Fig. 15(b), under EFT test with a negative voltage of −300 V, VDD begins to decrease rapidly from 1.8 V with negative exponential voltage pulse. After the EFT test, the output voltage (VOUT) of the proposed transient detection circuit transits from 0 to 1.8 V.

From the EFT test results shown in Fig. 15(a) and (b), with positive or negative exponential voltage pulses coupled to the

VDD power line, the output voltages(VOUT) of the proposed transient detection circuit can be changed from 0 to 1.8 V. The experimental results are consistent with the HSPICE simulation results under positive and negative EFT zapping conditions, as shown in Fig. 8(a) and (b). Therefore, the proposed transient

Fig. 15. MeasuredVDDandVOUTwaveforms on the new proposed on-chip transient detection circuit under EFT tests with (a) positive and (b) negative EFT voltages combined with an attenuation network.

detection circuit can successfully memorize the occurrence of EFT-induced exponential pulse transient disturbance.

In IEC 61000-4-4, the capacitive coupling clamp has been recommended as another measurement setup to couple the EFT testing voltages into the EUT. The capacitive coupling clamp provides the ability of coupling the fast transients and bursts to the circuit under test without any galvanic connection to the terminals of the EUT, shielding the cables or any other part of the EUT. The coupling capacitance of the clamp depends on the diameter, material of the cables, and shielding. The typical coupling capacitance between the cable and clamp ranges from 50 to 200 pF. For providing maximum coupling capacitance be-tween the cable and the clamp, the EFT generator is connected to the end of the clamp that is nearest to the EUT.

The measurement setup for the EFT test combined with the capacitive coupling clamp is shown in Fig. 16. The capacitive coupling clamp is connected with the EFT generator to directly couple the EFT testing voltages into theVDD cable line. The

VDD andVOUT voltage waveforms of the proposed transient detection circuit are monitored by a digital oscilloscope during EFT tests combined with the capacitive coupling clamp.

Fig. 16. Measurement setup for an EFT test combined with a capacitive coupling clamp.

Fig. 17. MeasuredVDDandVOUTtransient voltage waveforms of the new proposed on-chip transient detection circuit under EFT tests with EFT voltages of (a)+200 V and (b) −200 V combined with a capacitive coupling clamp.

Fig. 17(a) and (b) shows the measured VDD and VOUT transient responses of the proposed transient detection circuit under EFT test with input EFT voltages of+200 and −200 V, respectively. As shown in Fig. 17(a), under EFT tests with an input EFT voltage of+200 V, VDDbegins to increase rapidly from 1.8 V with positive-going underdamped sinusoidal voltage

Fig. 18. Firmware flowchart to recover the system when electrical transients happen.

waveform. During the EFT test, VOUT is influenced simulta-neously with positive-going underdamped sinusoidal voltage coupled to the VDD power line. After the EFT test with an input EFT voltage of +200 V, the output voltage (VOUT) of the proposed transient detection circuit transits from 0 to 1.8 V. In Fig. 17(b), under EFT test with an EFT voltage of−200 V,

VDDbegins to decrease rapidly from 1.8 V with negative-going underdamped sinusoidal voltage waveform. After the EFT test with an input EFT voltage of −200 V, the output voltage (VOUT) of the proposed transient detection circuit transits from 0 to 1.8 V.

From the EFT test results shown in Fig. 17(a) and (b), the new proposed on-chip transient detection circuit can success-fully memorize the occurrence of positive- or negative-going EFT-induced underdamped sinusoidal transient disturbance.

D. Hardware/Firmware Codesign

It has been proven that the hardware/firmware codesign can effectively improve the robustness of microelectronic products against system-level ESD and EFT stresses [21]. To perform the hardware/firmware codesign, the detection result from the transient detection circuit can be temporarily stored as a system recover index for firmware check. For example, the output (VOUT) state of the transient detection circuit is initially reset to logic “0” in the beginning by the power-on reset circuit. When electrical transients happen, the transient detection circuit can detect the occurrence of system-level electrical-transient distur-bance and transit the output state(VOUT) to logic “1.” At this moment, the system-check index is also changed to logic “1” to initiate the firmware recover procedure to restore the system to a known stable state as soon as possible. After the recover procedure, the output of the transient detection circuit and the firmware index are reset to logic “0” again for detecting the next electrical-transient disturbance events. The firmware flowchart is shown in Fig. 18.

The power-on reset circuit is designed to reset the system operation after power-on transition. Under normal power-on

condition, theVDDpower-on voltage waveform has a rise time on the order of milliseconds. As there is no input signal except power-on voltage waveform, the power-on reset circuit is often designed with an internal delay that is longer than the rise time of power-on transition. The proposed transient detection circuit is designed to detect the ESD- or EFT-induced fast electrical transients in the range of nanoseconds. However, if the power-on reset circuit would be mistriggered under electrical-transient disturbance, a two-input OR logic-gate circuit can be further added into the hardware/firmware codesign flow. The output signals of the power-on reset and transient detection circuits are connected as the two-input signals of theORlogic gate. When electrical-transient disturbance happens, the system recovery procedure can be still initiated to protect the microelectronic products against the electrical transitions from system-level ESD and EFT events.

V. CONCLUSION

A new on-chip transient detection circuit has been pro-posed and successfully verified in a 0.18-μm CMOS process. The detection function under different positive or negative system-level electrical-transient disturbance has been investi-gated by HSPICE simulation. The experimental results in sili-con chip have successfully verified that the proposed transient detection circuit can detect and memorize the occurrence of electrical transients under system-level ESD or EFT testing conditions. With hardware/firmware codesign, the proposed transient detection circuit can be used as a firmware index to provide an effective solution against the malfunction in micro-electronic products caused by system-level electrical-transient disturbance.

ACKNOWLEDGMENT

The authors would like to thank C.-C. Tsai and Dr. T.-Y. Chen for their valuable technical discussions and Himax Technologies, Inc., Taiwan, for the project support.

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Ming-Dou Ker (S’92–M’94–SM’97–F’08) received

the Ph.D. degree from the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, in 1993.

He was a Department Manager with the Very Large Scale Integration (VLSI) Design Division, Computer and Communication Research Labora-tories, Industrial Technology Research Institute, Hsinchu, Taiwan. Since 2004, he has been a Full Professor with the Nanoelectronics and Gigas-cale Systems Laboratory, Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan. In 2008, he was rotated to be Chair Professor and Vice President of I-Shou University, Kaohsiung, Taiwan. Currently, he is the Dis-tinguished Professor in the Department of Electronics Engineering, National Chiao Tung University; and also serves as the Executive Director of the National Science and Technology Program on System-on-Chip (NSoC) in Taiwan. In the field of reliability and quality design for circuits and systems in CMOS technology, he has authored or coauthored over 400 technical papers in international journals and conferences. He is the inventor of 165 U.S. and 147 Taiwan patents due to his many inventions to improve the reliability and quality of ICs. He had been invited to teach and/or to consult the reliability and quality design for IC products by hundreds of design houses and semiconductor companies in the worldwide IC industry. His current research interests include reliability and quality design for nanoelectronics and gigascale systems, high-speed and mixed-voltage I/O interface circuits, on-glass circuits for system-on-panel applications, and biomimetic circuits and systems for intelligent prosthesis.

Dr. Ker has served as a member of the Technical Program Committee and the Session Chair of numerous international conferences. He has also served as an Associate Editor for the IEEE TRANSACTIONS ONVLSI SYSTEMS. He was selected as the Distinguished Lecturer in the IEEE Circuits and Systems Society (2006–2007) and the IEEE Electron Devices Society (2008–2010). He was the President of Foundation in the Taiwan ESD Association.

Cheng-Cheng Yen (S’07–M’09) received the B.S.

degree from the Department of Electrical and Con-trol Engineering, National Tsing Hua University, Hsinchu, Taiwan, in 1998 and the M.S. and Ph.D. degrees from the Institute of Electronics, National Chiao Tung University, Hsinchu, in 2000 and 2009, respectively.

He is currently a Postdoctoral Researcher with National Chiao Tung University. His current research interests include transient detection circuits and IC reliability.