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行政院國家科學委員會補助專題研究計畫 □期中進度報告
■期末報告
奈米互補式金氧半場效電晶體靜態隨機存取記憶體靜態雜訊邊界與
負偏壓溫度效應/正偏壓溫度效應之量測與特性化電路結構設計
計畫類別：■個別型計畫 □整合型計畫
計畫編號：NSC 99-2221-E-009 -183-MY2
執行期間： 99 年 8 月 1 日至 101 年 7 月 31 日
執行機構及系所：國立交通大學電子工程學系
計畫主持人： 莊景德 (教授)
共同主持人： 周世傑 (教授)
計畫參與人員：楊皓義 (博畢，100.09), 林宜緯 (碩畢，99.10)
蔡銘謙 (碩畢，100.02), 林耕慶 (碩畢，100.10)
王紹丞 (碩畢，100.09), 胡育豪 (碩畢，101.09)
朱俐瑋 (碩畢，101.10),
廖偉男 (碩畢，預計 101.11)
張智皓 (碩士生),
陳淑卿 (兼任行政助理)
本計畫除繳交成果報告外，另須繳交以下出國心得報告：
□赴國外出差或研習心得報告
□赴大陸地區出差或研習心得報告
■出席國際學術會議心得報告
□國際合作研究計畫國外研究報告
處理方式：
除列管計畫及下列情形者外，得立即公開查詢
□涉及專利或其他智慧財產權，□一年□二年後可公開查詢
中 華 民 國 101 年 10 月 30 日
附件一2
電子工程學系
計畫名稱：奈米互補式金氧半場效電晶體靜態隨機存取記憶體靜態雜訊邊界與負偏壓溫度效應/正偏壓 溫度效應之量測與特性化電路結構設計 研究者：莊景德, 周世傑 經費來源：行政院國家科學委員會 關鍵詞：靜態隨機存取記憶體穩定度; 靜態雜訊邊界；長時間可靠度劣化; 負偏壓溫度效應; 正偏壓溫 度效應 隨著製程微縮至次-100 奈米領域，漏電、元件參數變異、及長時間可靠度劣化己成為互補式金氧 半場效電晶體靜態隨機存取記憶體的穩定度、可微縮性、及效能的主要限制。先進微處理機所使用的 快速記憶體及系統晶片(SoC) 的嵌入式記憶體需要大容積的靜態隨機存取記憶體及超過 +/- 5 個標準 差 (5σ) 的設計規格。因此以儲存位元及/或靜態隨機存取記憶體產品層次的位元列陣為基礎來設計的 特定量測與特性化電路結構設計日益重要。與此同時, 金氧半場效電晶體靜態隨機存取記憶體的生命 週期可靠度由於受到各種長時間可靠度劣化現象, 如熱載子效應 (Hot Carrier Effect) 、 P-型場效電晶體的負偏壓溫度效應、 高電介質金屬閘極 N-型場效電晶體的正偏壓溫度效應、時間相依介電質崩潰、 輻射性損壞等，的影響而急遽惡化。其中負偏壓溫度效應與正偏壓溫度效應使得臨界電壓，VT，隨著 使用的生命週期而偏移。因此之故，用以量測負偏壓溫度效應及正偏壓溫度效應, 並能讓設計者施以 適當的劣化加速壓温以量測及特性化其對記憶體穩定度劣化影響的量測電路結構己成為一個重要的研 發課題。 在這個 2 年的研究計劃中，我們將與智原科技，針對奈米級靜態隨機存取記憶體的靜態雜訊邊界 及負偏壓溫度效應與正偏壓溫度效應，共同研發量測與特性化的電路結構。我們將併行研發以儲存位 元為基礎 (如環型振盪器)及以靜態隨機存取記憶體產品層次的位元列陣 (SRAM cell array) 為基礎的 特定量測與特性化電路結構及量測技術。更進一步地，我們會將研發的電路結構及量測技術應用到靜 態隨機存取記憶體的穩定度及複晶閘極 (poly-gate) 互補式金氧半場效電晶體靜態隨機存取記憶體的 負偏壓溫度效應的量測及特性化。我們更將建構一套陣列層級讀取及寫入監/量測技術用以量測靜態隨 機存取記憶體位元陣列的雜訊邊界特性,藉此架構使得電路設計者可以得到關於靜態隨機存取記憶體 穩定度更多有意義的相關設計資訊。最後，我們將會建構一套可以整合觀察負溫度偏壓效應/正溫度偏 壓效應造成的退化效應與靜態隨機存取記憶體穩定度的架構。
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Department of Electronics Engineering
Title：Measurement and Characterization Structures for Static Noise Margin and NBTI/PBTI Degradation of
Nanoscale CMOS SRAM
Principal Investigator： Ching-Te Chuang and Shyh-Jye Jou Sponsor：National Science Council
Keywords：SRAM Stability, Static Noise Margin, Long Term Degradation, Negative Bias Temperature
Instability, Positive Bias Temperature Instability
With technology scaling down to deep sub-100 nm regime, leakage, variation and long-term degradation have surfaced to constrain the stability, scalability and attainable performance of CMOS SRAM. State-of-the-art processor cache memory and SoC embedded memory require large capacity SRAM with over +/-5σ design, and the ability to measure/characterize the Static Noise Margin (SNM) based on specific cell test structures and/or product level SRAM array has become ever-increasingly important. Meanwhile, the lifetime reliability of nanoscale CMOS SRAM suffers from long term degradation such as Hot Carrier Injection (HCI), Negative Bias Temperature Instability (NBTI, for pMOS), Poasitive Bias Temperature Instability (PBTI, for high- κ metal-gate nMOS), Time-Dependent Dielectric Breakdown (TDDB), radiation-induced damage, etc.. In particular, NBTI/PBTI cause the threshold voltage, VT, to drift over the life
span of usage, thus severely degrading the stability, margin, performance, and lifetime reliability. As such, SRAM NBTI/PBTI measurement structures, which allow designers to apply relevant stresses and characterize resulting stability degradation, have become a key research subject.
In this 2 year project, jointly with Faraday Technology Corporation (智原科技), we will develop measurement and characterization structures for Static Noise Margin and NBTI/PBTI for nanoscale CMOS SRAM. Both individual cell based structures (e.g. ring oscillator) and product array level techniques will be investigated. We will then apply the structures and measuring techniques to the characterization of SRAM stability and NBTI degradation (for poly-gate technology). Further, we will develop array-level measurement techniques to observe the characteristics of cells in SRAM cell array, and develop the architecture for
measuring the Static Noise Margin (SNM) to provide designer with more direct and significant information about the SRAM stability and design margin. Finally, we will build up a bridge between the measurement of NBTI and PBTI degradation and the resulting impact on SRAM
4 前言及文獻探討。
With technology scaling down to deep sub-100 nm regime, leakage, variation and long-term degradation have surfaced to constrain the stability, scalability and attainable performance of CMOS SRAM [1]. The rapid increase in local random VT variation, against the backdrop of lower supply voltage and
increasing memory capacity in state-of-the-art processors and SoC, has rendered the redundancy needed for repair impractical, and even prohibitive for designs below +/-5σ. For 6T SRAM, the major limiting factors in the design domain are the conflicting Read/Write requirements and cell disturbs [1, 2]. The variations in the Read-disturb voltage (“Cell down-level”) and inverter Trip voltage (“Cell switch-point”) increase, causing overlap and thus failure starting at 90 nm node [2]. As such, the ability to physically measure/characterize the SRAM Static Noise Margin (SNM) [3] has become increasingly important for proper understanding, modeling, and calibration of the design margin to ensure acceptable yield under the target performance metrics.
In addition to leakage and variation, NBTI (Negative Bias Temperature Instability) [4] has long been a limiting factor in the scaling of PMOS. At high negative bias and elevated temperature, the PMOS VT
gradually drifts to become more negative, thus reducing PMOS current drive and affecting cell stability, margin, and VMIN of SRAM [5]. Furthermore, with high-κ gate materials, PBTI (Positive Bias Temperature
Instability) in NMOS must be considered, as high-κ gates exhibit significant charge trapping and thus VT shift
in NMOS [6].
These long term VT drift and other gate oxide related VT degradation mechanisms must be properly
accounted for over the SRAM life span of usage [7-9]. Hence, SRAM stability and NBTI/PBTI measurement/characterization structures, which allow designers to apply relevant stresses and characterize stability and degradation, have become a key research subject.
The measurement/characterization structures for Static Noise Margin and NBTI/PBTI degradation can be either individual cell/device based or in a product array level environment. The individual cell based Static Noise Margin measurement/characterization structures are typically used in the early stage of SRAM cell technology/process development, where developers need to characterize various cell design/layout/groundrules, and through hardware cycles and measurement/characterization, decide on the final/proper cells to use. Typical structures consists of column or columns of cells with all internal nodes of a cell accessible externally [10, 11].
For measurement/characterization of NBTI/PBTI for individual devices, the most primitive approach utilizes two simple standard ring oscillators. One of the ring oscillators goes through NBTI/PBTI stress, and the frequency of this “stressed” ring oscillator is then compared with that of the “unstressed” ring oscillator. The resulting frequency difference gives an indication of the NBTI/PBTI degradation of the devices in the “stressed” ring oscillator. To enhance the sensitivity of the ring oscillator based structures, various techniques based on “Beat Frequency” difference of two ring oscillators have been developed, where a phase
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difference between the two ring oscillators is introduced by tapping logic [12] or a phase shifter [13]. As the “Beat Frequency” depends on the signal edge alignment of the two ring oscillators, a small drift of the frequency (hence the signal phase) of the “stressed” ring oscillator results in a large change in the “Beat Frequency”, thus significantly enhancing the sensitivity. To separate the NBTI and PBTI effects, improved “Cut-and-Bias” ring oscillator circuit with the flexibility of isolated or combined NBTI and PBTI measurement has been developed [14].
While individual cell/device based characterization structures can offer detail characteristics of the individual subjects, it is preferable and essential to characterize the Static Noise Margin and NBTI/PBTI degradation in product array like environment so as to capture all the lithography and process related effects. To accurately characterize the unstressed and stressed SRAM devices, it is necessary to place the devices as densely packed as they are in the normal SRAM array. It is also important that the layout around the measured device is as close as possible to the layout of the original SRAM array to incorporate all the effects of the dense layout and the applied ground rule waivers not present in isolated single transistors [15]. This kind of scheme allows gathering of data of important cell device characteristics in a “real” “product-like” environment.
With modified SRAM column architecture which allows external access to individual bit-line and/or word-line, one can gather information on Read Static Noise Margin (RSNM) and Write Margin (WM) by measuring bit-line current under various voltage sweep [16, 17, 18]. This kind of scheme maintains the SRAM cell layout in “real” product, with changes only in the peripheral logic to allow external access to Word-Line (WL) and Bit-Line for voltage sweep and current measurement.
References
1. Ching-Te Chuang, Saibal Mukhopadhyay, Jae-Joon Kim, Keunwoo Kim, and Rahul Rao,
“High-Performance SRAM in Nanoscale CMOS: Design Challenges and Techniques,” Invited Plenary Paper, Proc. IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), Taipei, Taiwan, Dec. 3-5, 2007, pp. 4-11.
2. H. Pilo, “SRAM Design in the Nanoscale Era,” Digest of Tech. Papers, ISSCC, SE5, 2005, pp.
366-367.
3. E. Seevinck, et al., "STATIC-NOISE MARGIN ANALYSIS OF MOS SRAM CELLS," Ieee Journal
of Solid-State Circuits, vol. 22, pp. 748-754, Oct 1987.
4. S. Chakravarthi, et al., "A comprehensive framework for predictive modeling of negative bias
temperature instability," in Proc. IEEE International Reliability Physics Symposium, 2004, pp. 273-282.
5. K. Kang, et al., "Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array:
Modeling and Analysis," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, 2007, pp. 1770-1781.
6. S. Zafar, et al., "A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks
6 23-25.
7. J. C. Lin, et al., "Time Dependent VCCMIN Degradation of SRAM Fabricated with High-k Gate
Dielectrics," in Proc. IEEE International Reliability physics Symposium, 2007, pp. 439-444.
8. Aditya Bansal, Rahul Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, and Ching-Te Chuang “Impact
of NBTI and PBTI in SRAM Bit-cells: Relative Sensitivities and Guidelines for Application-Specific Target Stability/Performance,” Proc. IEEE International Reliability Physics Symposium, Montreal, 2009, pp. 745-749.
9. Aditya Bansal, Rahul Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang, “Impacts of
NBTI and PBTI on SRAM Static/Dynamic Noise Margins and Cell Failure Probability”, Journal of Microelectronics Reliability, Elsevier, vol. 49, issue 6, June 2009, pp. 642-649.
10. Azeez Bhavnagarwala, et. al., “Fluctuation Limits and Scaling Opportunities for CMOS SRAM
Cells,” Dig. Tech. Papers, IEDM 2005.
11. Azeez Bhavnagarwala, et. al.,, “A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with
Dynamic Cell Biasing,” Dig. Tech. Papers, Symp. VLSI Circuits, 2007, pp. 78-79.
12. M. B. Ketchen, et al., "Ring Oscillator Based Test Structure for NBTI Analysis," Proc. IEEE
International Conf. on Microelectronic Test Structures, 2007, pp. 42-47.
13. K. Tae-Hyoung, et al., "Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency
Degradation of Digital Circuits," IEEE J. Solid-State Circuits, vol. 43, 2008, pp. 874-880.
14. Jae-Joon Kim, Rahul Rao, Saibal Mukhopadhyay, and Ching-Te Chuang, “Ring Oscillator Circuit
Structures for Measurement of Isolated NBTI/PBTI Effects,” Proc. International Conference on Integrated Circuit Design and Technology, 2008, pp. 163-166.
15. Thomas Fischer, et al., “A 65 nm test structure for SRAM device variability and NBTI statistics,”
Solid State Electronics, vol. 53, 2009, pp. 773-778.
16. G. Zheng, et al., "Large-scale read/write margin measurement in 45 nm CMOS SRAM arrays," Digest
of Technical Papers, Symp. VLSI Circuits, 2008, pp. 42-43.
17. Thomas Fischer, et al., “Analysis of Read Current and Write Trip Voltage Variability from a 1-MB
SRAM Test Structure,” IEEE Trans. Semiconductor Manufacturing, Vol. 21, No. 4, Nov. 2008, pp. 534-541.
18. S. Drapatz, et al., "Fast stability analysis of large-scale SRAM arrays and the impact of NBTI
degradation," Proc. ESSCIRC, 2009, pp. 92-95. 研究目的。
In this 2 year project, jointly with Faraday Technology Corporation (智原科技), we intend to develop measurement and characterization structures for Static Noise Margin (SNM) and NBTI/PBTI for nanoscale CMOS SRAM, and apply the structures and techniques to the characterization of SRAM stability and NBTI degradation (for poly-gate technology).
研究方法。
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investigated. Individual cell based structure has been developed based UMC’s 55nm 6T SRAM cell. The array-level measurement techniques have been developed based on SRAM macros relevant to Faraday’s (智原科技) 55nm SRAM compilers.
The developed individual cell based structures and product array level techniques have been validated by extensive simulations. Test sites and Test SRAM macros with reasonable/meaningful size (determined based on discussion with Faraday) have been designed. Based on the obtained hardware, we will carry out measurement/characterization, and analyze the data to understand the characteristic of Static Noise Margin and NBTI/PBTI degradation on SRAM. We will also try to correlate the measured data with simulation results.
We also collaborated with our former colleagues at IBM T. J. Watson Research Center to engage High-κ Metal-Gate Group and SRAM and Technology-Circuit Co-Design members in VLSI Design Department, and Georgia Tech., to develop Ring Oscillator Monitoring Structures for isolated/combined NBTI and PBTI Measurement. The monitoring structures have been implemented, and measurement/characterization have been carried out in both SiO2/poly-gate technology and high-k metal-gate
technology.
We further collaborated with our former colleagues at IBM T. J. Watson Research Center and University of Utah, Salt Lake City, UT, U.S.A. to develop a Slew-Rate Monitoring circuit for on-chip process variation detection. The Slew-Rate Monitor has been fabricated and characterized in 65 nm IBM CMOS technology.
全程結果與討論。
1. Embedded SRAM Ring Oscillator for In-Situ Measurement of NBTI and PBTI Degradation in CMOS 6T SRAM Array
We have developed a novel embedded SRAM ring oscillator structure and measurement technique to characterize the BTI degradation of 6T SRAM cell transistors in a real SRAM cell array environment. The embedded ring oscillators are built using the 6T SRAM cell transistors directly in a real SRAM cell array environment, thus providing direct correlation between measured BTI degradation of cell transistors and the resulting impacts on SRAM stability. The viability of the embedded ring oscillator odometer and the impact of bias temperature instability have been implemented/demonstrated in UMC 55nm Standard Performance (SP) CMOS technology. Measurement and characterization have been carried out, and the results have been presented in a conference paper at 2012 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT):
Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kunti Lee, Shyh-Jye Jou, Ching-Te Chuang, and Wei Hwang, “Embedded SRAM Ring Oscillator for In-Situ Measurement of NBTI and PBTI Degradation in CMOS 6T SRAM Array,” Proc. 2012 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April
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23-25, 2012.
This paper is attached in the Appendix (附錄).
A patent application for this “Embedded 6T SRAM Ring Oscillator for NBTI/PBTI Measurement” is being applied by 世界專利商標事務所。
莊景德, 周世傑, 黃威, 蔡銘謙, 林宜緯, 楊皓義, 杜明賢, 石維強, 連南鈞, 李坤地,“用以量測負 偏壓溫度效應/正偏壓溫度效應之內嵌式 6T 靜態隨機存取記憶體環形振盪器＂ (Embedded 6T
SRAM Ring Oscillator for NBTI/PBTI Measurement)。11(專)A040, 中華民國及美國專利由世界專
利商標事務所申請中。(國立交通大學)。
2. An Array Based All-Digital On-Chip Circuit for 6T SRAM Stability Measurement
We have developed an array based test structure to measure the noise margin of standard 6T SRAM. In this work, the Read Static Noise Margin (RSNM) is characterized by separating the Read Disturb Voltage (Vread) and Inverter Trip Voltage (Vtrip). The 6T SRAM cell is modified to allow direct read-out of the
Read Disturb Voltage and Inverter Trip Voltage from the SRAM Array. We modify only the metal layers over the cell while keeping the diffusion, poly and contact layers intact, so as to maintain the thin cell layout with horizontal uni-directional poly, and pattern density/symmetry. Acquired voltage data are measured by all digital measurement circuit scheme composed of VCO and counter with resolution of 0.167mV/bit. Write Margin (WM) is measured by stepping down the BL voltage until the Write operation fails. The scheme has been implemented in a 512Kb SRAM array in UMC 55nm Standard Performance (SP) technology, and the results have been presented in a conference paper at 2012 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT):
Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee and Wei-Chiang Shih, “An All-Digital Read Stability and Write Margin Characterization Scheme for CMOS 6T SRAM Array,” Proc. 2012 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 23-25, 2012.
This paper is attached in the Appendix (附錄).
A patent application for this “Array Based All-Digital On-Chip Vtrip, Vread, and WM Measurement Circuit
for 6T SRAM” is being applied by 世界專利商標事務所。
莊景德, 周世傑, 黃威, 林宜緯, 蔡銘謙, 楊皓義, 杜明賢, 石維強, 連南鈞, 李坤地,“6T 靜態隨機 存取記憶體陣列之量測轉態電壓、讀取干擾與寫入邊界的方法與架構” (Methods and Apparatus for
Measuring Vtrip, Vread, and WM of 6T SRAM Array)。中華民國及美國專利由世界專利商標事務所
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3. An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM Array
We have developed an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (VTH) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in
SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the VTH measurement scheme is about 2-7mV at TT corner
across temperature range from 85oC to -45oC, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit. Measured VTH distributions agree well with Monte Carlo
simulation results. The results have been presented in a conference paper at 2012 IEEE International Symposium on Circuits and Systems (ISCAS).
Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang , Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, and Jyun-Kai Chu, “An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM Array,” Proc. 2012 IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, Korea, May 20-23, 2012, pp. 2485-2488.
This paper is attached in the Appendix (附錄).
A patent application for this “Array Based All-Digital Threshold Voltage Measurement Scheme for 6T SRAM” is being applied by 世界專利商標事務所。
莊景德、周世傑、林耕慶、王紹丞、林宜緯、蔡銘謙、石維強、連南鈞、李坤地、朱俊愷, “臨 界電壓量測裝置(Threshold Voltage Measurement Device)＂ Y/R:11(專)A167US, 中華民國及美國 專利由世界專利商標事務所申請中。(國立交通大學)。
4. Reliability Monitoring Ring Oscillator Structures for Isolated/Combined NBTI and PBTI Measurement in High-K Metal Gate Technologies
Together with our former colleagues in the High-κ Metal-Gate Group and SRAM and Technology-Circuit Co-Design members in VLSI Design Department at IBM T. J. Watson Research Center, and Georgia Tech., we have developed Ring Oscillator Monitoring Structures for isolated/combined NBTI and PBTI Measurement. The monitoring structures have been implemented in high-k metal-gate technology. The measurement results clearly show significant RO frequency degradation from PBTI as well as NBTI. For comparison, RO structures with the same principle are also implemented in a SiO2/poly-gate technology, where PBTI is negligible. Experimental results show
noticeable frequency degradation under NBTI-only stress mode but negligible degradation under PBTI-only mode, which illustrates the validity of the proposed principle and structures. The results have
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been presented in a conference paper at 2011 IEEE International Reliability Physics Symposium (IRPS):
Jae-Joon Kim, Barry P. Linder, Rahul M. Rao, Tae-Hyoung Kim, Pong-Fei Lu, Keith A Jenkins, Chris H. Kim, Aditya Bansal, Saibal Mukhopadhyay, and Ching-Te Chuang, “Reliability Monitoring Ring Oscillator Structures for Isolated/Combined NBTI and PBTI Measurement in High-K Metal Gate Technologies,” Proc. 2011 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, April 10-14, 2011, pp. 47-50.
(a) (b)
Fig. 1. (a) Proposed ring oscillator structure. (b) Die micrograph and layout for BTI monitors for a high-k/metal gate technology. (170 x 22 μm2 for 4 RO experiments).
(a) (b)
Fig. 2. (a) RO frequency degradation vs. stress time. NBTI results from RO1 and RO3 differ because WPDUT/ WPB= 1:1 in RO1 and WPDUT/ WPB= 1:9 in RO3. (b) RO4 frequency degradation comparison
between simultaneous N/PBTI stress case and sum of individual NBTI and PBTI stress cases.
5. Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection
11
Lake City, UT, U.S.A., we have developed a Slew-Rate Monitoring circuit for on-chip process variation detection. The difference of rise and fall slew is presented as another process-variation metric along with the delay in determining the relative mismatch between the drive strengths of nMOS and pMOS devices. The importance of considering both of these metrics is illustrated, and a new slew rate monitoring circuit is presented for measuring the difference of rise and fall slew of a signal on the critical path of a circuit. Sensitivity analysis with multiple pulses as input has also been investigated. Bias generator circuits that track nMOS and pMOS threshold voltages have been incorporated, which makes the design less susceptible to process variation. Design considerations, simulation results, and characteristics of the slew-rate monitor circuitry in a 65-nm IBM CMOS process are presented, and a sensitivity of 50 MHz/50 ps for single pulse input is achieved. The measurement sensitivity of a fabricated slew-rate monitor in a 65-nm IBM CMOS technology is 0.11 V/μs, with 1089 pF as the output load of the slew-rate monitor. The results are presented in a paper to appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
Amlan Ghosh, Rahul M. Rao, Jae-joon Kim, Ching-Te Chuang and Richard B. Brown, “Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), (accepted).
12
(a) (b) Fig. 4. Schematic block diagram of (a) comparator-A, and (b) integrator.
13
Fig. 6. Measured sensitivity of the slew-rate monitoring circuit.
全程計劃產出論文及專利表列。
(A) 4 Conferen Papers:
1. Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kunti Lee, Shyh-Jye Jou, Ching-Te Chuang, and Wei Hwang, “Embedded SRAM Ring Oscillator for In-Situ Measurement of NBTI and PBTI Degradation in CMOS 6T SRAM Array,” Proc. 2012 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 23-25, 2012.
2. Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee and Wei-Chiang Shih, “An All-Digital Read Stability and Write Margin Characterization Scheme for CMOS 6T SRAM Array,” Proc. 2012 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 23-25, 2012.
3. Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, and Jyun-Kai Chu, “An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM Array,” Proc. 2012 IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, Korea, May 20-23, 2012, pp. 2485-2488.
4. Jae-Joon Kim, Barry P. Linder, Rahul M. Rao, Tae-Hyoung Kim, Pong-Fei Lu, Keith A Jenkins, Chris H. Kim, Aditya Bansal, Saibal Mukhopadhyay, and Ching-Te Chuang, “Reliability Monitoring Ring Oscillator Structures for Isolated/Combined NBTI and PBTI Measurement in High-K Metal Gate Technologies,” Proc. 2011 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, April 10-14, 2011, pp. 47-50.
14
1. Amlan Ghosh, Rahul M. Rao, Jae-joon Kim, Ching-Te Chuang and Richard B. Brown, “Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), (accepted).
(C) 3 Patents:
1. 莊景德, 周世傑, 黃威, 蔡銘謙, 林宜緯, 楊皓義, 杜明賢, 石維強, 連南鈞, 李坤地,“用以量測 負偏壓溫度效應/正偏壓溫度效應之內嵌式 6T 靜態隨機存取記憶體環形振盪器＂ (Embedded 6T SRAM Ring Oscillator for NBTI/PBTI Measurement)。11(專)A040, 中華民國及美國專利由世界專 利商標事務所準備申請中。(國立交通大學)。
2. 莊景德, 周世傑, 黃威, 林宜緯, 蔡銘謙, 楊皓義, 杜明賢, 石維強, 連南鈞, 李坤地,“6T 靜態
隨機存取記憶體陣列之量測轉態電壓、讀取干擾與寫入邊界的方法與架構” (Methods and
Apparatus for Measuring Vtrip, Vread, and WM of 6T SRAM Array)。中華民國及美國專利由世界專利
商標事務所準備申請中。(國立交通大學)。
3. 莊景德、周世傑、林耕慶、王紹丞、林宜緯、蔡銘謙、石維強、連南鈞、李坤地、朱俊愷, “臨 界電壓量測裝置(Threshold Voltage Measurement Device)＂ Y/R:11(專)A167US, 中華民國及美國 專利由世界專利商標事務所準備申請中。(國立交通大學)。
附錄。
1. Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kunti Lee, Shyh-Jye Jou, Ching-Te Chuang, and Wei Hwang, “Embedded SRAM Ring Oscillator for In-Situ Measurement of NBTI and PBTI Degradation in CMOS 6T SRAM Array,” Proc. 2012 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 23-25, 2012.
2. Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee and Wei-Chiang Shih, “An All-Digital Read Stability and Write Margin Characterization Scheme for CMOS 6T SRAM Array,” Proc. 2012 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 23-25, 2012.
3. Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, and Jyun-Kai Chu, “An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM Array,” Proc. 2012 IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, Korea, May 20-23, 2012, pp. 2485-2488.
Embedded SRAM Ring Oscillator for In-Situ Measurement of
NBTI and PBTI Degradation in CMOS 6T SRAM Array
Ming-Chien Tsai1, Yi-Wei Lin1, Hao-I Yang1, Ming-Hsien Tu1,
Wei-Chiang Shih2, Nan-Chun Lien1,2, Kuen-Di Lee2, Shyh-Jye Jou1, Ching-Te Chuang1 and Wei Hwang1
1Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.
Email: [email protected]
2Faraday Technology Corporation,
Hsinchu, Taiwan, R.O.C.
Abstract—One of the major reliability concerns in nano-scale CMOS VLSI design is the time-dependent Bias Temperature Instability (BTI) degradation. Negative Bias Temperature Instability and Positive Bias Temperature Instability (NBTI and PBTI) weaken MOSFETs over usage/stress time. We present an embedded 6T SRAM ring oscillator structure which provides in-situ measurement/characterization capability of cell transistor degradation induced by bias temperature instability. The viability of the embedded ring oscillator odometer and the impact of bias temperature instability are demonstrated in 55nm standard performance CMOS technology.
I. INTRODUCTION
Lifetime reliability is one of the key design factors for robust VLSI systems. Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), and Time Dependent Dielectric Breakdown (TDDB) have become major concerns for performance and yield of nano-scale CMOS VLSI systems. These reliability degradations not only constrain the technology scaling, but also threaten the stability and functionality of digital circuits [1-4]. The degradation of device threshold voltage under the presence of electrical and thermal stress has long been a significant reliability issue in scaled CMOS technologies. Due to the importance of long-term degradation in nano-scale CMOS SRAM, there have been significant amount of efforts investigating the impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability [1, 2]. Kang et al. [2] explored the impact of NBTI degradation of several critical performance parameters of SRAM arrays. They showed that, under NBTI stress, the Static Noise Margin (SNM), READ stability, and parametric yield of SRAM array were severely degraded over time. On the other hand, Write-ability and leakage current might improve with time. Bansal et al. [3] carried out failure analysis using Monte-Carlo simulations and showed that, under worst-case static stress, NBTI and PBTI degraded the stability during READ (significantly) and WRITE (marginally) operations.
Ring Oscillator (RO) based structure for measuring NBTI degradation is the simplest method [5]. It has been shown that the relative degradation of NBTI stressed ring oscillator increases as the operating voltage decreases. Some on-chip reliability monitors for measuring degradation of digital circuits have been proposed [5-7].The circuits in [5] overcome the drawbacks of conventional ring oscillators which fail to isolate the NBTI and PBTI contribution when PBTI isn’t negligible anymore in deeply-scaled CMOS technology with
high-K/metal-gate [8, 9]. Kim et al. [6] developed a silicon
odometer with high sensing resolution by measuring the beat frequency of two ring oscillators. Furthermore, a monitoring structure [7], which can measure the frequency degradation induced by HCI, BTI, and TDDB separately, has been introduced for accurate real-time reliability monitoring. However, all of these monitoring structures were implemented in logic circuits with individual isolated logic devices to characterize the BTI effects on general digital logic devices/circuits, not for specific SRAM cell transistors in a real SRAM cell array environment.
In this work, we propose an embedded SRAM ring oscillator structure and measurement technique to characterize the BTI degradation of 6T SRAM cell transistors in a real SRAM cell array environment. The embedded ring oscillators are built using the 6T SRAM cell transistors directly in a real SRAM cell array environment, thus providing direct correlation between measured BTI degradation of cell transistors and the resulting impacts on SRAM stability. The details of the Embedded SRAM Ring Oscillator (ESRO) are presented in Section II. The analysis and measurement results are shown in Section III, and the conclusions of the paper are given in Section IV.
II. EMBEDDEDSRAMRINGOSCILLATOR
A. Embedded SRAM Ring Oscillator and BTI Stress
Fig. 1 shows a PMOS (NMOS) under NBTI (PBTI) stress, As mentioned above, the SRAM stability degradation induced by BTI significantly impacts the long-term reliability. As such, it is crucial to have a characterization structure that can provide direct measurement of cell transistor degradation due to aging effects. We modify the SRAM cell array to form an ESRO for BTI measurement. We combine the BTI stress capability and ring oscillator into ESRO structure. In 6T SRAM cell (Fig. 2), we are mainly concerned about the degradation of pull-up PMOS (NBTI) and pull-down NMOS (PBTI). The degradation of these two devices can affect the cell stability and performance significantly. For the access pass-gate transistor, the active period for a particular WL is typically relatively short during the whole SRAM operation.
Fig. 1. NBTI stress of PMOS and PBTI stress of NMOS.
Therefore, compared with pull-up PMOS and pull-down NMOS, the stress period of pass-gate transistor is much shorter, and the BTI induced threshold voltage degradation of pass-gate transistor is negligible.
Fig. 3 shows an inverter stage in a ring oscillator, If the input of inverter is ‘0’, the PMOS is under NBTI stress while the NMOS is not stressed. Meanwhile, the supply voltage can be raised to Vstr to enhance the stress efficiency. On the other hand, when the input is ‘1’, the NMOS is under PBTI stress, and higher Vstr at the input can speed up the NMOS degradation.
B. Embedded 6T SRAM Ring Oscillator Structure
The unit-stage of ESRO, as shown in Fig. 4(a), is composed of two parts/cells: blanked-cell (for control and stress) and active-cell (for forming an inverter). The major function of blanked-cell is to provide the stress voltage to the input of active-cell inverter for stressing PMOS or NMOS, and we use PMOS (P_SWITCH) in the blanked-cell as a
switch. During Stress NMOS mode, CTRLSTR is pull down to
‘0’ to turn on P_SWITCH for passing VB_STR to the input of
active-cell inverter. With a “High” at active-cell inverter input, the NMOS is under PBTI stress. Complementarily, we provide a ‘0’ signal at the input of active-cell inverter for NBTI stress of PMOS. Due to the poor ability of PMOS to
pass ‘0’, we pull down CTRLSTR to a negative voltage to
over-drive P_SWITCH to pass a stronger ‘0’ to the input of the active half-cell inverter. The supply voltage of the active-cell can be pulled up to a higher voltage to enhance NBTI stress of PMOS.
The Device Under Test (DUT) is the pull-up PMOS (PU_INV) and the pull-down NMOS (PD_INV) in the active-cell. The pass-gate in the active-cell controls the connection of the ring oscillator. During Stress mode, the unit-stage inverter is isolated from the previous and succeeding inverters by the pass-gates in the active-cells (The Word-Line (WL) is “0” to turn off the pass-gate transistors). The other devices in the cell are blanked out to break the feedback loop so as not to affect the normal ring oscillator operation. The blanked-cells and
active-cells use two independent power supply lines, VB_STR
and VA_STR. Both of them can be set up at different levels
under different operation modes. The overall input conditions for Stress Mode and Measurement Mode are shown in Table 1. For a 6T SRAM, thin cell layout with horizontal uni-directional poly, and pattern density/symmetry are crucial for manufacturability, especially for the poly, diffusion and contact layers. To blank out unused cell devices, we keep the
diffusion, poly and contact layers intact, and only modify the metal layers to build the ESRO structure (Fig. 5). As shown in Fig. 4(b), two parallel ESROs share the internal connection nodes, and the activation of individual ESRO is decided by the enabling of WL0 or WL1. We then construct an ESRO with one hundred stages of blanked-cells and active-cells (and an Enabling NAND gate) as shown in Fig. 6. The input of the first stage is CN0 node, and the ring is folded every 25-stage. The switch of ring oscillator is placed at the peripheral area
Table 1. Input Conditions for Embedded SRAM Ring Oscillator
Signal Stress Mode Meas. Mode NBTI PBTI VA_STR Vstr Vstr Vnom VB_STR GND Vstr Vnom CTRLSTR Vstr_n GND Vnom WL GND GND VDDH Note: (1) Vstr Њ VDD, and Vstr_n Ω0.5V. (2) Vnom = VDD (3) VDDH = 1.2 VDD (a) (b)
Fig. 4. (a) The basic unit of proposed SRAM ring oscillator, and (b) schematic of two parallel unit-stage cells.
Fig. 3. One stage inverter under stress of NBTI and PBTI.
Fig. 2. A 6T cell suffers asymmetrical degradation from NBTI and PBTI.
near the ring oscillator array. The dummy cells (CNn (n=0, 25, 50, 75)) used in 100-stage ring array are for passing signals and to preserve the SRAM cell array layout characteristics in each stage of ESRO. The delay time of entire ESRO is 34.5ns. Fig. 7 shows the simulated results of frequency degradation versus threshold voltage drift using modified cell device
models. Based on 55nm 1P9M 1.0V SiO2/poly-gate standard
performance CMOS process, the oscillation frequency of ESRO is 14.5 MHz and the area of the two parallel 100 stages
ESROs is 546.7 m2 (66.67m*8.2m), including the dummy
cells for preserving the layout characteristics of SRAM cell array.
C. Counter-Based Measurement Circuit
Since the threshold voltage of MOSFET is an analog signal, it is difficult to extract large amount of data for SRAMs in SOCs. Hence, in this work, we use a full digital scheme to convert the threshold voltage drift to frequency difference to facilitate data extraction, processing, and statistical analysis. A basic set of measurement unit (Fig. 8) consists of two ring oscillators and a frequency comparator [10]. The output of the
comparator, FFCOUT, is the “Beat Frequency” (frequency
difference between the stressed ring oscillator and the unstressed ring oscillator). The final stage of ESROs, the 101-stage enabling NAND gate, is placed in the frequency comparator block. A counter-based digital read-out scheme is used to convert the beat frequency to digital output. The detailed structure is shown in Fig. 9. With this scheme, we can extract the beat frequency quickly with high resolution.
As shown in Fig. 9, for NBTI in PMOS, the beat
frequency FFCOUT ranges roughly from 50 KHz to 760 KHz.
Due to wide frequency range of FFCOUT, the counter B (16-bit)
should have the ability to cover the lowest and the highest
frequency of FFCOUT so that it won’t overflow in the counting
period, which is decide by counter A (10-bit). The extracted digital data can be easily converted back to threshold voltage drift with a conversion table for statistical analysis.
One SRAM Ring Oscillator bank includes 8 sets of measurement unit. The core part of the measurement circuit (Fig. 9) comprises of 64 SRAM Ring Oscillator banks and some peripheral circuits, such as decoder, global MUX, and buffer. The system block diagram is shown in Fig. 10. The
Fig. 10. Block diagram of the whole system. Fig. 9. The counter-based digital read-out measurement scheme.
Fig. 8. One set of testing circuits
0 10 20 30 40 50 0.01 0.1 Fr equency Deagr adt ion ( nor m a li z e d) ΔVT (mV) NBTI(PMOS) PBTI(NMOS)
Fig. 7. Simulated frequency degradation vs. threshold voltage drift. Fig. 6. 100-stage ESRO chain composed of modified SRAM cells. Fig. 5. Modification of 6T cell layout to form ESRO unit-stage.
inputs are 9-bit address and control signals like clock signal (CLK), and enable signal (EN) for ring oscillator. The lowest three bits of address, address [2:0] are for selecting one of the 8-set ESROs and beat frequency circuit in one bank. The [8:3] bits of address are used to select one of the 64 banks. The
oscillating signals of FSTR, FUNSTR and FFCOUT are transmitted
to the digital read-out circuit. STR and UNSTR are also transmitted to the chip output for observation. The area of the overall system, excluding the digital read-out circuit is 1650 um 1050um. The area of the digital read-out circuit is 903
um2, representing an area overhead of 0.52%
III. MEASUREMENTRESULTS
A test-chip is implemented in a 55nm SiO2/poly-gate
standard performance bulk CMOS technology. The real-time frequency degradation of stressed ESRO can be observed by recording the counter output or directly observing the STR_OUT in Fig. 9. The external reference signal, F_REF_RO makes the digital read-out circuit more adaptive to wide range of beat frequency.
Fig. 11 shows the measured ESRO frequency degradation versus stress time for NBTI stress voltage of 1.2V, 1.1V and
1.0V. As expected, higher stress voltage, VA_STR, results in
larger frequency degradation. We find that the frequency
degradation starts to saturate after 104 seconds stress time.
Based on the frequency degradation vs. threshold voltage drift characteristics in Fig. 7, the threshold voltage drift of pull-up
PMOS is more than 50mV after 104 seconds of 1.0V stress.
Fig. 12 compares the measured results of NBTI stress and
PBTI stress. Since SiO2/poly-gate technology is employed, the
ESRO frequency is degraded after NBTI-only stress, while
there is negligible change in ESRO frequency after PBTI-only stress. Fig. 13 shows the die photo and layout view for this test chip.
IV. CONCLUSION
In this work, we present an Embedded SRAM Ring Oscillator (ESRO) structure for measuring the degradation of 6T SRAM cell transistors induced by NBTI/PBTI. The ESRO preserves the original layout characteristics of 6T SRAM cell array with stress capability. We also describe the digital read-out scheme, and the measured BTI frequency degradation in 55nm standard performance CMOS technology.
ACKNOWLEDGMENT
This work was supported by Ministry of Economic Affairs in Taiwan under Contract 98-EC-17-A-01-S1-124, and National Science Council (NCS), Taiwan, under Contract NSC 99-2221-E-009 -183-MY2.
REFERENCES
[1] J. H. Stathis and S. Zafar, "The negative bias temperature instability in MOS devices: A review," Microelectronics and Reliability, vol. 46, pp. 270-286, 2006.
[2] K. Kang, H. Kufluoglu, K. Roy, and M. A. Alam, "Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, pp. 1770-1781, 2007.
[3] A. Bansal, R. Rao, J. J. Kim, S. Zafar, J. H. Stathis, C. T. Chuang, "Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability," Microelectronics Reliability, vol. 49, pp. 642-649, Jun 2009.
[4] V. Reddy, A. T. Krishnan, A. Marshell, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishnan, "Impact of negative bias temperature instability on digital circuit reliability," Reliability Physics Symposium Proceedings, pp. 248-254, 2002.
[5] K. Jae-Joon, R. Rao, S. Mukhopadhyay, and C. T. Chuang, "Ring oscillator circuit structures for measurement of isolated NBTI/PBTI effects," IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, pp. 163-166, 2008.
[6] T. H. Kim, R. Persaud, and C. H. Kim, "Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits," IEEE Journal of Solid-State Circuits, vol. 43, pp. 874-880, 2008.
[7] J. Keane, X. Wang, D. Persaud, and C. H. Kim, "An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB," IEEE Journal of Solid-State Circuits, vol. 45, pp. 817-829, 2010.
[8] S. Zafar, Y. H. Kim, V. Narayana, C. Cabral Jr., V. Paruchuri, B. Doris, J. Sathis, A. Callegari, and M. Chudzik, "A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates," Symposium on VLSI Technology, pp. 23-25, 2006. [9] R. Degraeve, M. Aoulaiche, B. Kaczer, P. Roussel, T. Kauerauf, S.
Sahhaf, and G. Groeseneken,, "Review of reliability issues in high-k/metal gate stacks," International Symposium on the Physical and Failure Analysis of Integrated Circuits, pp. 1-6, 2008.
[10] M. B. Ketchen, M. Bhushan, and R. Bolam, "Ring Oscillator Based Test Structure for NBTI Analysis," in IEEE International Conference on Microelectronic Test Structures, pp. 42-47, 2007
Fig. 13. Die photo (left) and layout view (right) of the test chip.
104 0.00 0.02 0.04 0.06 0.08 0.10 0.12 Freque ncy D eagrada ti o n (no rm a li zed ) Stress Time (s) NBTI PBTI
Fig. 12 Measured ESRO frequency degradation under NBTI-only and PBTI-only stress in SiO2/poly-gate technology.
103 104 0.1 1 Freuen cy Degradation (normalized) Stress Time (s) VA_STR=1.2V VA_STR=1.1V VA_STR=1.0V
Fig. 11. Measured ESRO frequency degradation versus stress time for different NBTI stress voltage.
1
Abstract—We present an all-digital Read Stability and Write Margin (WM) characterization scheme for CMOS 6T SRAM array. The scheme measures the cell Read Disturb voltage (Vread)
and cell Inverter Trip voltage (Vtrip) in SRAM cell array
environment. Measured voltages are converted to frequency with Voltage Controlled Oscillator (VCO) and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. Resistor based voltage divider with 64 voltage levels and 10mV per step is employed to allow sweeping of BL voltage from 640mV to GND for WM characterization. A 512Kb test macro is implemented in UMC 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations validate the accuracy of Vread and Vtrip measurement scheme, and post-layout
simulations show the resolution of the digital read-out scheme is 0.167mV/bit.
I. INTRODUCTION
The cell stability, Static Noise Margin (SNM) [1], and VMIN
of CMOS 6T SRAM are limited by leakage, variation, and supply voltage in the physical domain [2-7], and conflicting Read/Write requirements and cell disturb in the design domain. With technology scaling, the variations in cell Read-Disturb
voltage (Vread) (Fig. 1) and cell Inverter Trip voltage (Vtrip)
increase, causing overlap and Read failure [8]. Various measurement techniques have been developed to characterize SRAM bit cell transistors, Read Stability and Write Margin (WM) [9]. While individual cell/device based characterization structures [10] can offer detail characteristics of the individual subjects, it is preferable and essential to characterize the Read Stability and WM in product array like environment so as to capture all the lithography and process related effects [11-14]. It is also important that the layout surrounding measured devices is as close as possible to the layout of the original SRAM array to incorporate the effects of dense layout and the applied ground rule waivers not present in isolated single transistor or cell.
In this work, we present an all-digital Read Stability and Write Margin (WM) characterization scheme for CMOS 6T SRAM array. The scheme measures the cell Read Disturb
voltage (Vread) and cell Inverter Trip voltage (Vtrip) in SRAM
cell array environment. Measured voltages are converted to frequency with Voltage Controlled Oscillator (VCO) and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. Resistor based voltage divider with 64 voltage levels is employed to allow sweeping of BL voltage for WM characterization. Section II describes the modified cell structure, measurement scheme and Monte Carlo simulation results to validate the measurement scheme. Section III presents the test macro architecture and digital read-out
scheme. Section IV discusses the 512Kb test macro implementation in UMC 55nm CMOS technology. The conclusions of the paper are given in Section V.
Fig. 1. Standard 6T SRAM cell in Read mode.
II.MEASUREMENT SCHEMES FOR VREAD,VTRIP AND WM
A. Modified Cells for Vread and Vtrip
Fig. 2 and Fig. 3 depict the schematic, modification of the
cell layout and the equivalent circuit for Vread and Vtrip
measurement, respectively. For 6T SRAM, thin cell layout with horizontal uni-directional poly, and pattern density/symmetry are crucial for manufacturability and yield, especially for poly, diffusion and contact layers. To blank out unused cell devices and alter connections while preserving the layout and surroundings of critical layers, we keep the diffusion, poly and contact layers intact, and only modify Via and metal layers as shown in Fig. 2(b) and 3(b).
To measure Vread, the left cell inverter is blanked out with its
supply and GND nodes left floating. The input of the right cell
inverter (gate of M1/M2) is connected to VDD to force the right
cell storage node Q to “Low”, corresponding to the condition
for Read operation. The column structure for Vread
measurement is shown in Fig. 4(a). In Vread measurement mode,
“Vread_enb” goes “Low”, and the Read conditioning PMOS
precharges and holds BL at VDD. The voltage at node Q,
resulting from the voltage divider effect from right access
transistor M3 and right pull-down NMOS M2, will be Vread, and
is passed through the left access transistor M6 to BLB for measurement.
For Vtrip measurement , the left cell inverter is blanked out
with its supply and GND nodes left floating. In Vtrip
measurement mode, “Vtrip_enb” (Fig. 4(b)) goes “Low”, The Trip
conditioning PMOS equalizes (i.e. shorts) the voltages of BL and BLB, which in term forces the input and output of the right
cell inverter (M1/M2 in Fig. 3) to equal potential at Vtrip.
An All-Digital Read Stability and Write Margin
Characterization Scheme for CMOS 6T SRAM Array
Yi-Wei Lin1, Ming-Chien Tsai1, Hao-I Yang1, Geng-Cing Lin1, Shao-Cheng Wang1, Ching-Te Chuang1,
Shyh-Jye Jou1, Wei Hwang1, Nan-Chun Lien1,2, Kuen-Di Lee2 and Wei-Chiang Shih2
1 Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R. O. C.
2
Faraday Technology Corporation, Hsinchu, Taiwan, R. O. C.
2
Fig. 5 compares the Monte Carlo simulation results (290000
samples) of Vread and Vtrip distributions of the proposed scheme
with that of a single isolated cell inverter. The distribution of the proposed scheme can be seen to track that from single
isolated cell inverter very well.
Fig. 5. Comparison of Monte Carlo simulation results for (a) Vread and
(b) Vtrip of proposed scheme with that of isolated cell inverter.
B. Write Margin (WM) measurement
Resistor based voltage divider with 64 voltage levels and 10mV per step is employed to allow sweeping of BL voltage from 640mV to GND for WM characterization. In WM measurement mode, background data of “1” (Q = 1) are written into the cell array. Then, “WEB (Write Enable BAR)” (Fig. 4(c)) goes “Low”, enabling gated inverter I1 to clamp BLB at
VDD. The output from the resistor based voltage divider is fed
into BL through an unity gain buffer to “Write” the selected cell to “0”. “WEB” then goes “High” to disable gated inverter I1, and the data in the selected cell is sensed (i.e. Read) by sensing inverter I2 from BLB to decide whether the Write operation has been successfully performed.
Fig. 2. (a) Vread cell schematic, (b) Vread cell layout and (c) Vread cell equivalent circuit.
Fig. 3. (a) Vtrip cell schematic, (b) Vtrip cell layout and (c) Vtrip cell equivalent circuit.
(a) (b) (c)
3
III.TEST CHIP ARCHITECTURE AND DIGITAL READ-OUT SCHEME
Fig. 6 shows the measurement array architecture. To reduce pin count for the control signals and input address, shift registers are employed for both row and column decoders. The
columns for Vread, Vtrip, and WM measurement are interleaved
with independent set of column shift registers. For WM measurement, it is necessary to stay at the same selected WL through Write (WM Measurement)-Read (Verify whether Write is successful)-Write (Write original data back into selected cells) sequence while sweeping through the BL voltage step. Two types of shift registers are employed: the column shift register (Fig. 7(a)) for normal sequential shift and the row shift register (Fig. 7(b)) with the added capability of holding the previous data (for staying at the same WL for WM measurement). To prevent the voltage level degradation through the column mux, full transmission gate with high gate control voltage of 1.2V is use. The rest of the design including supply for cell array operates at 1.0V.
Fig. 6. Measurement Array Architecture.
(a) (b)
Fig. 7. (a) Column shift register and (b) row shift register. The bit-line length is 128 cells. Each bank comprises 128
WL and 85 sets of interleaved Vread, Vtrip and WM columns (a
total of 3ͪ85 columns). So there are about 128ͪ85ͪ3~32K cells in a bank. With 16 banks, the total cell number is 16ͪ32K ~
512Kb. For each Vread, Vtrip or WM measurement, we can
obtain 128ͪ85ͪ16=174.08K samples.
(a)
(b)
Fig. 8. (a) VCO and counter based digital read-out scheme and (b) single stage (left) of 21 stage VCO (right) [15].
To facilitate extraction, processing, and statistical analysis of large amount of data, a VCO (Voltage Controlled Oscillator) and counter based digital read-out scheme (Fig. 8 and 9) similar to that in [15] is employed. The measured analog voltage is fed into an unity-gain buffer, converted into frequency by VCO, divided through a 10-bit Frequency Divider (FD) and read-out by the counter. Reference and calibration
paths are provided. Since the voltage levels of measured Vread
and Vtrip are low ( < 1/2 VDD), P-type VCO with PMOS delay
control device (Fig. 8(b)) is employed so the measured analog voltage (the control voltage at the gate of PMOS delay control device) is at where the VCO sensitivity is maximum. This provides a sensitivity of about 480MHz/V (Fig. 10) for the VCO. The resolution of the counter depends on number of bits and the period of counting. The 13-bit counter in the Reference path is used to set the counting period of the 14-bit counter in the measurement path which does the actual counting. This
provides a resolution of about0.167mV/bit.
4
Fig. 10. Sensitivity of P-type VCO in Fig. 8(b).
IV.TEST MACRO IMPLEMENTATION
The 512Kb test macro is implemented in UMC 55nm 1P10M Standard Performance (SP) CMOS technology. This array based measurement macro is located at the upper right corner of the test chip (Fig. 11(a)). The layout view of the test macro is shown in Fig. 11(b)). The test array has two power domains: 1.2V for the full transmission gate column mux, and 1.0V for the cell array and other peripheral circuits. The total
number of OP-Amp is 7 (2 for Vread measurement, 2 for Vtrip
measurement, 1 for resistor based voltage divider output for WM measurement, and 2 for calibration) . All OP-Amps are located at the middle strip of the macro with a 3.3V supply. Four VCO’s and resistor voltage divider are located at the right side of the macro with their own supply. The overall macro area is 2644Ӵmx1290Ӵm (excluding FD and counter) with 27 pins. The characteristics of the test macro are summarized in Table-I.
(a) (b)
Fig. 11. (a) Array based measurement macro (upper right) in test chip and (b) layout view of array based measurement macro.
V.CONCLUSIONS
We presented an all-digital Read Stability and Write Margin (WM) characterization scheme for CMOS 6T SRAM array.
The scheme measured the cell Read Disturb voltage (Vread) and
cell Inverter Trip voltage (Vtrip) in SRAM cell array
environment. Measured voltages were converted to frequency with Voltage Controlled Oscillator (VCO) and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test macro was implemented in UMC 55nm CMOS technology. Post-layout simulations showed the resolution of the digital read-out scheme is 0.167mV/bit.
Table-I : 512Kb Test Macro Characteristics
ACKNOWLEDGMENT
This work was supported by National Science Council, Taiwan, under Contract NSC 99-2221-E-009-183-MY2, Ministry of Economic Affairs in Taiwan under Contract 99-EC-17-A-01-S1-124, and Ministry of Education in Taiwan under ATU Program.
REFERENCES
[1] E. Seevinck, et al., "Static-noise margin analysis of MOS SRAM cells", IEEE J. Solid-State Circuits, vol. SC-22, no. 2, 1987, pp. 748 – 754.
[2] S. R. Nassif, “Modeling and analysis of manufacturing variations,”in Proc. Custom Integrated Circuit Conf., 2001,pp. 223–228.
[3] S. Borkar, et al., “Parameter variation and impact on circuits and microarchitecture,” in Proc. Design Automation Conf., 2003, pp. 338–342.
[4] A. Bhavnagarwala, et al., “The impact of intrinsic device fluctuations on CMOS SRAM cell stability,” IEEE J. Solid-State Circuits, vol. 36, no. 4, Apr. 2001, pp. 658–665.
[5] X. Tang, et al., “Intrinsic MOSFET parameter fluctuations due to random dopant placement,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 5, no. 4, Dec. 1997, pp. 369–376.
[6] S. Mukhopadhyay, et al., “Modeling and estimation of failure probability due to parameter variation in nano-scale SRAMs for yield enhancement,” in Dig. Tech. Papers, Symp. VLSI Circuits, 2004, pp. 64–67.
[7] S. Mukhopadhyay, “Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Dec. 2005, vol. 24, no. 12, pp. 1859-1880.
[8] H. Pilo, “SRAM Design in the Nanoscale Era,” Digest of Tech. Papers, ISSCC, SE5, 2005, pp. 366-367.
[9] K. Takeda, et al., “Redefinition of write-margin for next generation SRAM and write-margin monitoring circuit. Dig. Tech. Papers, International Solid-State-Circuit Conference,2006, pp. 2602-2603. [10] A. Bhavnagarwala, et. al., “Fluctuation Limits and Scaling
Opportunities for CMOS SRAM Cells,” Dig. Tech. Papers, IEDM, 2005, pp. 659-662.
[11] X. Deng, et al., “Characterization of Bit Transistors in a Functional SRAM,” Dig. Tech. Papers, Symp. VLSI Circuits, 2008, pp. 44-45. [12] T. Fischer, et al., “A 65nm Test Structure for SRAM Device Variability
and NBTI Statistics,” Solid State Electronics, vol. 53, 2009, pp. 773-778.
[13] G. Zheng, et al., "Large-scale Read/Write Margin Measurement in 45nm CMOS SRAM Arrays," Digest of Technical Papers, Symp. VLSI Circuits, 2008, pp. 42-43.
[14] T. Fischer, et al.,” Analysis of Read Current and Write Trip Voltage Variability from a 1-MB SRAM Test Structure,” IEEE Trans. on Semiconductor Manufacturing, Vol. 21, Issue 4, 2008, pp. 534 - 541. [15] R. Rao, et al., “A Completely Digital On-Chip Circuit for
Local-Random-Variability Measurement,” Dig. Tech. Papers, ISSCC, 2008, pp. 412 – 623.
An All-Digital Bit Transistor Characterization
Scheme for CMOS 6T SRAM Array
Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Nan-Chun Lien, Wei-Chiang Shih, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou Kuen-Di Lee, Jyun-Kai Chu
Department of Electronics Engineering Faraday Technology Corporation National Chiao Tung University, Hsinchu, Taiwan, R.O.C. Hsinchu, Taiwan, R.O.C.
Abstract—We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop
to measure the individual threshold voltage (VTH) of 6T SRAM
bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology.
Monte Carlo simulations indicate that the accuracy of the VTH
measurement scheme is about 2-7mV at TT corner across
temperature range from 85oC to -45oC, and post-layout
simulations show the resolution of the digital read-out scheme is
< 0.2mV per bit. Measured VTH distributions agree well with
Monte Carlo simulation results.
I. INTRODUCTION
With technology scaling down to deep sub-100 nm regime, leakage, variation and long-term degradation have surfaced to constrain the stability, scalability and attainable performance of CMOS SRAM [1]. The rapid increase in local random VTH
variation, against the backdrop of lower supply voltage and increasing memory capacity in state-of-the-art processors and SoC, has become the major challenge in the design of 6T SRAMs. Various measurement techniques have been developed to characterize the VTH fluctuation of logic devices
[2-5] and SRAM bit cell transistors [6-8]. While isolated device/cell based characterization structures can offer detail characteristics of the individual subject, it is preferable and essential to characterize the VTH variation in product array like
environment to capture the lithography and process related effects. It is important to maintain the dense layout and surroundings of the measured devices as close as possible to the original SRAM array to incorporate the layout dependent effects and applied ground rule waivers not present in insolated single transistor. Various array based techniques for characterizing bit cell transistors and/or cell stability/degradation have been developed [7-12]. These array based techniques typically modify the SRAM cell layout to gain access to (or “expose”) the individual cell transistors for ID and VTH measurement in standard array topology without
changing the cell layout considerably [8], or modify the SRAM column architecture to allow external access to each and every bit-line for gathering information on ID and VTH [7],
Read Static Noise Margin (RSNM) and Write Margin (WM) by measuring bit-line current under various voltage sweeps [9, 10]. It is also highly desirable to have digital read-out scheme
to facilitate fast collection, extraction, processing, and statistical analysis of large amount of data [5, 12].
Fig. 1. Schematic of 6T SRAM cell.
In this work, we present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) (Fig. 1) in SRAM cell array environment. The measured voltage is converted to frequency with dual-VCO and counter-based digital read-out to facilitate data extraction, processing, and statistical analysis. Section II describes the modified cell structure and measurement scheme. Section III presents the Monte Carlo simulation results and cell layout modification. Section IV discusses the test chip organization and peripheral circuit design. The digital read-out scheme is described in Section V. Section VI presents the 512Kb test chip implementation and measurement results in 55nm CMOS. The conclusions of the paper are given in Section VII.
II.MEASUREMENT SCHEME AND MODIFIED CELL STRUCTURE
Fig. 2 depicts the basic Operational Amplifier (OP-Amp) based VTH measurement scheme in [2, 3], where the Device
Under Test (DUT) is an NMOS (Fig. 2(a)) and a PMOS (Fig. 2(b)). In this scheme, the source voltage of DUT (Vsource)
follows Vset, and together with Rload, determines the current
through DUT. The Vset and Rload are chosen such that the
current density through DUT is where the VTH is defined (and
to be measured). As such, the gate voltage of DUT, Vgate, is
one ｜VTH｜ above (below) Vsource for NMOS (PMOS), and
measurement of Vgate provides direct information of VTH
(Vgate = Vset ± ︱VTH︱). This scheme has been used to
characterize VTH variations of an addressable array of 65nm
PD/SOI logic transistors [2, 3].
