Improved low temperature characteristics of p-channel MOSFETs with Si1-xGex raised source and drain

Abstract—P-channel metal–oxide–semiconductor field-effect transistors with Si₁ Ge raised source and drain (RSD) have been fabricated and further studied for low temperature ap-plications. The Si₁ Ge RSD layer was selectively grown by ANELVA SRE-612 ultra-high vacuum chemical vapor deposition (UHVCVD) system. Compared to devices with conventional Si RSD, improved transconductance and specific contact resistance were obtained, and these improvements become even more dra-matic with reducing channel length. Well-behaved short channel characteristics with reduced drain-induced barrier lowering (DIBL) and off-state leakage current are demonstrated on devices with 100 nm Si1 Ge RSD, due to the resultant shallow junction and less implantation damage. Moreover, temperature measure-ments reveal that Si1 Ge RSD devices show more dramatic improvement in device performance at low temperature ( 50 C) operation, which can be ascribed to the higher temperature sensitivity of the Si₁ Ge sheet resistance.

Index Terms—Low temperature measurements, PMOSFET, se-lective epitaxial growth (SEG), short channel effect, strained-SiGe, ultra-high vacuum chemical vapor deposition.

I. INTRODUCTION

T

in situ doped or ion-implanted p /n Si Ge layer have been reported [1]–[4]. Previously, pure Si selective epitaxy has been proposed to fabricate elevated source/drain (also known as raised source/drain) metal oxide semiconductor field effect transistor (MOSFET) to simultaneously achieve shallow junction for better device operation, and a thick sacrificial layer

Manuscript received August 14, 2000; revised December 11, 2000. This work was supported in part by the National Science Council of Taiwan, R.O.C., under Contract NSC89-2215-E009-050.

H.-J. Huang was with the Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C. She is now with IBM Semiconductor Research and Development Center, Hopewell Junction, NY 12533 USA.

K.-M. Chen was with the Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University. He is now with the National Nano Device Laboratories, Hsinchu, Taiwan, R.O.C.

T.-Y. Huang and C.-Y. Chang are with the Department of Electronics Engi-neering and Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C. (e-mail: [email protected]).

T.-S. Chao is with the National Nano Device Laboratories and also with the Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.

G.-W. Huang and C.-H. Chien are with the National Nano Device Laborato-ries, Hsinchu, Taiwan, R.O.C.

Publisher Item Identifier S 0018-9383(01)05680-5.

for reliable silicided contact to the junction [5]–[9]. In these regards, Si Ge is better suited than pure Si. Si Ge can not only be selectively deposited onto the exposed source and drain (S/D) area, similar to pure Si, it also enjoys a lower deposition temperature, which is beneficial for device appli-cation. Besides, Si Ge can be selectively etched with high selectivity to Si and SiO [10]. More importantly, Si Ge has a lower Schottky barrier height with respect to p junction because of the reduced band gap, which results in a lower contact resistivity and higher current drive, when compared to pure Si [11]–[13]. Recently, we have successfully fabricated p-channel metal oxide semiconductor field effect transistor (PMOSFET) with Si Ge as the raised S/D layer, and its impacts on contact resistance and device performance have been studied [13]. In particular, we showed that by employing Si Ge RSD, a drive current (measured at V and V) of 246 A/ m, which represents a 17% improvement, compared to the counterpart with pure Si RSD, is achieved for an effective channel length of 0.24 m. Furthermore, the improvement is found to increase with reducing channel length. For example, the improvement is only 15% when m. However, the improvement can reach 29% when is reduced to 0.16 m. This demonstrates the importance of maintaining a low series resistance as device is scaled down, thus makes the device with Si Ge RSD even more attractive for future sub-0.1 m technologies.

In this work, we report, for the first time, the temperature dependence on the Si Ge RSD device performance. De-tailed electrical characteristics of PMOSFETs with and without various RSD structures were measured and compared at three different temperatures, i.e., room temperature, 50 C, and 100 C. In addition, the drain-induced barrier lowering (DIBL) characteristics of PMOSFETs with Si Ge RSD and the specific contact resistivity and sheet resistance variation as a function of temperature were also studied in detail.

II. EXPERIMENTS

The fabrication of P-channel MOS transistors with various raised source/drain structures started with a standard baseline process [13]. Briefly, following a 4 nm gate oxide growth and polysilicon gate formation, source/drain extension implant ( cm , 10 KeV) was performed. Then, a 800 C, 20 min furnace anneal and a 1050 C, 10 s rapid thermal anneal

Fig. 1. I 0 V and transconductance characteristics of a conventional Si RSD and a Si Ge RSD devices, both with gate oxide thickness of 4 nm.

(RTA) were performed for dopant activation. Afterwards, a 150 nm sidewall spacer was formed. Next, wafers were split to receive either SiGe or Si selective epitaxial growth (SEG) on the exposed S/D regions by an ANELVA SRE-612 cold-wall ultra-high vacuum chemical vapor deposition (UHVCVD) system [14]. The standby base pressure was kept at

torr. For growing B-doped strained Si Ge layers, Si H , GeH , and 1% B H diluted in H were introduced to achieve a growth rate of 41 Å/min for Si Ge and 43 Å/min for Si Ge at 550 C, respectively. The maximum operation time for maintaining selective epitaxial growth of Si Ge or Si Ge layer (i.e., epitaxy on Si region only, but not on field oxide region) at 550 C is above 90 min. Samples with epitaxial thickness of 50 nm and 100 nm were processed in order to study the effects of the epitaxial layer thickness on the device performance. For comparison, conventional Si MOS transistors (i.e., without any raised S/D layer) were also fabricated in the same run. To obtain higher degree of boron concentration in S/D region, a cm , 20 KeV BF implant was adopted, which is followed by a 900 C, 30 s RTA for activation. Afterwards, a 500 nm TEOS was deposited, and a Ti/TiN/Al–Si–Cu/TiN 4-layer metal was deposited and patterned to complete contact metallization. Electrical characterizations at various temperatures ranging from 50 C to 100 C were performed with a HP4156 system, which was equipped with a thermal controller connected to the Cascade semi-auto probe station. Sheet resistance was extracted using bridge resistor test structures, while the contact resistance was measured by Kelvin cross-bridge structures.

III. RESULTS ANDDISCUSSIONS

Fig. 1 compares the and transconductance char-acteristics of MOS transistors with Si Ge and Si RSD samples. Both devices have the same epitaxial RSD thickness of 100 nm and the same effective channel length of 0.24 m. By using Si Ge RSD, and values (measured at

V and V) of 127 mS/mm and

158.6 A/ m, which are 19.02% and 16.11% higher than those of the counterpart device with Si RSD device, are obtained. These improvements are believed to be due to the lowering of

Fig. 2. Transconductance as a function of Ge mole fraction for various device channel length. The specific contact resistivity as a function of Ge mole fraction is also plotted in this figure.

Fig. 3. Drain-induced barrier lowering DIBL(V 0 V ) for PMOS transistors with various RSD structures.

the Schottky barrier height (SBH) in metal/p Si Ge junc-tion, which leads to the reduction of sheet resistance and specific contact resistivity [6]. The energy band gap (Eg) of Si Ge is known to change from 1.12 to 0.66 eV with increasing Ge mole fraction [15]. For pseudomorphic p-Si Ge layer, the SBH is expected to be lower than that of metal/p Si by 0.07 eV [16], thus effectively reduces the specific contact resistivity .

As shown in Fig. 2, the transconductance and relative con-tact resistivity measured by transmission line method (TLM) are plotted as a function of Ge mole fraction for devices with various channel lengths. The thickness of the epitaxial RSD layer is 50 nm. It can be seen that the effects of on device performance become more dramatic when the devices are scaled down. For m, a 13% improvement in value could be ob-tained for PMOSFET with 50 nm Si Ge RSD, compared to the device with Si RSD.

With a thicker epitaxial RSD layer (e.g., 100 nm), shallower p S/D junction could be obtained, especially for Si Ge layer with higher Ge mole fraction [2], [17], [18]. Thus the sus-ceptibility to punch-through and short channel effect could be alleviated, which is advantageous especially for sub-0.1 m de-vices. Fig. 3 shows the drain-induced barrier lowering (DIBL) effects for PMOSFETs with various structures. is de-fined as the threshold voltage extracted at maximum transcon-ductance at the drain voltage of 0.1 V, while is the satura-tion threshold voltage extracted at drain voltage of 2.5 V. While the device with a thin 50 nm Si RSD displays essentially the same DIBL characteristics as the conventional Si PMOSFET

Fig. 4. Drain leakage currentI as a function of drain bias V in off-state

(V = 0 V) for conventional Si RSD and SiGe RSD devices.

Fig. 5. Subthreshold characteristics and transconductance of conventional Si PMOS transistor measured at various temperatures.

without any RSD, improvement in DIBL is observed for the de-vice with 100 nm Si Ge RSD because the junction depth of the 100 nm Si Ge RSD in the source and drain re-gion would be as shallow as the depth of the extension rere-gion ( 800 Å). In addition, the improvement in DIBL indeed in-creases with increasing Ge mole fraction. It is worthy to note that for device with a thick 100 nm Si Ge RSD, the implant damage could be alleviated, because the damage region is lo-cated away from the p –n S/D junction. Thus no high tempera-ture anneal ( 900 C) is necessary to anneal out defects caused by the implant damage, as is required in conventional Si PMOS-FETs. The remarkable leakage current reduction at low level is indeed confirmed in Fig. 4 for devices with Si Ge RSD, all devices with an effective channel length of 0.24 m. On the other hand, there is essentially no difference in the gate induced drain leakage current (GIDL) that is measured at high bias. This is because the interface quality between gate and drain region for all samples remains essentially the same.

The effects of Si Ge RSD on the low temperature oper-ation of the transistors were also studied. Figs. 5 and 6 showed the subthreshold and transconductance characteristics measured at three different temperatures (i.e., 223, 298, and 373 K) for a conventional p-channel device (i.e., without any RSD) and the device with 100 nm Si Ge RSD, respectively. Both the transconductance and the drain current increase with reducing

Fig. 6. Subthreshold characteristics and transconductance of Si Ge RSD PMOS transistor measured at various temperatures.

Fig. 7. Drain current versus drain voltage for conventional and Si Ge RSD PMOS transistors.

temperature due to increased carrier mobility. At 50 C, the transconductance value is 145 mS/mm and 169 mS/mm (mea-sured at V) for the conventional device and the de-vice with Si Ge RSD, respectively. Leakage current also achieves its lowest value at the lowest measurement temperature (i.e., 50 C), because of reduced scattering rate and increased carrier mean free path. Generally, all aspects of – charac-teristics approach their optimum conditions with reducing tem-perature. Threshold voltage decreases while temperature in-creases due to increased number of intrinsic carriers. Finally, the thermal behavior of the parasitic components in a transistor could also affect the output characteristics of the transistors. Standard versus characteristics for the conventional non-RSD device and the device with 100 nm Si Ge RSD are shown in Fig. 7 for two operation temperatures, i.e., 223 K ( 50 C) and 298 K (25 C). The channel width of the transis-tors is 100 m. In the figure, solid and dotted lines denote the conventional device and the device with Si Ge RSD op-erating at 50 C (coarse lines) and 25 C (thin lines), respec-tively. The improvements with reduced temperature are more dramatic for the device with Si Ge RSD, as compared with the conventional device. The drain current (measured at

V, V) are 286.5 A/ m and

254.8 A/ m for RSD Si Ge and the conventional de-vice at 50 C. In order to confirm this phenomenon further, the saturation transconductance versus effective channel length is plotted in Fig. 8. It reveals the superior room

tempera-Fig. 8. Saturated transconductanceg versus effective gate length measured at various temperatures for conventional and Si Ge RSD devices.

Fig. 9. Normalized g [050 C]=g [100 C] versus effective channel length for conventional and Si Ge RSD devices.

ture and low-temperature performance in value for the de-vice with Si Ge RSD. For an effective channel length of 0.17 m, the transconductance increases from 166 to 187 mS/mm as temperature changes from 25 C to 50 C for the device with Si Ge RSD, which represents a 12.5% im-provement in . In contrast, the value changes from 135 to 146 under the same condition for the conventional device, which represents only 7.8% improvement for low-temperature operation.

To calculate the degree of improvements in transconduc-tance, the normalized maximum linear value measured at 50 C with respect to the same parameter measured at 100 C is plotted as a function of the effective channel length in Fig. 9. The average ratio of enhancement is roughly 1.6 and 1.54 for the Si Ge RSD device and the conventional device, respectively. For device operation in saturation mode, normalized drive current C C (measured

at V and V) as a function of the

effective channel length is shown in Fig. 10. A remarkable improvement in the normalized drive current as temperature varied from 100 C to 50 C is again observed for devices with Si Ge RSD, as compared with the conventional de-vices. It is worthy to note here that the normalized drive current C C reduces with decreasing for all devices. This trend is different from that of the normalized maximum linear which remains essentially constant with

Fig. 10. NormalizedI [050 C]=I [100 C] versus effective channel length for conventional and Si Ge RSD, and Si Ge RSD devices.

reducing . This is because when the device is operating in linear region (e.g., V), carrier velocity is under low electric field condition, mobility which is independent of channel length plays an important role in maximum linear . As a result, a constant value in maximum linear versus that is dependent only on temperature is observed for all devices. However, when the device is operating in saturation mode (e.g., V, and V), a high electric field is generated along the channel and would become even higher as decreases. Several factors, including velocity saturation, reduced carrier mobility caused by carrier scattering, and extrinsic component at high current drive would dominate

and determine the C C behavior, thus

reduces the enhancement ratio as devices are scaled down. In order to study further the temperature variations in in-trinsic and exin-trinsic components of the transistors, sheet resis-tance and contact resistivity as a function of temperature were measured, and the results are shown in Figs. 11 and 12, respectively. Generally, sheet resistance in source and drain gion, extension layer, and channel resistance decreases with re-ducing temperature due to enhanced mobility. On the contrary, specific contact resistivity increases with reducing temperature because less number of carriers would be able to overcome the metal/semiconductor energy barrier (SBH) by thermionic emis-sion. This is especially true for the conventional device with higher energy barrier. The superior low-temperature behavior of the Si Ge RSD device can be elucidated by the basic MOSFET model [19]. A MOSFET can always be broken down into an intrinsic MOS device and extrinsic source and drain re-sistive components. The entire extrinsic transconductance is

(1)

where is the transconductance of the intrinsic device, denotes the parasitic resistance including sheet re-sistance, contact rere-sistance, and extension resistanc, etc. The measured contact resistance values for a m contact are 45.82, 3.17, and 1.94 , while the sheet resistance values at 298 K are 132.5, 84.6, and 96.48 for conventional, Si Ge RSD, Si Ge RSD, respectively. Since the contact resistance is relatively small, the entire is

Fig. 11. Sheet resistance as a function of temperature for various structures.

Fig. 12. Specific contact resistivity as a function of reciprocal temperature

(1=T ) for metal with different contact layer structures.

mainly determined by the sheet resistance and extension resistance. So the temperature dependence of the device’s electrical performance would basically follow the temperature behavior of the sheet resistance. However, the temperature de-pendence of the sheet resistance is more sensitive for Si Ge RSD device than that of the conventional device. For example,

changes from 132.47 to 118.86 as temperature changes from 298 K to 223 K, which represents a 10.27% reduction, for the conventional device. In comparison, a 10.98% and 11.21% reduction ratio could be obtained for devices with Si Ge RSD and Si Ge RSD, respectively. The more sensitive temperature behavior of Si Ge RSD devices can thus explain their dramatic improvement in device performance at low temperature.

IV. CONCLUSION

In this paper, the drain-induced barrier lowering effects and low-temperature characteristics of p-channel transistors with Si Ge raised source and drain (RSD) were studied. We found that Si Ge RSD devices show better device performance including better drive current, transconductance, and reduced short-channel effects, compared to pure Si RSD devices. The improvements, which become more dramatic with reducing channel length, are believed to be mainly due to the lowering of the Schottky barrier height in metal/p Si Ge junction, which leads to the reduction of sheet resistance and specific contact resistivity. Moreover, Si Ge RSD devices are also found to depict a larger improvement rate under low

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Kun-Ming Chen (M’00) was born in Miaoli,

Taiwan, R.O.C., in 1971. He received the M.S. de-gree and the Ph.D. dede-gree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1996 and 2000, respectively.

He joined the National Nano Device Labora-tories, Hsinchu, Taiwan, in 2000, as an Associate Researcher. He was engaged in research on the SiGe and microwave device process and characterization.

Tiao-Yuan Huang (F’95) was born in Kaohsiung,

Taiwan, R.O.C., on May 5, 1949. He received the B.S.E.E. and M.S.E.E. degrees from National Cheng Kung University, Taiwan, in 1971 and 1973, respec-tively, and the Ph.D. degree in electrical engineering from the University of New Mexico, Albuquerque, in 1981.

After serving two years in the Taiwanese Navy, he joined the Chung Shan Institute of Science and Tech-nology, Lungtan, working on missile development. He left for the U.S. in 1977. After a two-year stint with Semiconductor Process and Design Center, Texas Instruments, he moved on to Silicon Valley and had since worked with several companies, including Xerox Palo Alto Research Center, Integrated Device Technology, Inc., and VLSI Technology, Inc. He had worked in various VLSI areas including memories (DRAM, SRAM, and nonvolatile memories), CMOS process/device technolo-gies and device modeling/simulation, ASIC technolotechnolo-gies, and thin film tran-sistors for LCD display. In 1995, he returned to Taiwan to become an Out-standing Scholar Chair Professor with National Chiao-Tung University and Vice President with National Nano Device Laboratories, National Science Council, Taiwan. He has published over 150 technical papers in international journals and conferences, and holds over 40 patents.

Dr. Huang received the 1988 Semiconductor International R&D Technology Achievement Award for his invention of the fully overlapped LDD transistors. He served on the technical committee of the IEEE International Electron De-vices Meeting (IEDM) in 1991 and 1992. He also served on the program com-mittee of the International Conference on Solid States Devices and Materials (SSDM) from 1996 to 1998.

Tien-Sheng Chao (M’96) was born in Penghu,

Taiwan, R.O.C., in 1963. He received the Ph.D. degree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1992.

He joined the National Nano Device Laboratories (NDL) as an Associate Researcher in July 1992, and became a Researcher in 1996. He was engaged in developing the thin dielectrics preparations, cleaning processes, and CMOS devices fabrication.

Chao-Hsin Chien is with the National Nano Device Laboratories, Hsinchu,

Taiwan, R.O.C.

Chun-Yen Chang (F’88) was born in Feng-Shan,

Taiwan, R.O.C. He received the B.S. degree in electrical engineering from Cheng Kung University, Taiwan, in 1960, and the M.S. degree in tunneling in semiconductor–supercondutor junctions and the Ph.D. degree in carrier transport across metal-semi-conductor barrier, both from National Chiao-Tung University (NCTU) Hsinchu, Taiwan, in 1969.

He has devoted himself to education and aca-demic research for more than 40 years. He has contributed profoundly to the areas of micro-electronics and optomicro-electronics, including the invention of the method of low-pressure-MOCVD-using tri-ethyl–gallium to fabricate LED, laser, and microwave transistors, Zn-incorporation of SiO for stabilization of power devices, and nitridation of SiO for ULSIs, etc. From 1962 to 1963, he fulfilled his military service by establishing at NCTU Taiwan’s first experiment TV transmitter that formed the founding structure of today’s CTS. In 1963, he joined NCTU to serve as an instructor establishing a high vacuum laboratory. In 1964, he and his colleague established the semiconductor research center (SRC) at NCTU with a very up-to-date, albeit homemade, facility for silicon device processing, where they made the nation’s first Si Planar transistor in April 1965, and subsequently the first IC in August 1966. In 1968, he published Taiwan’s first-ever semiconductor paper in the international journal

Solid State Electronics. In 1969, he became a Full Professor, teaching solid

state physics, quantum mechanics, semiconductor devices and technologies. From 1977 through 1987, he single-handedly established a strong electrical engineering and computer science program at NCKU where GaAs, -Si, poly-Si researches were established in Taiwan for the first time. Since 1987 he served consecutively as Dean of Research (1987–1990), Dean of Engineering (1990–1994), and Dean of Electrical Engineering and Computer Science (1994–1995). Simultaneously he was serving as the founding president of National Nano Device Laboratories (NDL) from 1990 through 1997. In 1997, he became Director of the Microelectronics and Information System Research Center (MIRC), NCTU (1997–1998). Many of his former students have since become founders of the most influential Hi-Tech enterprises in Taiwan, namely UMC, TSMC, Winbond, MOSEL, Acer, Leo, etc. In August 1, 1998, he was appointed as the President of NCTU. As the National-Chair-Professor and President of NCTU, his vision is to lead the university for excellence in engineering, humanity, art, science, management and bio-technology. To strive forward to world class multidisciplinary university is the main goal to which he and his colleagues have committed.

Dr. Chang received the IEEE third millennium medal in 2000. He is a member of Academia Sinica and a Foreign Associate of the National Academy of Engi-neering.