Dual Modulation Technique for High Efficiency in High-Switching Buck Converters Over a Wide Load Range

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Dual Modulation Technique for High Efficiency

in High-Switching Buck Converters Over a

Wide Load Range

Jen-Chieh Tsai, Tsung-Ying Huang, Wang-Wei Lai, and Ke-Horng Chen, Senior Member, IEEE

Abstract—A dual modulation technique to improve power

con-version efficiency with minimal increase in output voltage ripple is presented. The worsening switching noise caused by parasitic re-sistance and inductance due to high-switching operation can also be alleviated by the proposed ac ripple detector. Furthermore, the dual modulation method can speed up the load transient response since the switching frequency can increase to 5 MHz during the transient period. At very light loads, the switching frequency is al-ways kept higher than the acoustic frequency to avoid noisy sound. Experiment results show that the converter operates at 5 MHz using a small inductor of 1 H. The load transient response time is shorter than 3 s when load current changes from 150 to 450 mA or vice versa. Power efficiency is kept higher than 85% over a wide load current range. Specifically, light efficiency can be raised to about 45% above that of the conventional design.

Index Terms— DC-DC buck converter, dual modulation

tech-nique, hopping frequency modulator (HFM), loading potential de-tector (LPD) .

I. INTRODUCTION

R

ECENTLY, switching power converters use a high-switching controller to reduce the size of the output filter for compact solution in portable devices, such as cellular phones, wireless devices, and Bluetooth applications. However, the design of a high-switching controller needs to consider carefully the power conversion efficiency and high-switching noise caused by parasitic components. In general, the efficiency of a converter is defined as the ratio of output power, , to input power, , as expressed in (1)

(1) is the sum of power loss in switching converters and ex-pressed as (2). and are the conduction and switching losses, respectively. is the power loss in the controller com-posed of analog and digital circuits [1]

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Manuscript received September 21, 2010; revised January 25, 2011; accepted March 21, 2011. Date of publication May 16, 2011; date of current version June 29, 2011. This paper was recommended by Associate Editor C. Piguet.

The authors are with the Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu, Taiwan (e-mail: khchen@cn.nctu.edu.tw).

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSI.2011.2142970

Fig. 1. The conventional current mode buck converter.

The conventional pulse width modulation (PWM) of the cur-rent mode control (Fig. 1) becomes limited as switching fre-quency increases. The control system can have high efficiency at heavy loads as the is kept low by using low on-resis-tance of power switches. Incidentally, efficiency decreases dras-tically when the load gradually decreases to no load condition since the increasing value of dominates it. Specifically, the high-switching operation resulting from the use of a small in-ductor could deteriorate efficiency. Thus, it is important to keep high efficiency over a wide load range.

The power converter system generally undergoes multiple op-eration modes in order to extend the battery life of present-day portable devices. Essentially, these include standby mode reg-ulated by the pulse frequency modulation (PFM), burst mode to save on power, and normal PWM operation mode to sus-tain system operation [2]–[5]. However, the circuit complexity, output ripple, and noise issue are not effectively treated at the same time [6]–[9]. For high-switching operation, it is important to carefully consider the specifications at the same time since the performance of the power converter will be deteriorated and the load current range will be limited [10], [11]. Furthermore, in the current-mode control, high-switching frequency decreases system accuracy due to limited response time of the inductor current sensor [12]–[14]. In addition, the switching noise dras-tically increases to deteriorate the accuracy of current sensor to decrease the system stability.

Thus, it is important to improve the estimation accuracy of the inductor current for high-switching operation. In prior arts, the equivalent series resistance (ESR) on the output capacitor can be used to generate the current ripple to achieve fast load tran-sient response through the two voltage feedback loops. How-ever, it suffers from large output voltage ripple and low effi-ciency [15]–[20]. Besides, using large ESR for system stability

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1672 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 7, JULY 2011

TABLE I

A COMPARISON OF THECONVERTERWITHDIFFERENTCONTROLMETHODS

limits the selection of output capacitor. Specifically, the large ripple reduces the performance of the sequent stage that needs small transient voltage dip [21]–[23]. Therefore, the proposed dual modulation technique with the ac ripple detector needs to improve power conversion and remove high-switching noise to increase system stability simultaneously.

The dual modulation technique can separate the inductor cur-rent into the ac ripple signal and the loading potential signal. It can accurately acquire the inductor current information to de-cide the duty cycle without the need of large ESR. The loading potential signal not only can determine the optimum switching numbers for each power switch at different loads, it also can generate a hopping switching frequency at light loads for high-conversion efficiency. Furthermore, the hopping switching fre-quency should be higher than the acoustic frefre-quency to avoid noisy sound. Compared with conventional PWM switching con-verters, the dual modulation technique can achieve faster tran-sient response and higher power conversion efficiency simulta-neously with an acceptable output ripple. In addition, multilayer ceramic capacitors (MLCC) can be selected as the output capac-itor for low cost. The low-cost MLCC becomes more popular due to its low ESR. Thus, the proposed ac ripple detector can sense the low inductor current ripple. It is superior to those de-signs without using MLCC.

Table I compares the converter with different control methods. The dual modulation mode not only has good ef-ficiency but also reduces the output ripple and chip area compared with other methods. Specially, the audio noise, which is important issue for communication applications, can be effectively reduced.

The organization of this paper is shown as follows. Section II introduces the design concept of the proposed dual modulation technique and the ac ripple detector. The circuit implementation is shown in Section III. The close-loop analysis is described in Section IV to demonstrate the system stability. Experimental results shown in Section V can prove the correction and advan-tages of the dual modulation technique. Finally, conclusions are given in Section VI.

II. DESIGNCONCEPTDESCRIPTION

For high-switching operation, power conversion efficiency decreases drastically when load current changes from heavy to light. The dual modulation technique needs to hop switching fre-quency to find a trade-off between power conversion efficiency and output voltage ripple when load current decreases [25].

The timing diagram of the dual modulation technique is illus-trated in Fig. 2. The original PWM control uses a high-switching

Fig. 2. Waveforms of the buck converter with the dual modulation technique.

signal to regulate the output voltage to achieve a reduced ripple. Since the conduction loss dominates the whole power consumption at heavy loads, the high-switching signal would not result in a great decrease in efficiency. However, the switching loss drastically deteriorates efficiency from medium-to light-load condition due medium-to the high-switching operation. Therefore, the secondary modulator becomes necessary to re-duce the switching numbers as shown by the modulated signal used to control the power switches. At this time, dual modulation operates to raise efficiency within an allowable output ripple.

The architecture of the proposed dual modulation technique is shown in Fig. 3. The controller is separated into two parts. The primary modulator makes the system operate normally under high-switching frequency, and the secondary modulator can raise power conversion efficiency at light loads. Thus, high power conversion efficiency and a fast transient response under high-switching operations can be achieved. The dual modulation technique should detect the load condition using the proposed loading potential detector (LPD) circuit. In addition, the combination of the LPD circuit and the error signal received by the error amplifier can be viewed as the control signal in the hopping frequency modulator (HFM) circuit. As a result, the hopping signal generated by the secondary modulator can regulate the original PWM signal to find the trade-off between efficiency and output voltage ripple.

The flow diagram of the dual modulation technique is shown in Fig. 4. Basically, the operation of primary modulator is similar to that of the buck converter. When the load current is smaller than the threshold current , the dual modulation is started. That is, the PWM signal generated by the primary modulator will be modulated by the secondary modulator to reduce the switching power loss. As the current is smaller than 10 mA, the system will automatically switch to secondary modulation. The secondary modulator contributes to the decrease in the switching frequency and the increase in the hopping period. Light-load conditions require reduced switching frequency in order to save power. The HFM circuit can determine a suitable switching frequency to reduce substantially the switching power loss at the power switches. Meanwhile, dual modulation starts to decrease the switching

frequency from the constant to

through the hopping frequency, , in the secondary modu-lator. As depicted in Fig. 5, the value of varies with load current.

In addition, the hopping frequency not only reduces switching loss but also always keeps the output ripple within the allowable range.

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Fig. 3. The proposed buck converter with the dual modulation technique.

Fig. 4. The flow chart of the dual modulation system.

The decrease in the switching frequency is accompanied with an increase in the hopping period as load current declines continuously. The decrease in switching frequency results in increased efficiency from a medium- to light-load condition. Much power is retrenched due to the switching loss reduction at the power MOSFETs. To further raise efficiency at very light loads, the primary modulator is shut down automatically and only the secondary modulator is employed to regulate the output voltage and to save much power in the quiescent operation loss. Furthermore, to avoid operation in the acoustic region, the hopping frequency is always kept higher than the acoustic frequency, , even at no load condition.

For high-switching converters, the conventional current sensing method may fail to provide accurate sensing load cur-rent due to limited bandwidth. Thus, it is better to find a suitable current sensing method for the high-switching converter. Fig. 6 shows the concept of the proposed ac ripple control. In time domain, the output LC stage of the converter can be considered as a low-pass filter and work as an integrator.

Fig. 5. Efficiency and hopping frequency versus load current in the proposed converter system.

However, the existence of ESR and ESL may deteriorate the accuracy of current sensing signal and the steady state duty cycle. Considering the ESR, , and the equivalent series inductor (ESL), , on the output capacitor, , the output voltage ripple can be evaluated as the summation expressed in (3)

(3) Briefly, (3) is composed of overshoot voltage, , across the ESR; induced voltage, , which is the differentiation of the inductor current with ESL; and voltage ripple, , which is the integration of the inductor current on the [26],

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Fig. 6. The concept of current sensing flow as it utilizes the ac ripple detector.

Fig. 7. Schematic of the HFM circuit.

[27]. Thus, it is convenient to differentiate in order to ob-tain the ac signal of the inductor current. This can be expressed as

(4) At the right side of (4), the first and second terms represent the effect of the ESR and ESL, respectively. Owing to high-switching operation, the ESR and ESL seriously affect system stability and result in a large output ripple. The inductor current information can be accurately derived through the operation of the proposed ac ripple detector. The ac ripple detector behaves as a differentiator and inserts one low-frequency zero to increase system stability. One low-pass filter is utilized to filter out the high-frequency components contributed by the ESR and ESL. Consequently, the accurate inductor current can be derived as the PWM ramp since the effect of the ESR and ESL can be efficiently removed. In other words, the cheap MLCC can be selected as the output for low cost.

Fig. 8. Schematic of the frequency hopper.

Fig. 9. Schematic of LPD circuit.

III. CIRCUITIMPLEMENTATION

A. Hopping Frequency Modulator Circuit

The HFM circuit, as shown in Fig. 7, can generate a load-de-pendent pulse, , to modulate the primary PWM signal in order to reduce further the switching loss [28]. Besides, the hop-ping frequency technique is used to power-level tracking power amplifier with reduced spurious emission by utilizing a dc-dc converter. The frequency-hopping technique is implemented by varying the switching frequency of the dc-dc converter, which supplies the power of an RF PA. Ideally, if two switching fre-quencies are used and each frequency is used half of the time, the magnitude of the resulting spurs can be reduced by 6 dB [29]. In our design, the signal , is controlled by two vari-ables, which are the error signal, , from the error amplifier and the dc load current signal, , from the LPD circuit. It can decide an adequate duty cycle in the HFM circuit once the dual modulation technique is triggered. The output voltage may have a large drop voltage caused by the small value of , which induces a large number of switches skipped. The drop voltage at the output raises the value of to constitute a neg-ative feedback loop for increased system stability.

The charging current for the capacitor, , is determined by the current signal decided by the values of and and expressed as (5)

(5)

Fig. 10. Schematic of the ac ripple detector.

Fig. 11. Small-signal model of the ac ripple control buck converter.

defines the threshold current that switches the operation from the primary PWM to dual modulation. As load current de-creases continuously, the system switches automatically to dual modulation; that is, load current is smaller than . The current is converted from the signal by the voltage-to-current (V-to-I) converter. The minimum value of corresponds to the largest charging current for the that result in the shortest charging time. As a result, the duty of the HFM pulse can contain the longest duration at very light loads to reduce the switching frequency at the power switches.

The charge on the capacitor is reset by a hopping fre-quency signal, RST , generated by the frequency hopper in order to vary the hopping frequency, , based on load cur-rent. Consequently, the decreases and the duty cycle in-creases to reduce the switching numbers at the power MOSFETs when load current becomes light. Thus, efficiency can be im-proved. On the other hand, the HFM pulse is greatly decreased, and small enough to have no effect on the high-switching PWM pulse during the primary PWM operation. Only the primary PWM operates to suppress output ripple.

B. Frequency Hopper

The frequency hopper is used to generate a load-dependent hopping switching frequency for the HFM circuit. The load-dependent hopping switching frequency varies over a wide load

TABLE II

DESIGNPARAMETERS OF THEPROPOSEDCONVERTER

Fig. 12. Bode plot of the proposed converter system.

range if the secondary starts to work from medium to very light-load condition.

As shown in Fig. 8, the is generated by the LPD circuit to determine the dc load current condition. The current signal converted from the by the V-to-I converter is nearly equal to the charging current , which is expressed as (6) and can determine the hopping frequency as shown in (7) due to the small current . The frequency hopper can let the user design the desired frequency by adjusting of and

(6) (7) Since the system has a primary high-switching frequency, , the clock synchronizer is used to synchronize the output signal RST with high-switching clock, CLK. It also can fix the pulse width of the signal RST for regular operation in the dual modulation technique compared with using the signal RST.

When load current changes from 1 mA to 150 mA, the varies from 70 kHz to 1 MHz. Meanwhile, the can range from 70 kHz to 3 MHz. As a result, a lot of switching loss can be reduced to improve power conversion efficiency. In this design, the switching frequency reverts to high-switching oper-ation of 5 MHz when load current is larger than , which is designed as 150 mA. The selection of 5 MHz is to sup-press the output ripple smaller than 50 mV at medium to heavy loads.

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Fig. 13. Chip micrograph.

C. Loading Potential Detector Circuit

The LPD circuit (Fig. 9) is used to generate the loading po-tential signal, , which is proportional to the dc load current [30], [31].

The sensing transistor, , with the aspect ratio much smaller than the power PMOSFET, SW , at the power stage, the virtual short-circuit characteristic of the operational amplifier can mirror the inductor current in the power P-type MOSFET to the sensing transistor. The sensing current can be scaled down to the transistor during the rising period. The sensing current flows through the internal resistor and is filtered by the low-pass filter to suppress the switching ripple in generating the loading potential signal .

The design of the compensator contains two low pass filters composed of , , , and to get a smooth con-trol signal to generate a dual modulation signal to find out the trade-off between the output ripples and the efficiency. Besides, the low pass filters will stable the secondary modulation and it will be analyzed in Section IV.

The hysteretic comparator compares the output signal with the predefined threshold voltage . When is smaller than (i.e., the system is at very light loads), the hysteretic comparator triggers the signal, SET, from high to low. Specifically, to promote additional power saving, the primary modulator shuts down and the output voltage of the system is regulated only by the secondary modulator at very light loads.

Since the LPD circuit extracts the dc value of the load cur-rent, the bandwidth of the operational amplifier should not be too large to save power; that is, the selection of the operational amplifier can only be a simple one-stage structure with low quiescent current in order to save chip area and power con-sumption. Furthermore, the biasing current induces a minimum output sensing current even at no load condition, indicating a minimum value at the signal . As a result, the hopping fre-quency can be always kept higher than the acoustic frefre-quency to address the noise issue.

D. AC Ripple Detector

The schematic of the ac ripple detector is shown in Fig. 10. Apart from its ability to determine the ac value of the inductor

TABLE III DESIGNSPECIFICATIONS

current, the ac ripple detector can also eliminate high-frequency noise due to ESL [26], [27].

In time-domain, the high-speed voltage-controlled current-source (VCCS) circuit is used to differentiate the output feed-back signal, , to generate a low-frequency zero without the need of large compensation capacitor for reducing silicon area. Owing to the simple circuit structure, the bandwidth can be extended beyond that of conventional current sensing circuit using an operational amplifier. Thus, the is converted to a small-signal current to charge and discharge the capac-itor. Before generating the sensing signal , the small-signal current is delivered to the ESL cancellation circuit to eliminate the ESL effect using a low-pass filter.

The signal of contains the ac inductor current, , and the high-switching noise generated by the ESL, . After the operation of ESL cancellation circuit, the pure ac inductor current can be derived to modulate the primary modulator. Thus, the value of approximately equals to (8). rep-resents the value of after the low-pass filter

(8) The sensing ac signal, , can be received as shown in (9) by the sensing resistor

(9) Thus, the sensing signal can be produced correctly and rapidly under high-switching operation.

IV. SMALL-SIGNALANALYSIS OF THEPROPOSEDSYSTEM

Fig. 11 shows the small-signal model of the dual modulation buck converter with the ac ripple detector [26]. The loop gain can be divided into two parts. The first part, which is the power stage, contributes duty-to-output transfer function and contains

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TABLE IV

THE COMPARISONS ARE BETWEEN THE PROPOSED METHOD AND THEPRIORARTS

dual poles due to the output LC filter as expressed in (10) with a dc gain of

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The zero, , generated by is pushed to high frequen-cies by using small ESR. is the loading resistor and is the series resistor of the LC resonant loop, which is the sum of MOSFET on resistance, inductor resistance, and .

The second part, composed of the controller, contributes the output-to-duty transfer function. In dual modulation, the control path contains two feedback loops, namely, the primary loop and the secondary feedback loops. The primary feedback loop is de-termined by the ac ripple detector and the error amplifier. Thus, the primary duty cycle can be decided through the signals, and , by the PWM comparator. On the other hand, the sec-ondary feedback loop is determined by the error amplifier and the secondary modulator.

The loop selection is determined by the LPD circuit. At very light loads, only the secondary modulator loop is selected as the feedback path. The feedback signal directly passes through the secondary modulator loop, , to generate the duty cycle. As load current increases continuously, the feedback signal passes through both primary and secondary loops. Thus, dual modulation combines the primary and the secondary mod-ulators at medium to light loads. At heavy loads, the feedback path is decided by the primary modulator when load current is larger than . The feedback signal only passes through the primary loop since the secondary loop

is disabled and the switch is always connected to the primary path.

The transfer function, , of the error amplifier with the PI compensator can be derived as (11)

(11) The dc gain is constituted by the error amplifier’s transcon-ductance, , and the output resistance, . The PI com-pensator introduces one pole, composed of and compensation capacitor , and one zero, composed of the compensation network, and .

Similarly, the transfer function, as shown in (12) contributed by the secondary modulator, is used to provide a low-bandwidth response to filter out the high-switching PWM signal according to the load current. Thus, the dc gain of the is inversely proportional to the load current and con-trolled by

(12)

where , , and

is the low-frequency gain.

The close-loop transfer function in the secondary modulator can be expressed as (13)

(13) Therefore, the close-loop transfer function in dual modulation can be expressed as (14)

(14) As the load decreases continuously, the contribution of the primary modulation becomes smaller than that of the secondary modulation. At very light loads, the secondary modulator can take over the control authority.

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Fig. 14. Waveforms of the output voltage and inductor current at different load current conditions. (a)I = 5 mA. (b) I = 20 mA. (c) I = 110 mA (d) I = 220 mA.

In this study, the primary modulation is demonstrated as fol-lows: The control duty can be expressed as (15) to include the results from the ac ripple detector and the error amplifier

Fig. 15. Load transient response. (a) Load current steps from 150 mA to 450 mA or vice versa. (b) Load current steps from 1 mA to 500 mA or vice versa. The modulation rapidly switches between the secondary and the primary modulation techniques.

where is the sensor gain. (15)

Owing to the LC double poles, the ac ripple detector as a differentiator can introduce a low-frequency zero, , with a time constant, , to increase the system stability. Thus, the transfer function, , is shown in (16)

(16) In a steady state, the PWM comparator transfer functions and have the same value of as defined in (17)

(17) Thus, the output-to-duty transfer function can be derived as shown in (18). As expressed in (19), the system contains one single, low-frequency dominant pole, , and two compen-sated zeros,

(18)

(9)

Fig. 16. (a) Efficiency comparison between the original PWM operation and the proposed dual modulation technique. (b) Efficiency of the proposed con-verter over a wide range of load current.

As a result, the close-loop transfer function can be expressed in (20), which contains two zeros and three poles. According to design parameters shown in Table II, the position of the three poles and the two zeros can guarantee system stability during the primary PWM operation

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Fig. 12 depicts the analytic Bode plot of the primary modu-lator with the ac ripple detector. Expectedly, the phase margin is larger than 45 degrees since the pole-zero cancellation of the proposed ac ripple detection technique is achieved without using a large ESR.

V. EXPERIMENTALRESULTS

The circuit was implemented by the TSMC 0.25 m CMOS process. The chip micrograph is shown in Fig. 13. The specifica-tions of the converter are listed in Table III and the comparison list of the dcdc buck converter is shown in Table IV.

Fig. 14 shows the output waveforms at different load current conditions when the converter enables the dual modulation tech-nique. Fig. 14(a)–(c) reveals how the HFM circuit can adjust the switching frequency dynamically according to load current. Fig. 14(d) shows the system correctly reverts to the PWM mode when load current is raised higher than .

The waveforms of the output voltage and the inductor current during load transient response are shown in Fig. 15. Fig. 15(a) shows the recovery times are about 2.5 s and 3 s when load current changes from 150 mA to 450 mA and vice versa, respec-tively. And the load current changes from 1 mA to 500 mA and

vice versa as shown in Fig. 15(b). This demonstrates the system

stability is controlled by the dual modulation system with the ac ripple detector.

Fig. 16(a) shows the comparison in efficiency between the conventional PWM operation and the proposed dual modu-lation technique. The number of switching signal at the gate of the power MOSFETs can be effectively reduced. As a result, the maximum efficiency improvement is about 45% at load current mA. The efficiency of the proposed converter over a wide load range is shown in Fig. 16(b). The level of effi-ciency dropped slightly at the mode transition within allowable specification. However, this demonstrates that efficiency can be always kept high by using the dual modulation technique.

VI. CONCLUSION

The proposed dual modulation technique can enhance power conversion efficiency within the allowable output voltage ripple for the supply of system-on-a-chip applications. The pro-posed ac ripple detector can alleviate the worsening switching noise caused by parasitic resistance and inductance due to high-switching operation. In addition, the switching frequency can be kept higher than the acoustic frequency to avoid noisy sound in the LPD circuit. Experiment results show that the inductor size can be reduced to about 1 H with the switching of 5 MHz. The load transient response time is smaller than 3 s when load current changes from 150 to 450 mA or vice

versa. Furthermore, the power efficiency can be always kept

higher than 85% over a wide load current range. It ensures light efficiency can be raised about 45% above that of the conventional design.

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Jen-Chieh Tsai was born in Kaohsiung, Taiwan.

He received the B.S. degree in electrical engineering from National Yunlin University of Science and Technology, Yunlin, Taiwan, in 2003 and the M.S. degree in electrical engineering from Tamkang University, Taipei, Taiwan, in 2005. He is currently working toward the Ph. D. degree in electrical and control engineering, National Chiao Tung Univer-sity, Hsinchu, Taiwan.

His research area contains many projects of high resolution ADC, low power DAC, and power man-agement ICs at the Low Power Mixed Signal Lab. His interests include power management circuit designs, PFC ICs, and analog integrated circuit designs.

Tsung-Ying Huang was born in Taoyuan, Taiwan,

who received the B.S. and M.S. degree from Elec-trical Control Engineering in National Chiao Tung University, Taiwan, in 2008 and 2010. He has participated in contains many projects of power management ICs at Low Power Mixed Signal Lab in National Chiao Tung University, Taiwan. Also he is presently an advanced engineer of analog IC design in Novatek Microelectronics Corporation in Hsinchu Science Park, Taiwan. His interests include power management circuit designs and analog integrated circuit designs.

Wang-Wei Lai was born in Taoyuan, Taiwan, on July

22, 1986. He received the M.S. degree in electrical control engineering from National Chiao Tung Uni-versity, Taiwan, in 2010.

His research area contains many projects of power management ICs in Low Power Mixed Signal Lab in National Chiao Tung University, Taiwan. Currently, he is an Advanced Engineer of analog IC design at Novatek Microelectronics Corporation in Hsinchu Science Park, Taiwan. His interests include power management circuit designs and analog IC designs.

Ke-Horng Chen (M’04–SM’09) received the B.S.,

M.S., and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, in 1994, 1996, and 2003, respectively.

From 1996 to 1998, he was a part-time IC De-signer at Philips, Taipei. From 1998 to 2000, he was an Application Engineer at Avanti, Ltd., Taiwan. From 2000 to 2003, he was a Project Manager at ACARD, Ltd., where he was engaged in designing power management ICs. He is currently an Associate Professor in the Department of Electrical Engi-neering, National Chiao Tung University, Hsinchu, Taiwan, where he organized a Mixed-Signal and Power Management IC Laboratory. He is the author or coauthor of more than 100 papers published in journals and conferences, and also holds several patents. His current research interests include power management ICs, mixed-signal circuit designs, display algorithm and driver designs of liquid crystal display (LCD) TV, red, green, and blue (RGB) color sequential backlight designs for optically compensated bend (OCB) panels, and low-voltage circuit designs.