This content has been downloaded from IOPscience. Please scroll down to see the full text.
Download details:
IP Address: 140.113.38.11
This content was downloaded on 24/04/2014 at 14:58
Please note that terms and conditions apply.
Flip-Chip Packaging of Noise Metamorphic High Electron Mobility Transistors on
Low-Cost Organic Substrate
View the table of contents for this issue, or go to the journal homepage for more 2011 Jpn. J. Appl. Phys. 50 096503
(http://iopscience.iop.org/1347-4065/50/9R/096503)
Flip-Chip Packaging of Low-Noise Metamorphic High Electron Mobility
Transistors on Low-Cost Organic Substrate
Chin-Te Wang, Chien-I Kuo, Heng-Tung Hsu1, Edward Yi Chang, Li-Han Hsu, Wee-Chin Lim, and Yasuyuki Miyamoto2
Department of Materials Science and Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan
1Department of Communications Engineering and Communication Research Center, Yuan Ze University, Chunli 320, Taiwan 2Department of Physical Electrons, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan
Received March 29, 2011; accepted June 17, 2011; published online September 20, 2011
The rapid growth of high-frequency wireless communication demands high-performance packaging structures at low cost. A flip-chip interconnect is one of the most promising technologies owing to its low parasitic effect and high performance at high frequencies. In this study, the in-house fabricated In0:6Ga0:4As metamorphic high electron mobility transistor (mHEMT) device was flip-chip-assembled using a commercially available low-cost organic substrate. The packaged device with the optimal flip-chip structure exhibited almost similar DC and RF results to the bare die. An exopy-based underfill was applied to the improvement of reliability with almost no degradation of the electrical characteristics. Measurement results revealed that the proposed packaging structure maintained a low minimum noise figure of 3 dB with 6 dB associated gain at 62 GHz. Such a superior performance after flip-chip packaging demonstrates the feasibility of the proposed low-cost organic substrate for commercial high-frequency applications up to the W-band. # 2011 The Japan Society of Applied Physics
1. Introduction
The demand for communication systems at frequencies up to the W-band has been growing rapidly in recent years because such systems have the potential of providing high data transmission rates.1,2)The high-frequency performance of these systems mainly depends on the device character-istics and packaging structure. In terms of the device tech-nology, indium-rich InxGa1xAs/InxAl1xAs-based
meta-morphic high electron mobility transistors (mHEMTs) are gaining increasing popularity owing to the high electron mobility and saturation velocity of the InGaAs materials, which in turn delivers a lower noise figure with higher gain at high frequencies.3–6)
The packaging structure is also an essential issue for practical implementation concerns. Generally, such a structure should provide a reliable transmission path from chip to substrate and protect the device from external hazards, such as environmental effects, mechanical stress, and humidity.7) Conventionally, the chip is assembled on ceramic-based substrates, such as Al2O3,8) and then the ceramic-based substrates are integrated into the systems made of printed circuit boards (PCBs).
Despite the major advantages provided by the flip-chip packaging, such as good thermal management, good mechanical stability, and high reliability,9–11) mounting ceramic-based substrates onto PCBs unavoidably introduces additional transitions in signal paths, which will induce extra parasitic effects to impact the system performance. In addition, the approach also causes additional cost owing to the transition from ceramic substrates to PCBs.
This work is performed to develop a low-cost yet robust flip-chip-on-board (FCOB) technology for high-frequency applications up to the W-band. A commercially available PCB (RO3210 organic substrate from Rogers) was adopted for the feasibility study of the proposed technology. To further improve the reliability of the overall structure, an epoxy-based underfill, which can alleviate the stress on the bump transitions between the chips and the PCB,12–14) was applied. Possible performance degradations at high
frequen-cies due to the inclusion of the underfill (though with low dielectric constant) were taken care of by the optimal design of the geometries on the RO3210 organic substrate through full-wave electromagnetic simulation.
In the following sections, the in-house fabrication process of the proposed technology is presented in detail. In0:6Ga0:4As mHEMT devices were flip-chip-assembled onto the RO3210 organic substrate to demonstrate the applica-bility of such a technology to high-frequency applications. The optimal design of the layout patterns on the RO3210 organic substrate was verified by the measurement of flip-chip-bonded 50 transmission lines. To investigate the effect of the epoxy-based underfill on the overall perfor-mance, comparisons were performed on the flip-chip-assem-bled devices with and without underfill injection. Measure-ment results revealed an insertion loss of less than 1 dB and a return loss lower than 20 dB up to 110 GHz for the flip-chip-bonded 50 transmission lines with an optimal design. For a flip-chip-bonded mHEMT with an optimal transmission line design, a minimum noise figure of 3 dB with 6 dB associated gain at 62 GHz was achieved. The superior performance proves that it is possible to flip-chip assemble mHEMT devices onto commercially available organic substrates for operation up to the W-band at competitive cost.
2. Experimental Procedure
Both the GaAs substrate with 50 coplanar waveguide (CPW) transmission lines and the In0:6Ga0:4As mHEMT device with 150 nm gate length were flip-chip-assembled on the RO3210 organic substrate for performance characteriza-tion. The interconnect structure is shown in Fig. 1. The In0:6Ga0:4As mHEMT device with 150 nm gate length used in this study was fabricated using in-house process described in detail in ref.15. For the passive structures on the RO3210 organic substrate, the fabrication process started with the metallization of the GaAs substrate. The seed layers of titanium (Ti) and gold (Au) metals with thicknesses of 500 and 1000 A were deposited by an E-gun evaporator. A thin photoresist was patterned for the following gold electroplat-ing of the CPW transmission lines. After electroplatelectroplat-ing, the thin photoresist and seed layers were removed. The GaAs substrate was then thinned down to 100m and diced.
E-mail address: edc@mail.nctu.edu.tw
The choice of commercially available PCBs as the substrates instead of the ceramic-based substrates helps to meet the low-cost target. However, surface treatment played an important role in the proposed FCOB technology. Figure 2(a) shows the SEM image of the RO3210 organic substrate, which has a surface roughness of 3m. To improve the adhesion between the metallization layer and the PCB substrate, the PCB surface roughness was reduced through a chemical mechanical polishing (CMP) process. Figure 2(b) shows the SEM image of the PCB surface after CMP, where an improvement in surface roughness from 3 to 1m can obviously be seen. The flip-chip interconnect structure on the RO3210 organic substrate was
in-house-fabricated by photolithography and electroplating. Firstly, the seed layers of Ti and Au metals were deposited by an E-gun evaporator with thicknesses of 500 and 1000 A, respectively. The Ti layer was used as the adhesion layer between the Au circuit and the RO3210 organic substrate. The CPW transmission line with a characteristic impedance of 50 was patterned on the photoresist and gold-elec-troplated to a thickness of 3m. Then, the thick photoresist for bump transition was performed. Subsequently, the gold bump transition was electroplated with optimization condi-tions to achieve enough bump height for the following flip-chip bonding process.
After the chip and RO3210 organic substrate were fabricated, the flip-chip bonding process was performed using M9 flip-chip bonder system. The chip was flip-chip-assembled on the RO3210 organic substrate by Au-to-Au thermal compression process with optimization bonding conditions, such as bonding temperature, bonding time, and bonding force.
To improve the reliability, the epoxy-based underfill with low dielectric constant was injected into the gap between the chip and the substrate using an underfill capillary process. The material properties of the underfill are listed in Table I. This underfill has a low viscosity that allows it to flow into the gap between the device and the substrate by capillary force. Finally, the flip-chip structure with the underfill was cured at 150C for 2 h in oven. The curing process helps to reduce the air entrapment and increase the reliability of the package itself.
3. Design and Optimization
Prior to the assembly of active devices through the flip-chip bonding process, the high-frequency characteristics of the RO3210 organic substrate were investigated by the measurement of a 50 CPW transmission line. A 50 CPW transmission line designed on the RO3210 organic substrate with a line width of 50m and a spacing of 27 m between the signal trace and the ground, and a length of 854m was fabricated and measured. Figure 3 shows the measured results up to 110 GHz using an on-wafer probing system after load–reflection–reflection–match (LRRM) cali-bration. The simulated results using electromagnetic simu-lators16) are also included. The measured and simulated insertion losses (S21) match well with a difference of less than 0.7 dB up to 110 GHz. The measured return loss of the CPW thru line was below 20 dB up to 90 GHz. Generally, the organic substrate exhibited low insertion and return losses for W-band applications.
An underfill is commonly used in flip-chip packaging for reliability improvement. It is clear that the impedance will change with the inclusion of the underfill between the chip and the RO3210 organic substrate since the additional dielectric layer will alter the distribution of the
electro-Fig. 1. (Color online) Schematic view of the flip-chip interconnect structure.
(a)
(b)
Fig. 2. SEM images of the low-cost RO3210 organic substrate (a) before and (b) after CMP lapping process.
Table I. Materials properties of epoxy-based underfill. Tg (C) CTE (ppm/C) Moisture absorption (%) "r tan Epoxy-based underfill 140 46 <1 3.2 0.02 C.-T. Wang et al. Jpn. J. Appl. Phys. 50 (2011) 096503
magnetic field with the epoxy-based low dielectric constant material adopted. Figure 4(a) shows the measured S-para-meters of the 50 CPW transmission line on GaAs flip-chip-assembled on the RO3210 organic substrate with and without the underfill, and the pattern is also included for reference. Cylindrical bumps of 40m diameter and 20 m height were used throughout the structure. As can be observed in Fig. 4(a), both frequency shift and impedance degradation occur at frequencies above 60 GHz for the structure with the underfill compared with the structure without the underfill. The corresponding S11 plotted in
the Smith chart is shown in Fig. 4(b). It is clearly seen in Fig. 4(b) that the impedance is mainly capacitive at high frequencies. To compensate for this capacitive characteristic of the impedance, a 50-m-long high-impedance transmis-sion line section was introduced into the RO3210 organic substrate, as shown in Fig. 5(a). Figure 5(b) shows the effect of the width of this high-impedance line simulated using an HFSS simulation tool.16)Apparently, a length of 25m gave the optimal performance over the frequency range of interest. Such an observation was then verified by experi-ment. Figure 6 shows the measured response of the 50 CPW transmission line on GaAs flip-chip-assembled on the RO3210 organic substrate with the high-impedance line including the optimized compensation structure. As expected, good impedance match is observed up to 110 GHz with an insertion loss of less than 0.6 dB, indicating that excellent transmission properties were obtained from the optimal design.
4. Performance Characterization of the Packaged Device
To demonstrate the capability of the proposed technology for device application, an In0:6Ga0:4As mHEMT device with
0 -50 -40 -30 -20 -10 0 Simulation Measurement Frequency (GHz) Return loss (dB) -2.5 -2.0 -1.5 -1.0 -0.5 0.0 Insertion loss (dB) 100 80 60 40 20
Fig. 3. (Color online) Simulated and measured results of the CPW transmission lines on low-cost organic substrate.
(a) (b) 0 -40 -30 -20 -10 0 Return loss, S1 1 (dB) Frequency (GHz) Common flip-chip structure
With underfill Without underfill -4 -3 -2 -1 0 Insertion loss, S21 (dB) 100 80 60 40 20
Fig. 4. (Color online) (a) Measured S-parameter of the common flip-chip interconnect structure and (b) Smith chart of the corresponding S11results.
(a) (b) 0 -50 -40 -30 -20 -10 0 Without Compensation Comp. Width 40 um Comp. Width 25 um Frequency (GHz) Return loss, S1 1 (dB) -5 -4 -3 -2 -1 0 Insertion loss, S21 (dB) 100 80 60 40 20
Fig. 5. (Color online) (a) Schematic and (b) simulation results of the compensation design in flip-chip interconnect structure.
150 nm gate length was flip-chip-assembled on the RO3210 organic substrate for performance evaluation. Note that the high-impedance transmission lines used to compensate for the capacitive impedance were included in the patterns on the RO3210 organic substrate to connect the gate and drain of the device. Figure 7 shows the measured DC character-istics where the transconductance (gm) and drain current
(IDS) are plotted as functions of drain voltage at various
gate bias levels. Similar performance characteristics were obtained for the flip-chip-packaged device. The RF perfor-mance was characterized using an on-wafer probing system with a vector network analyzer up to 110 GHz. Figure 8 shows the measured S21against frequency up to 110 GHz for the bare die, flip-chip-packaged device without the underfill, and flip-chip-packaged device with the underfill. All the devices were biased at peak gm occurrence with the input
and output terminated by a 50 load. A degradation of less than 2 dB was observed for the flip-chip-packaged device with the underfill compared with the bare die over the entire frequency range of interest. The effect of the compensation
through high-impedance lines was evidenced by the minor degradation observed for frequencies above 60 GHz. In this aspect, the proposed FCOB approach showed a certain competitive edge over the conventional approach. In ref.17, a Ka-band LNA MMIC chip was firstly packaged into a ceramic-based QFN package and then integrated into an RO4003C PCB. A gain degradation of 4.5 dB at 40 GHz compared with the bare die case was presented. Finally, the minimum noise figure (NFmin) was measured and is plotted
in Fig. 9. As is shown, the flip-chip-packaged device with the underfill exhibited anNFmin of 3 dB with an associated
gain of 6 dB at 62 GHz, indicating promising results of the proposed low-cost FCOB technology for applications in the W-band.
5. Conclusions
In this study, we have successfully demonstrated the FCOB technology for applications in the W-band at very low cost. The main breakthrough for the proposed technology lies in the fact that commercially available organic substrates were used as the carriers instead of conventional ceramic-based
0 -40 -30 -20 -10 0 Insertion loss (dB) Return loss (dB) Frequency (GHz) Flip-chip structure with compensation
With underfill Without underfill -2.0 -1.5 -1.0 -0.5 0.0 100 80 60 40 20
Fig. 6. (Color online) Measured S-parameter results of the optimized flip-chip interconnect structure with and without underfill.
-1.4 0 100 200 300 400 500 600 700 In0.6Ga0.4As mHEMT Lg = 150 nm; VDS = 0.8 V
Bare die FC package
FC package with UF Gate-source voltage, VGS (V) Drain current, I DS (mA/mm) 0 100 200 300 400 500 600 700 T ransconductance, gm (mS/mm) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2
Fig. 7. (Color online) Comparison of drain current density (IDS) and
transconductance (gm) as a function of gate–source voltage (VGS) at
VDS¼ 0:8 V between the In0:6Ga0:4As mHEMT device, packaged device, and packaged device with underfill.
100 10 1 0 2 4 6 8 10 12 S-parameter (dB) Frequency (GHz) In0.6Ga0.4As mHEMT Lg = 150 nm; VDS= 0.8 V, VG=- 0.6 V Bare die FC package FC package with UF
Fig. 8. (Color online) Comparison of insertion gain (S21) between the In0:6Ga0:4As MHEMT device, packaged device, and packaged device with underfill. 0 1 2 3 4 5 6 70 60 50 40 30 In0.6Ga0.4As mHEMT;Lg = 150 nm VDS= 0.8 V, VG= -0.6 V
Bare die FC package
FC package with UF Frequency (GHz) Noise Figure, NF (dB) 0 2 4 6 8 10 12 Associated Gain (dB)
Fig. 9. (Color online) Comparison of the minimum noise figure and associated gain at VDS¼ 0:8 V, VG¼ 0:6 V between the In0:6Ga0:4As MHEMT device, packaged device, and packaged device with underfill.
C.-T. Wang et al. Jpn. J. Appl. Phys. 50 (2011) 096503
substrates. Design optimization was performed on the layout patterns of the RO3210 organic substrate through elec-tromagnetic simulations, which also took into account the change in impedance due to the existence of the epoxy-based underfill for reliability improvement. High-impedance lines were introduced into the structure on the RO3210 organic substrate to compensate for the capacitive impedance and thus achieved good transmission properties when the 50 transmission line was flip-chip-assembled. The In0:6Ga0:4As mHEMT device was packaged and characterized with the optimized structure design. The measured DC and RF performance characteristics of the assembled mHEMT using the proposed low-cost FCOB technology showed very promising features, indicating that this technology can be used for applications up to the W-band.
Acknowledgement
The authors would like to acknowledge the assistance and support from the National Science Council, Taiwan, R.O.C., under the contracts NSC 99-2120-M-009-005 and National Nano Device Laboratories for high-frequency measurement.
1) T. von Kerssenbrock and P. Heide:IEEE MTT-S Int. Microwave Symp.
Dig., 1999, Vol. 1, p. 289.
2) G. S. Dow, D. C. W. Lo, Y. Guo, E. W. Lin, T. T. Chung, M. D. Biedenbender, O. Miromontes, A. Marashi, L. Yujiri, P. S. C. Lee, M. M. Shoucri, and B. R. Allen:IEEE MTT-S Int. Microwave Symp. Dig., 1996,
Vol. 1, p. 369.
3) B. H. Lee, D. An, M. K. Lee, B. O. Lim, S. D. Kim, and J. K. Rhee:IEEE
Electron Device Lett.25 (2004) 766.
4) S. Kim, S. Song, W. Choi, S. Lee, W. Ko, Y. Kwon, and K. Seo:Int. Conf.
Indium Phosphide and Related Materials, 2004, p. 20.
5) K. Elgaid, H. McLelland, M. Holland, D. A. J. Moran, C. R. Stanley, and I. G. Thayne:IEEE Electron Device Lett.26 (2005) 784.
6) H. T. Hsu, C. I Kuo, E. Y. Chang, and F. Y. Kuo:Microelectron. Eng.87
(2010) 2253.
7) M. Ito, K. Maruhashi, K. Ikuina, N. Senba, N. Takahashi, and K. Ohata:
IEEE MTT-S Int. Microwave Symp. Dig., 2000, Vol. 1, p. 57.
8) H. Kusamitsu, Y. Morishita, K. Maruhashi, M. Ito, and K. Ohata:IEEE
Trans. Electron. Packag. Manuf.22 (1999) 23.
9) W. Heinrich:IEEE Int. Workshop Radio-Frequency Integration
Technology, 2005, p. 124.
10) W. Heinrich, A. Jentzsch, and H. Richter:Electron. Lett.37 (2001) 180. 11) A. Tessmann, M. Riessle, S. Kudszus, and H. Massler:IEEE Microwave
Wireless Components Lett.14 (2004) 145.
12) Z. Feng, W. Zhang, B. Su, K. C. Gupta, and Y. C. Lee:IEEE Trans.
Microwave Theory Tech.46 (1998) 2269.
13) Y. Ohshima, T. Nakazawa, K. Doi, H. Aoki, and Y. Hiruta:IEEE Int.
Reliability Physics Symp., 1997, p. 124.
14) C.-F. Chen and N. Thammadi:Int. Symp. Advanced Packaging Materials,
2006, p. 51.
15) C. I Kuo, H. T. Hsu, E. Y. Chang, Y. Miyamoto, and W. C. Tsern:Jpn. J.
Appl. Phys.47 (2008) 7119.
16) Ansoft HFSS [www.ansoft.com].
17) Y. H. Suh, D. Richardson, A. Dadello, S. Mahon, and J. T. Harvey: 13th GAAS Symp., 2005, p. 545.
