Amorphous bilayer TiO2-InGaZnO thin film transistors with low drive voltage

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Amorphous bilayer TiO

2

–InGaZnO thin ﬁlm transistors with low drive

voltage

Hsiao-Hsuan Hsu

a

_{, Chun-Hu Cheng}

b,⇑

_{, Ping Chiou}

a

_{, Yu-Chien Chiu}

a

_{, Chun-Yen Chang}

a

_{, Zhi-Wei Zheng}

a

Department of Electronics Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan, ROC

b

Department of Mechatronic Technology, National Taiwan Normal University, Taipei 10610, Taiwan, ROC

a r t i c l e

i n f o

Article history: Received 8 January 2014

Received in revised form 20 May 2014 Accepted 27 May 2014

Available online 26 June 2014

The review of this paper was arranged by Dr. Y. Kuk

Keywords: InGaZnO (IGZO) Thin-ﬁlm transistor (TFT) Titanium oxide (TiO2)

a b s t r a c t

This paper describes a high-performance thin-ﬁlm transistor (TFT) fabricated using TiO2and InGaZnO semiconducting layers. Favorable transistor characteristics, including a low threshold voltage of 0.45 V, a small subthreshold swing of 174 mV/decade, and a high ﬁeld effect mobility of 19 cm2_{/V s at a low drive} voltage of <2 V, were achieved. This favorable performance mainly resulted from the combined effect of the high-dielectric-constant gate dielectric and the TiO2–InGaZnO active semiconductor bilayer, which reduced the operating voltage, enhanced the device mobility, and improved the transistor gate swing. This TiO2–InGaZnO TFT exhibits great potential for future high-speed and high-resolution display applications.

1. Introduction

Low-temperature indium–gallium–zinc oxide (IGZO) thin-ﬁlm transistor (TFT) devices have attracted a substantial amount of attention because they require a low process temperature and feature high mobility and a high drive current. Compared with poly-Si TFTs, which require a high thermal budget, IGZO TFTs can achieve high-performance transistor characteristics at low process temperatures, ensuring greater performance uniformity and device reliability. Furthermore, studies have been demonstrated that low-temperature IGZO TFTs fabricated using high-dielectric-constant (

j

) gate dielectrics [1–7]can be integrated with high-resolution organic light-emitting diodes (OLEDs) to develop high-quality dis-play technologies that are large in area and feature low power consumption.

IGZO-TFT-driven active-matrix OLEDs (AMOLEDs) have been applied to high-resolution displays[8–10], but such applications have been hindered by critical problems regarding transistor char-acteristics, such as a large subthreshold swing (SS) and low device mobility, which must urgently be addressed to enable them to be applied in high-resolution displays. Although increasing the gate dielectric thickness can suppress gate leakage, the high operating voltage necessary to increase the driving current is unavoidable.

In addition, the low device mobility and high-voltage operation of IGZO TFTs are unsuitable for driving OLEDs, which require a high current and low power consumption.

A TFT using a TiO2 semiconducting channel was recently reported. This TiO2-channel TFT exhibited a high electron mobility of >16 cm2_{/V s and a large on–off ratio of >10}6_{, but a high operating} voltage of 40 V[11]. In our recent work, we used Ti-doped IGZO as channel capping layer to improve the transfer characteristics of TFT devices based on an oxygen gettering scheme with a thermal bud-get of 300 °C[12]. This experimental work exhibited promise for future application. However, the composition control of IGZO:Ti was difficult, and also the gettering effect could not work efficiently below 300 °C, which limited the application on flexible substrate. In this study, a high-performance bilayer IGZO TFT was fabricated by integrating with a room-temperature TiO2channel capping layer. The high transmittance in visible-light range, room temperature process and simple composition of TiO2layer make it very attractive for channel application of flexible electronics. The TiO2–IGZO TFT achieved favorable transistor characteristics, namely a low threshold voltage (VT) of 0.45 V, a small SS of 174 mV/decade, and a high field effect mobility (

l

FE) of 19 cm2/ V s under a low drive voltage (VG–VT) of <2 V. This improvement in performance is attributable to the stacked channel structure enabled by the incorporation of the room-temperature TiO2 semiconductor, which not only lowers the SS and the off-current VTbut also enhances the Ion/Ioffratio and device mobility.

http://dx.doi.org/10.1016/j.sse.2014.05.010

E-mail address:[email protected](C.-H. Cheng).

Solid-State Electronics 99 (2014) 51–54

Contents lists available atScienceDirect

Solid-State Electronics

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2. Experimental details

A bottom-gate TFT was fabricated on a 200-nm-thick insulating SiO2 substrate. A 35-nm-thick bottom TaN gate electrode was deposited using a sputtering system. Subsequently, a 25-nm-thick TiO2layer and a 30-nm-thick HfO2layer (bilayer HfO2–TiO2gate dielectric) were deposited using electron beam evaporation and annealed at a low temperature, 300 °C, to initiate dielectric activa-tion. Afterward, 15-nm IGZO was deposited in a gas mixture of 30% O2in an Ar ambient, and 8.5-nm-thick and 15-nm-thick TiO2layers were deposited at room temperature to form bilayer TiO2–IGZO structures. The control single-layer IGZO channel was fabricated to facilitate performance comparison. Finally, a 300-nm-thick Al ﬁlm was evaporated and patterned to form source and drain con-tacts. The patterned channel size was 530

l

m 45

l

m. The elec-trical characteristics of the IGZO TFT devices were characterized using current–voltage (I–V) and capacitance–voltage (C–V) measurements that were acquired using an HP4156C semiconduc-tor parameter analyzer and an HP4284A precision LCR meter, respectively.

3. Results and discussion

First, the metal-insulator-metal (MIM) capacitor of the Al/HfO2/ TiO2/TaN was measured to evaluate the ﬁlm quality of the gate dielectric. The measured capacitance density of the MIM capacitor was approximately 0.34

l

F/cm2at 100 kHz (not shown), yielding an acceptable dielectric constant (

j

value) of 20. A TiO2dielectric with high crystallinity can be activated at a low temperature of 300 °C[12] and can reach a high capacitance density because of its extremely high

j

values of 40–60[13,14]. A high capacitance density and small capacitance equivalent thickness have the

beneﬁt of reducing the operating voltage (VOP) and VT. However, amorphous TiO2with a narrow bandgap of 3.05 eV and a small conduction band offset (DEC) of only 0.05 eV[15,16]may induce a large gate leakage current, especially when the gate voltage is increased to achieve a high driving current. Furthermore, the Ti-terminated surface or weak Ti–O bond between the gate dielec-tric and channel interface generates shallow traps that degrade device mobility following an incomplete oxidation process. Nota-bly, the gate leakage of a TiO2dielectric becomes less temperature dependent when the annealed temperature is processed below 300 °C[13], enabling a high capacitance density to be reached by using a low-temperature TFT process. To prevent interface defects, a bilayer HfO2–TiO2 dielectric structure was adopted. The HfO2 layer features a large bandgap of >6 eV and a highDECof >2.3 eV

[17]in contact with IGZO channel; thus, it serves as an effective buffer layer and reduces trap-induced leakage paths near the inter-face. High-

j

TiO2, which can be activated at a low temperature, is also a potential candidate for low-temperature ﬂexible display applications[18–20].

Fig. 1(a) and (b) shows the output Id–Vd and transfer Id–Vg characteristics of a conventional single-layer (SL) IGZO TFT, respec-tively. The SL-IGZO TFT device exhibited an SS of 331 mV/decade, a mobility of 3 cm2_{/V s, and a V}

Tof 0.63 V at a drive voltage of 3 V. The SS was linked to the interface trap states (Dit) and interface charge capacitance (Cit= qDit), which were calculated based on the equation SS = kT/q ln 10 [1 + (Cb+ Cit)/Cox], where Cox, Cb, and Citare the gate oxide capacitance, bulk capacitance, and inter-face charge capacitance, respectively. Therefore, to achieve a low SS, Citmust be minimized and a high gate capacitance must be ensured. Based on the transistor characteristics, the low device mobility and large SS cannot meet the basic requirements for AMOLED application and must to be improved urgently. The

0.0 0.5 1.0 1.5 2.0 2.5 0 5 10 15 20 Drain Voltage, I D ( µµ A) Drain Voltage, V D (V) -1 0 1 2 3 10-10 10-9 10-8 10-7 10-6 10-5 10-4 Sqrt (I D_{) (} A 1/2 ) Drain Current, I D (A) Gate Voltage, V G (V) 0.00 7.50x10-3

(a)

(b)

V_G = 2.0 V SL-IGZO TFT SL-IGZO TFT S.S. =331 mV/dec V_T = 0.63 V

Fig. 1. (a) Id–Vdand (b) Id–Vgcharacteristics of conventional SL-IGZO TFT device. VTcan be extracted by linear extrapolation from the square root of drain current as a function

of gate voltage. 0 1 2 3 0 100 200 300 400 500 V_G = 2.0 V Bilayer TiO₂-IGZO TFT

Drain Current, I D ( µ A) Drain Voltage, V D (V) -1 0 1 2 10-10 10-9 10-8 10-7 10-6 10-5 10-4

Bilayer TiO₂-IGZO TFT

S.S. = 174 mV/dec V_T = 0.45 V Drain Current, I D (A) Gate Voltage, V D (V)

(a)

(b)

Fig. 2. (a) Id–Vdand (b) Id–Vgcharacteristics of TiO2(15 nm)–IGZO TFT device. VTcan be extracted by linear extrapolation from the square root of drain current as a function of

gate voltage. The inset of (b) is the schematic structure of TFT device.

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channel carriers are dominated by oxygen vacancies in the IGZO active layer and the reaction equation can be expressed as follows: IGZ-Ox+ VIGZ-Ox2+ + 2e ? IGZ-Ox. Here, VIGZ-Ox2+ are the oxygen vacancies in IGZO that influence the channel mobility and off cur-rent. Although oxygen vacancies can be controlled through appro-priate in situ annealing or post-deposition annealing, modifying the compound ratio and oxygen concentration accurately is diffi-cult, especially in the fabrication of a low-temperature and multi-element thin films.

Fig. 2(a) and (b) shows the Id–Vdand Id–Vgcharacteristics of the bilayer TiO2(15 nm)–IGZO TFT. The inset of Fig. 2(b) shows the schematic structure of the bilayer TiO2–IGZO TFT device. Favorable Id–Vdtransistor output characteristics were observed at an even bias and a low VOPof 2 V. Compared with the control SL-IGZO TFT, the bilayer TiO2–IGZO TFT exhibited a low SS of 174 mV/dec-ade, which was much lower than the 331 mV/decade of the control SL-IGZO TFT. This small SS is supported by the low VOPof 2 V and the VTof 0.45 V. To realize the goal of a low-power green transistor, both the dc power and ac switching power (CSVD2f/2) must be reduced[21,22]. Here, CS, VD, and f are the switching capacitance, drain voltage, and operation frequency, respectively. The transistor must be operated using a low VDand VTto lower the AC switching power. Therefore, improving VTand VOPis critical for applying this transistor in large-area displays.

Fig. 3(a) and (b) shows the I–V curves and Id–Vgcharacteristics of the SL-IGZO TFT and the bilayer TiO2(15 nm)–IGZO TFT, respec-tively. The TiO2(15 nm)–IGZO TFT exhibited a considerably lower leakage current than did the SL-IGZO TFT; this result is attributable to the TiO2 semiconductor layer with a high

j

value, which modiﬁed the local ﬁeld effect near the source/drain sides, thereby lowering the channel leakage. By effectively controlling the

channel leakage, the off-current and SS can be greatly improved. Furthermore, the

l

FE was further improved from 3 cm2/V s to 19 cm2_{/V s by using TiO}

2layers of various thicknesses.

The transistor parameters of TiO2–IGZO TFT devices, including the VT, SS,

l

FE, and Ion/Ioffratio, are shown inFig. 4(a) and (b) as a function of TiO2 thickness. Compared with the control SL-IGZO TFT, the TiO2–IGZO TFT featured considerably enhanced perfor-mance, with a low VTof 0.45 V, a small SS of 174 mV/decade, a large

l

FEof 19 cm2/V s, and an Ion/Ioffratio of 1.4 105. Therefore, the use of a TiO2semiconductor layer was proved to improve the transistor characteristics, especially device mobility and gate swing, that are essential to high-speed and high-resolution display applications. 4. Conclusion

A high-performance TiO2–IGZO TFT incorporating a TiO2 semi-conductor layer was demonstrated. The TiO2–IGZO TFT exhibited favorable device integrity, and achieved a low VTof 0.45 V, a small SS of 174 mV/decade, and a high

l

FEof 19 cm2/V s at a low drive voltage of <2 V. Depositing TiO2at a low temperature to improve transistor characteristics differs from other channel modulation approaches such as plasma treatment, which requires a high ther-mal budget, and may be useful in potential applications for high-resolution ﬂexible displays that require a low-temperature process.

Acknowledgment

This work was supported by the National Science Council (NSC) of Taiwan, Republic of China, under Contract No. NSC 102-2221-E-003-019. 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 10-12 10-10 10-8 10-6 10-4 10-2 SL-IGZO TiO₂(8.5nm)-IGZO TiO₂(15nm)-IGZO Current

(

A

)

Voltage (V) -0.5 0.0 0.5 1.0 1.5 2.0 20µ 40µ 60µ 80µ 100µ SL IGZO (µFE=3 cm 2 /Vs) TiO₂(8.5nm)-IGZO (µFE= 15 cm 2 /Vs) TiO₂(15nm)-IGZO (µFE= 19 cm 2 /Vs) Bilayer TiO₂-IGZO TFT

Drain Current, I D (A) Gate Voltage, V G (V)

(a)

(b)

Fig. 3. (a) I–V curves of SL-IGZO and bilayer TiO2–IGZO. (b) Id–Vgcharacteristics of SL-IGZO and TiO2–IGZO TFT devices, respectively.

0.4 0.5 0.6 0.7 0.8 Threshold Voltage, V T (V) V T Suh-threshold Swing, SS (mV/dec) TiO₂Thickness (nm) 50 100 150 200 250 300 350 S.S. 0 2 4 6 8 10 12 14 16 0 0 2 4 6 8 10 12 14 16 5 10 15 20 µFE cm 2 /Vs µFE I ON /I OFF ratio x10 5 TiO 2Thickness (nm) 0.4 0.8 1.2 1.6 ION/IOFF ratio

(a)

(b)

Fig. 4. (a) Threshold voltage, sub-threshold swing, (b) ﬁeld-effect mobility, and Ion/Ioffratio as a function of TiO2thickness for TiO2–IGZO TFT devices.

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