A 110 MHz 84-dB CMOS Programmable Gain Amplifier With Integrated RSSI Function

(1)

A 110-MHz 84-dB CMOS Programmable Gain

Amplifier With Integrated RSSI Function

Chun-Pang Wu and Hen-Wai Tsao

Abstract—This paper describes a CMOS programmable gain

amplifier (PGA) that maintains a 3-dB bandwidth greater than 110 MHz and can provide an 84-dB gain control range with 1-dB step resolution. The PGA can also be operated in a low-power mode with 3-dB bandwidth greater than 71 MHz. Integrated with this PGA is a CMOS successive logarithmic detecting amplifier with a 0.7-dB logarithmic accuracy over an 80-dB dynamic range. It achieves 83-dBm sensitivity and consumes 13 mA from a single 3-V supply in the normal power mode. The chip area, including pads, occupies 1.5 1.5 mm2.

Index Terms—CMOS analog integrated circuits, CMOS RF

transceiver integrated circuits, gain-programming logic, inter-mediate-frequency amplifiers, IF amplifier, programmable gain amplifier, received signal strength indicator (RSSI).

I. INTRODUCTION

A

LTHOUGH zero-IF and low-IF architectures have been used recently in mobile communication handsets to reduce the external component count, superheterodyne architecture, as shown in Fig. 1, continues to be widely used in many other com-munication systems due to its more reliable performance. Signal processing, such as amplifying or filtering, is usually realized at the IF frequency in a superheterodyne system. The circuits will consume less power if most of signal processing is performed at the IF frequency rather than at the RF frequency. Also, dc offset and flicker noise can be ignored if most of the overall system gain is realized at the IF frequency rather than at the baseband. In wireless communication systems, the energy of the re-ceived signal spreads over a wide dynamic range after passing through unpredictable propagation paths, so a programmable gain amplifier (PGA) is usually adopted in the signal chain. In order to adjust the gain of the PGA to the optimal value suitable for subsequent processing, the received signal strength must be measured either at an intermediate frequency or at the base-band, and an automatic gain control function must be realized by feeding back the gain control signal to the PGA according to the measured received signal strength.

The voltage gain of the proposed PGA in this paper can be programmed from 0 to 84 dB in 1-dB steps, which corresponds to a programmable power gain range from 6 to 78 dB with input impedance 50 and output impedance 200 . Together with this PGA, we also designed a received signal strength indi-cator (RSSI) circuit in order to monitor the signal strength at the Manuscript received October 26, 2004; revised February 14, 2005. This work was supported by MediaTek Incorporation, Taiwan.

The authors are with the Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. (e-mail: [email protected]).

Digital Object Identifier 10.1109/JSSC.2005.848023

IF frequency and to use it as an indicator of how to adjust the gain of the system. In addition, the RSSI curve will not change when we adjust the gain of the PGA. The PGA circuit we pro-pose can be used either in the receiving path or the transmitting path, as shown in Fig. 1. In Section II, we describe the circuit architecture of the proposed PGA with RSSI. The circuit de-signs of the fixed gain stages and the fine gain step stage are ex-plained in Sections III and IV, respectively. Section V describes the RSSI circuit and other related considerations. The experi-mental results are shown in Section VI. Finally, a conclusion is drawn in Section VII.

II. CIRCUITARCHITECTURE

In the design of a PGA with nonuniform gain distribution over all gain stages, as shown in Fig. 2(a) [1], accurate gain control can be easily achieved. Integrated RSSI function can also be achieved if a correction factor linked to the gain setting value is adopted. However, the RSSI calibration for different gain set-tings becomes very complicated when high resolution of gain control resolution is needed. Therefore, in such cases, measure-ment of the received signal strength needs to be performed, for example, at the baseband. But then the tracking speed of the au-tomatic gain control loop will be lowered, and hence it is not suitable for fast fading channels. On the other hand, in a PGA with uniform gain distribution over all gain stages, as shown in Fig. 2(b) [2], the RSSI circuit can be easily attached to the PGA circuit. Unfortunately, though, the RSSI curve will not remain the same when the gain of the PGA is adjusted, and a typical family of RSSI curves is shown in Fig. 2(c) [3], [4]. In order to adjust the gain of the PGA according to the measured RSSI, a mapping from the RSSI output to the true signal level is required.

In the proposed design, shown in Fig. 3, we combine the advantages of the PGAs with nonuniform and uniform gain distribution so that excellent gain control and accurate RSSI measurement can be achieved. Furthermore in this design, the RSSI curve will not change like those of the PGA with uniform gain distribution when the gain of the whole PGA is changed. The proposed PGA circuit is composed of six fixed 12-dB gain stages, and one fine gain control PGA stage. With these six fixed gain stages, we can adjust our gain in 12-dB gain steps over a 72-dB range by selecting the input of the gain chain or one of the outputs of the six fixed gain stages, as shown in Fig. 3. Then we further increase the resolution of the whole PGA by amplifying the selected output signal through another PGA with fine gain steps, for instance 1 dB in our design, to cover the 12-dB range. In this way, the overall gain of the PGA is programmable from 0 to 84 dB with 1-dB resolution steps. 0018-9200/$20.00 © 2005 IEEE

(2)

1250 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 6, JUNE 2005

Fig. 1. Block diagram of a typical superheterodyne system.

III. FIXEDGAINAMPLIFIERDESIGN

The gain variation of the fixed gain stages will degrade the performance of the circuit in two aspects. First, the gain setting of the PGA will change as shown in Fig. 4(a) and (b), and the resolution will be lowered. Second, the range and accuracy of the received signal level that can be detected using the RSSI will also be significantly affected, as shown in Fig. 4(c). These curves differ from those shown in Fig. 2(c) because the detector circuits are different. Some techniques, such as using matching components, i.e., N-channel input transistors with N-channel loads in a differential amplifier, can reduce gain variation. But gain control is still needed for the body effect when process vari-ations exist. In our fixed gain stage circuit design, we use sym-metric loads, as described in [8]. This kind of load can be used to reduce the common mode noise and enlarge the linear range of the load. The gain of the single fixed gain stage may vary from 6 to 15 dB, with process variations according to simulation results. In order to reduce the gain variation caused by such process vari-ations, we designed a gain control bias circuit to generate the bias current for our fixed gain amplifiers, as shown in Fig. 5(a). The circuit will compare the actual gain of the fixed gain ampli-fier to an ideal gain value, which is equal to and shown as line D in Fig. 5(b), and then generate the correct bias current to bias the fixed gain amplifiers. The difference between the actual output voltage and the ideal output bias voltage

of the operational amplifier can be shown as

(1) where is the gain of the fixed gain amplifier, and is the voltage gain of the operational amplifier OP in Fig. 5(a). By rearranging (1), we can obtain the gain of the fixed gain stage as

(2) There is a gain offset, i.e., , between the actual gain and the ideal gain , i.e., , but as long as the gain of the operational amplifier is large enough,

(a)

(b)

(c)

Fig. 2. (a) Block diagram of a PGA with nonuniform gain distribution. (b) Block diagram of a PGA with uniform gain distribution. (c) Typical family of RSSI curves of a PGA with uniform gain distribution.

(3)

Fig. 3. Block diagram of the proposed PGA.

the gain will be very close to the ideal value . Though the resistance variation may be rather large in a typical CMOS process, the gain will not change provided that the ratio of the resistors will remain approximately constant. Matching between the resistors is very important, and a resistor layout similar to the interdigitated layout [9] is used in this design. Since the gain control circuit operates at dc, the voltage across the resistor should not be too small as compared to the offset voltage of the replica amplifier. The voltage across the resis-tors should not be too large when we consider the nonlinearity in the replica amplifier or load. In our design, we choose the typical voltage across the resistors as 200 mV so that the load is still in the linear region under this output voltage, even if we assume that resistor variation could be 30%, and the typical voltage across is 50 mV, which means the offset voltage should be smaller than about 2.6 mV to keep the gain error of the fixed gain amplifier within 0.5 dB.

For the fixed gain amplifier in our design, power can be saved by lowering its bandwidth. As shown in Fig. 5(a), the loads of the fixed gain amplifiers are composed of a fixed resistor in par-allel with a voltage-controlled resistor (VCR), which is in the

form of symmetric loads. The gain of the fixed gain amplifier can be shown as given by (3a)–(3c), shown at the bottom of the

page, where and is the channel

length modulation coefficient. In order to determine the max-imum gain of the fixed gain amplifier, we can differentiate (3b) with respect to and it can be shown that the maximum gain occurs when the resistance of the VCR is equal to the resistance of the resistor. This means that the maximum gain occurs when the tail current is , denoted as point B in Fig. 5(b). This gain must be larger than the gain of the fixed gain stages we choose. When the resistance is much lower than the resistance of the VCR, the load resistance is dominated by , so the gain of the fixed gain amplifiers can be en-hanced by increasing the tail current in (3a), shown as zone A in Fig. 5(b). Also, the 3-dB bandwidth of the amplifier is determined by the dominant pole

formed by the load resistance, i.e., , and the capacitance at the output node. When dominates the resis-tance of the load, i.e., is much smaller than , the gain of the fixed gain amplifier can be enlarged by decreasing the tail current of the amplifier according to (3c), shown as

(3a) (3b) (3c)

(4)

(a)

(b)

(c)

Fig. 4. (a) Gain versus Gain control code when the gain of fixed gain amplifiers is larger thanAv(= 12 dB). (b) Gain versus Gain control code when the gain of fixed gain amplifiers is smaller thanAv(= 12 dB). (c) RSSI curves when the gain of fixed gain amplifiers is equal to, larger than, and smaller thanAv(= 12 dB).

zone C in Fig. 5(b). In cases when is much smaller than , the 3-dB bandwidth of the fixed gain amplifier is given by . Since is smaller than , which is a fixed value, we can expect the 3-dB bandwidth to be larger when dominates the load resistance and at the same time, the current consumption is also higher. Therefore, if the IF frequency does not exceed the bandwidth of the PGA in low-power mode, then power can be saved by operating the circuit in this mode, i.e., point E in Fig. 5(b). When the IF

fre-TABLE I

SUMMARY OFGAINSETTING OF THEFINEGAINSTEPPGA

quency is higher, the circuit should be operated in high power mode, which is point F in Fig. 5(b).

IV. FINEGAINSTEPAMPLIFIER

In order to achieve fine gain step adjustment, another PGA with fine gain steps of 1 dB over a 12-dB range is arranged at the end of the signal chain. The circuit of this PGA is shown in Fig. 6. The gain step is determined by the ratio

of the gain control transistors M3 to M4 and M5 to M6. The gain of the PGA from 0 dB to 6 dB can be expressed as

(4) The ratio of to , chosen for the voltage gain setting of the fine gain amplifier from 0 to 6 dB with respect to the minimum gain, is also shown in Table I. For example, the gain achieved by choosing is 1 dB larger than the gain achieved by choosing . To extend the voltage gain range to cover 7 to 12 dB, we can simply apply another 6-dB PGA with the same gain setting in parallel with the former 6-dB PGA, which is also shown in Fig. 6. The change of the total width of gain control transistors M3 and M4 (M5 and M6) should be as small as possible so that the variation of the voltage at point X (point Y) does not significantly affect the of the input tran-sistors M1 and M2. If the variation of the voltage at point X (point Y) is too large, the gain step error will also increase due to the significant variation of of the input transistors M1 and M2. The precision of the resolution within the 6-dB gain control

range depends mainly on the factor of ,

i.e., the matching between the switching transistors M3 and M4. Process variations and variations of environment such as temperature will affect only the gain offset, but not the resolu-tion. We only have to take care of the mismatch between the switching transistors by using layout skills such as interdigi-tated arrays [9] to realize high resolutions. Besides matching between switching transistors, matching between input transis-tors’ transconductances of the two 6-dB PGAs must be taken into consideration for the gain monotonicity of the whole PGA. The gain of the PGA from 7 to 12 dB can be expressed as

(5)

(a)

(b)

Fig. 5. (a) Fixed gain stage and gain control bias circuit. (b) Gain versus gain control voltage.

where the terms with the prime sign denote the same term for the additional PGA, and is the difference between the input transistors’ transconductances of the two 6-dB PGAs. If we

as-sume that the difference between and

is negligible, (4a) can be simplified to

dB

(4b)

In order to keep the gain monotonicity of the whole PGA, the gain error must be controlled to within 0.5 dB, which means should be smaller than 11%. This can be achieved quite easily nowadays in a standard CMOS process. The differ-ential output points are connected to the power supply through two external inductors that can improve the linearity of the PGA, since the output bias voltage is now pulled up to the power

supply. These two inductors and the capacitor between the dif-ferential output nodes also provide the bandpass filtering and impedance matching functions.

V. RSSI CIRCUIT, OFFSETCANCELLATIONCIRCUIT,AND OTHERCONSIDERATIONS

The operation of the RSSI circuit is shown in Fig. 7(a) [5]. When the signal saturates, for example, the third stage of the am-plifier chain, the detectors after this stage source no current, the detectors before this stage source current , and the detector of the third stage sources a variable current according the V–I curve of the detector. The total sourcing current and the resistor determine the output RSSI voltage. The detector circuit is shown in Fig. 7(b) [6], and the output current can be ex-pressed as shown in the equation at the bottom of the next page, where is the width ratio of the two input transistor pairs, as shown in Fig. 7(b). Simulation has demonstrated that such a de-tector circuit can function well in spite of the process variations.

(6)

Fig. 6. Fine gain step PGA amplifier.

The coarse gain step adjusting circuit must be designed care-fully to prevent reverse signal coupling from the output of the last stage of the fixed gain amplifier chain, either through the fixed gain output selecting circuit or the substrate; otherwise, the circuit may oscillate due to positive feedback. In the fixed gain output selecting circuit, coupling from gate to drain could be eliminated by cascading two stages or putting one more switch transistor between the output and the drain of the input tran-sistor. Double guard rings are used to prevent substrate coupling in the circuit layout. Because the gain of the amplifier chain is quite high (72 dB), any circuit mismatch will cause significant offset and may even saturate the output of the amplifier chain. To avoid this, an offset cancellation scheme must be adopted. The offset cancellation circuit, shown in Fig. 8, measures the output offset level and compensates for the offset voltage by

feeding back this signal to an auxiliary amplifier accompanying the first fixed gain stage. The offset cancellation circuit can still work even if the last stage is clipping, because the input referred dc offset value will slightly change the duty cycle of the output clipping signal, and the filtered output offset value can be used for offset cancellation. This circuit is also widely used in the de-sign of limiting amplifiers. The amplifier chain with the offset cancellation circuit will have a minimum operating frequency, and this can be set by changing of the offset cancellation circuit and the capacitor. The first fixed gain stage must also be designed carefully because the auxiliary amplifier’s bias cur-rent will lower the resistance of the VCR at the output of the first fixed gain stage. Thus we have to design the first fixed gain stage with a slightly higher gain to accommodate the gain re-duction caused by the auxiliary amplifier.

(5a) (5b) (5c)

(7)

(a)

(b) Fig. 7. (a) Architecture of the RSSI circuit. (b) One of the detector circuits of the RSSI.

The output of the fixed gain stage that is chosen to be the input of the fine gain control stage has a swing ranging from 50 to 200 mV. Thus, a fixed gain stage is considered as saturated when its output exceeds 200 mV, and the rectifiers should be designed according to this operating range. However, the fol-lowing saturated fixed gain stages will be used by the RSSI cir-cuit only, but not the whole PGA signal chain, so these saturated fixed gain stages can be turned off without affecting the inte-grated RSSI function only if we also turn off the current of the saturated rectifiers (this is not realized in this chip), because the rectifier output current goes to zero when its input saturates. So in the presence of larger signals, we can prevent the last ampli-fier stages from clipping. However, this will break the loop of the offset cancellation circuit, so the offset cancellation circuit should be modified, for example, by turning on these saturated stages when the PGA is not in the operation mode in a TDMA system or using some feedback schemes like a dynamic mode feedback circuit. In another way, if we just lower the gain of the following saturated fixed gain stages, i.e., like unity gain buffers,

and still turn off the current of the saturated rectifiers, the offset cancellation circuit still maintains its function.

VI. EXPERIMENTALRESULTS

The IF amplifier we proposed [7] has been fabricated in a 0.35- m one-poly four–metal (1P4M) CMOS process. The ca-pacitors used for frequency compensation in the operational am-plifier for the bias circuit of the fixed gain stages are realized using MOS capacitors. The gain programming logic circuit and RSSI circuit are also integrated with the IF amplifier. The test chip is directly bonded to a PCB surrounded with the required external components. The programmable power gain range of the whole PGA is from 7.78 to 79.79 dB in normal operation mode (at 110 MHz) and 7.79 to 80.03 dB in low-power oper-ation mode (at 71 MHz), as shown in Fig. 9. It has been found that the peaks of gain step error occur every 12 dB because of the 12-dB gain of the fixed gain stages. The gain step error is kept within 0.4 dB when the test chip is operated in either normal

(8)

Fig. 8. Schematics of offset cancellation circuit.

Fig. 9. IF amplifier power gain and gain error.

Fig. 10. RSSI output and RSSI error.

or low-power mode. The input impedance is a 50- external re-sistor across the input tranre-sistor gates, and the output impedance

Fig. 11. IF amplifier OCP and IP3.

is a 200- on chip resistor. In Fig. 10, it is shown that the mea-sured RSSI accuracy is 0.7 dB, with the input signal varying from 83 to 3 dBm. The accuracy of the voltage meter used for measuring the RSSI circuit is 10 mV, which corresponds to an error of about 0.6 dB. The measured output 1-dB compres-sion point is 4 dBV, and the third order output intercept point is 10.6 dBV, as shown in Fig. 11. The IC consumes 13 mA from 3 V when operated in normal mode and 5 mA from 3 V when operated in low-power mode. The chip micrograph is shown in Fig. 12. The chip area, including pads, occupies 1.5 1.5 mm . Table II summarizes the key measured performances and pre-vious works.

VII. CONCLUSION

In this paper, we developed a 110-MHz 84-dB programmable gain amplifier using standard CMOS technology. Despite the process variations, excellent performance can be maintained by using the gain controlled bias circuit. The programmable gain amplifier can operate at a minimal input signal of 83 dBm.

(9)

Fig. 12. Chip micrograph.

TABLE II

(10)

High gain step accuracy ( 0.4 dB) with 1-dB resolution was also achieved by this amplifier. In addition, power can be saved under the low-power mode when the IF frequency of the input signal is smaller than 74 MHz.

ACKNOWLEDGMENT

The authors would like to thank National Chip Implementa-tion Center for chip implementaImplementa-tion.

REFERENCES

[1] F. Piazza et al., “A 2 mA/3 V 71 MHz IF amplifier in 0.4m CMOS programmable over 80 dB range,” in IEEE ISSCC Dig. Tech. Papers, Feb. 1997, pp. 78–79.

[2] RF2903 Integrated Spread Spectrum Receiver, Data Sheet, RF Micro Devices, Greensboro, NC, 1999.

[3] TA0024 RF2903: A highly integrated receiver IC for spread spectrum

applications, RF Micro Devices, Greensboro, NC.

[4] C. W. Chang, “The simulation, design, implementation, and testing of W-CDMA receiver compatible with IMT-2000,” Masters thesis, Na-tional Taiwan Univ., R.O.C., Jun. 2000.

[5] E. Nash, Logarithmic Amplifier Explained, Analog Dialogue 33-3. Norwood, MA: Analog Devices Inc., 1999.

[6] K. Kimura, “A CMOS logarithmic IF amplifier with unbalanced source-coupled pairs,” IEEE J. Solid-State Circuits, vol. 28, no. 1, pp. 78–83, Jan. 1993.

[7] C.-P. Wu and H.-W. Tsao, “A 110 MHz 84 dB CMOS programmable gain amplifier with RSSI,” in Proc. IEEE RFIC Symp., Jun. 2003, pp. 639–642.

[8] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723–1732, Nov. 1996.

[9] A. Hastings, The Art of Analog Layout. Englewood Cliffs, NJ: Pren-tice-Hall, 2001.

[10] S. Tadjpour, F. Behbahani, and A. A. Abidi, “A CMOS variable gain amplifier for a wideband wireless receiver,” in IEEE Symp. VLSI Circuit

Dig. Tech. Papers, 1998, pp. 86–89.

Chun-Pang Wu was born in Kaohshiung, Taiwan,

R.O.C., on March 10, 1975. He received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1998. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering and Graduate Institute of Electronics Engineering at National Taiwan University.

His research interests are PLL, DLL, and building blocks for wireless communication systems.

Hen-Wai Tsao received the B.S., the M.S., and

Ph.D. degrees in electrical engineering from Na-tional Taiwan University, Taipei, Taiwan, R.O.C., in 1971, 1975, and 1985, respectively.

Since 1978, he has been with the Department of Electrical Engineering, National Taiwan Univer-sity, where he is currently a Professor. His main research interests are optical fiber communication system, communication electronics, and electronic Instrumentation.