Single-Inductor Multi-Output (SIMO) DC-DC Converters With High Light-Load Efficiency and Minimized Cross-Regulation for Portable Devices

ductor multiple-output (SIMO) DC-DC converter with hysteresis mode is proposed. It includes multiple buck and boost output voltages. Owing to the adaptive adjustment of the load-depen-dant peak-current control technique and the hysteresis mode, the cross-regulation can be minimized. Furthermore, a new delta-voltage generator can automatically switch the operating mode from pulse width modulation (PWM) mode to hysteresis mode, thereby avoiding inductor current accumulation when the total power of the buck output terminals is larger than that of the boost output terminals. The proposed SIMO DC-DC con-verter was fabricated in TSMC 0.25 m 2P5M technology. The experimental results show high conversion efficiency at light loads and small cross-regulation within 0.35%. The power conversion efficiency varies from 80% at light loads to 93% at heavy loads.

Index Terms—Cross-regulation, single-inductor multi-output

(SIMO) DC-DC converter, SoC system.

I. INTRODUCTION

T

ODAY’S power management units of portable products require high power conversion efficiency, fast line/load transient response, and small power module volume. In par-ticular, cell phones, digital cameras, MP3 players, PDAs, and portable products require varied voltage/current levels of power supplies for delivery to different sub-modules in portable products. Thus, there are different designs that provide different voltage/current levels as shown in Fig. 1. Low dropout (LDO) regulator arrays are one of the designs for different voltage/current levels as depicted in Fig. 1(a), where the index is from 1 to which is used to index the th output. However, LDO regulator arrays sacrifice power conversion efficiency and greatly reduce battery life. The other solution is illustrated in Fig. 1(b), which combines with different inductive switching converters. The high power conversion efficiency is ensured by the inductive switching converter. However, the large number of inductors occupies the large footprint area and increase fabrication cost. To achieve microminiaturization and high power conversion efficiency for a power management unit, the single inductor multiple output (SIMO) DC-DC converter has been developed as a suitable solution. The conceptual

Manuscript received September 03, 2008; revised October 23, 2008. Current version published March 25, 2009.

The authors are with the Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu City, Taiwan (e-mail: khchen@cn. nctu.edu.tw).

Digital Object Identifier 10.1109/JSSC.2009.2014726

one inductor component to generate multiple voltage/current levels for different sub-modules in the portable products. The SIMO DC-DC converter not only reduces the footprint area and fabrication cost but also provides highly power conversion efficiency [1]. However, all load current conditions of the mul-tiple output terminals arise in the current level of the inductor. When the load current condition of each output accumulates in the same inductor, the design challenges of the SIMO DC-DC converter such as cross-regulation, power conversion efficiency, system stability, and lack of flexibility of both the buck and boost must be seriously addressed. Thus, several topologies and control techniques have been proposed to implement SIMO DC-DC converters [2]–[13]. The SIMO DC-DC converter in [1] uses the peak current control method and state machine to regulate output voltage. The work in [2] proposed the charge control method and divided one period to regulate the multiple output voltages. Due to the high freewheeling current level, the power conversion efficiency is greatly decreased in light load condition. The works in [3] and [10] calculate the cross-reg-ulation problem when one period is divided to regulate the multiple boost output voltages. Moreover, the work in [10] proposed the pseudo-continuous conduction mode (PCCM) which involves the advantages of continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The works in [4]–[8], and [12] show time multiplexing (TM) tech-niques to regulate the multiple output voltages and to reduce cross-regulation. The works in [11] are proposed to monitor freewheeling current as the inductor current control method for dual boost output voltages. The work in [13] orders the power distribution of four boost output voltages. Its first three output voltages are controlled using comparators and are thus called comparator-controlled output voltages, while the last-ordered output is P-I controlled with an error amplifier. However, the flexibility of the buck and boost output voltages is limited by the structure of the converter and control methodology. Thus, to simultaneously generate buck and boost output voltages, the previous works in [2] proposed the charge control method and used minimum switches to provide one buck and one boost output voltage. The SIMO DC-DC converter which uses minimum switches is going to cause charge accumulation in the inductor during unbalanced output loads. Thus, this paper studies previous design problems and applies extended solu-tions to a study case. A load-dependant peak-current control SIMO DC-DC converter with hysteresis mode is proposed to provide multiple buck and boost output voltages and to solve

Fig. 1. Different power management designs. (a) Use of many LDO regulators. (b) Use of many switching converters. (c) Use of a single-inductor and multiple-output converter.

Fig. 2. Conventional SIDO DC-DC converter with one buck and one boost output in [2], and [12].

the challenges of cross-regulation, power conversion efficiency, and system stability [9].

The organization of this paper is as follows. Section II de-scribes the minimum switch methodology of the SIMO DC-DC converter with the load-dependent peak-current control tech-nique in order to improve cross-regulation and light load ef-ficiency. Section III describes the implementation of the pro-posed SIMO DC-DC converter. Section IV presents the power comparator and delta-voltage generators to smoothly switch the operating mode between the PWM and hysteresis modes. In Section V, the experimental results show the minimized cross-regulation and performance of the proposed SIMO DC-DC con-verter. Finally, the conclusion is made in Section VI.

II. MINIMUMSWITCHNUMBERSTRUCTUREWITH THE

LOAD-DEPENDANTPEAK-CURRENTCONTROLTECHNIQUE

A. Controlling Sequence Used to Minimize the Number of Switches

Fig. 2 shows the topology of a conventional single inductor dual output (SIDO) DCDC converter with buck and boost output voltages [2] and [12]. Five kinds of inductor current path are

used to regulate the output voltages during one switching cycle. Paths 1 and 2 provide the charge to the buck output . Paths 3 and 4 deliver the charge to the boost output . Path 6 is used to hold the charge in the inductor and to function as a freewheeling current loop. As in previous works, the min-imum number of power switches is shown in [10], [11], and [13]. These works generated the boost output voltages and con-trolled the storage charge of the inductor in order to regulate the output voltage during one switching cycle. Thus, to minimize the number of power switches in the SIMO DC-DC converter, the dual boost output terminals converter as shown in Fig. 3 is going to generate one buck and one boost output voltage [2]. According to the operation of conventional SIDO DC-DC con-verter, paths 1, 3, and 4 must be kept in the structure. Path 1 is the only one path to deliver charge to the buck output. Path 3 is the only choice to store charge in the inductor with a large cur-rent slope, and path 4 is the only path to deliver charge to the boost output. Furthermore, the buck output voltage can only be regulated by path 1. Thus, path 2 can be removed. This means the switches and in Fig. 2 are removed for a minimum number of power switches. After the removal of path 2, a switch

Fig. 3. Topology of minimum number of switches in [2] with one buck and one boost output voltage, and the proposed controlling sequence and path 0 of the hysteresis mode.

Fig. 4. Comparison of two topologies with four switches to implement the SIDO DC-DC converter. (a) The previous proposed controlling Sequence-I in [2]. (b) The proposed Sequence-II with the load-dependant peak current control technique.

A previous controlling sequence-I is depicted for one buck and one boost output in Fig. 4(a) [2]. At the beginning of each switching cycle, path 3 in Fig. 3 stores the charge of the inductor from the freewheeling current level to the pre-defined and fixed current level . Then path 1 is selected to deliver charge to the buck output, and the inductor current level is increased to the value , which is dependent on the load condition of the buck output at the same time. After buck output operation, the boost output draws the charge from path 4, and the inductor current drops back to . Finally, the current level of the inductor is kept by path 6. The inefficient performance is the major disadvantage since the inductor current is increased to a highly undesired value if the buck output is derived during heavy load condition. The other drawback is the pre-defined and fixed that contribute to the highly freewheeling current level and the serious decrease in power conversion efficiency in the light-load condition. The highly undesired current value of the inductor also causes the serious cross-regulation in the output voltages. As a result, there is difficulty in ensuring the conversion efficiency and minimum cross-regulation of the con-trolling sequence-I. Furthermore, when the load condition of the buck output is larger than that of the boost output in the

struc-ture of Fig. 3, the storage charge of the inductor accumulates without a releasing path. The highly current level appears in the inductor and results in unregulation. To address these issues, a new controlling sequence-II with the load-dependent peak-cur-rent control technique is presented as illustrated in Fig. 4(b). In the beginning of controlling sequence-II, path 1 is used to simul-taneously regulate the buck output voltage and store the charge in the inductor. After path 1, the inductor current is rapidly in-creased to the load-dependant peak-current control level by path 3. Then controlling sequence-II switches to path 4 to draw the charge of the inductor to boost the output; after which, it drops back to the current level of the inductor to . Finally, the current level of the inductor is kept by path 6. Since the cur-rent level increases during heavy load condition and de-creases during light load condition, the power losses during the freewheeling loop can be minimized. Due to the storage charge of the inductor in path 1 having been fully taken into account in controlling sequence-II, the highly undesired value is eliminated. Thus, power conversion efficiency and cross-regu-lation can be improved. In addition, a hysteresis control mode has been proposed to eliminate the unregulation during the un-balanced load condition in the next section.

Fig. 5. Scenarios of different operation modes when the load current changes from light to heavy. (a) DCM; (b) CCM; (c) fixedI PCCM; (d) the load dependent peak current control technique.

B. Load-Dependent Peak-Current Control for Improving Light-Load Efficiency and Reduction of Cross-Regulation

The inductor waveform represents the status of storage charge and the order of the system. Four inductor current waveforms are depicted in Fig. 5. At first, the inductor current waveform of the operation of DCM is shown in Fig. 5(a). The order of the system is equal to one, and one low-frequency pole exists in the closed loop. When the power is larger than the maximum power limitation of DCM, the inductor current will switch to CCM operation as shown in Fig. 5(b). The order of the system becomes two and thus the compensation of the system needs a complicated method like a proportional-integral-differential (PID) compensator to ensure large low-frequency gain and a suitable phase margin. The PCCM operation was proposed to address the disadvantages in DCM or CCM operation [3] and [10], [11]. The PCCM technique sets a fixed inductor current DC level to store enough energy in the inductor as depicted in Fig. 5(c). Thus, the order of the system is similar to that in DCM operation, while the maximum power delivered by the operation of PCCM is larger than that in DCM operation. This simplifies the compensation scheme. Once the disappearance of the free-wheeling stage happens when the load current exceeds the max-imum power limitation or when a sudden load current rises from light to heavy, the stability and minimized cross-regulation are not guaranteed since the order of the system becomes two. As illustrated in Fig. 5(d), the load-dependent peak-current control technique is proposed to adaptively store suitable charge in the inductor. When the load current becomes small, the peak cur-rent level will be decreased to a small curcur-rent level to ensure high power conversion efficiency at light loads. Furthermore, a minimum peak inductor current is defined to prevent the output from having a too large transient dip voltage.

III. THEIMPLEMENTATION OF THEPROPOSEDSIMO DC-DC CONVERTER

According to the proposed controlling sequence-II and the load-dependent peak-current control technique, the architecture of the proposed SIMO DC-DC converter is illustrated in Fig. 6. The following sub-sections describe the details of the sub-mod-ules.

A. Load-Dependent Peak-Current Decision Circuit

To improve the power conversion efficiency at light loads and to reduce the effect of cross-regulation, a peak current decision circuit is depicted in Fig. 7. All output voltages of the error am-plifiers are converted current signals by the V-I converters. Each V-I converter outputs two current output signals with a conver-sion ratio . The current signals

and (the index is 1 to ) are used to work as discharging currents of the charge reservation circuit. The other current signals are summed to generate the load-dependent peak-current , which varies with load currents. Furthermore, to avoid the zero inductor peak current, a min-imum peak inductor current is set by a current source . The non-inverting input of the comparator is decided by the voltage signal , which is generated by flowing two cur-rent signals and through the resistor

. The value of is determined by

(1) The input voltages of the V-I converters are

and from the error amplifier array that indicates the load conditions of all multiple buck and boost output termi-nals. For a dip in one of the output terminals due to an increase in load current, for example, the control system increases the duty ratio, which in turn indirectly causes an increased peak inductor current. The energy stored in the inductor is gradually increased to minimize cross-regulation due to the load-dependant peak in-ductor current level at heavy loads. Similarly, the period of free-wheel stage occupies little duration of every switching cycle. The order of the system is still kept as one, and the power dissi-pation is always kept small. Therefore, the proportional-integral (PI) compensator can ensure the stability of the system, and the heavy-load power conversion efficiency can be kept high.

B. The Current Sensor and Charge Reservation Circuits

The current sensor shown in the left side of Fig. 8 [2] and [3] has register which is times of the sensing resistor . To achieve the load-dependant peak-current control technique, the current sensor cannot be turned off during the whole switching cycle. Thus, the freewheeling power MOSFET as illustrated in Fig. 6 is connected between the input power

Fig. 6. The proposed load-dependent peak current control SIMO DC-DC converter with hysteresis mode for high power conversion efficiency and minimum cross-regulation.

source and the node at the expense of power conversion efficiency during the freewheeling stage. The architecture of the charge reservation circuit is shown in the right side of Fig. 8. The sensing current is converted to the voltage ,

which is sent to compare with the peak current level as illustrated in Fig. 6. The sensing current is also used to deter-mine the individual duty cycle of each buck or boost output. Thus, there are charge monitoring circuits in the charge

Fig. 7. The load-dependent peak current control circuit dynamically adjusts the peak current level according to the value of the load current.

reservation circuit. The internal capacitors and are used to monitor the buck and boost output voltages, respectively. The charge monitoring circuit in the sub-block is also shown in Fig. 8. When the voltage of is low, flows into capacitor to indicate the energy delivering condition of one of buck or boost output voltage. Once the voltage changes from low to high, the dis-charging current , which comes from the load-dependence peak-current control circuit, starts to discharge capacitor . Thus, the values of and

on and can monitor the status of the buck and boost output voltages. As a result, the duty cycle can be determined by voltage on the capacitor and the feedback voltage (or ) after the operation of the comparator in Fig. 6.

Assume that the value of (or ) is (or ) times that of (or ) for the buck (or boost) output

, and the index is 1 to . The values of and are set within the input common mode range of the comparator array in Fig. 6. Since the value of is times that of , the values of internal capacitors (or ) in the charge reservation circuit are (or ) times that of (or ), respectively. To generate the discharging current , which comes from the load-dependence peak current control circuit in Fig. 7, the values of resistor and are described as (2) for the buck output and for the boost output .

(2) and (or ) are the transconductance of the error ampli-fier and the ratio of the voltage divider, respectively. The values of the resistors and ensure that the discharging cur-rents are proportional to the load current. The values of the dis-charging currents are expressed as (3) for buck output and boost output , respectively.

(3) The charge stored on internal capacitor or can effectively represent the regulated output voltage at the buck or boost output terminal. Thus, the proposed charge reservation circuit can accurately decide the duty cycle of the buck or boost output terminals.

C. Logic Control Circuit With Automatic Mode Switch to Avoid Instability

The control logic generator with mode switch controller is depicted in Fig. 9. The operation of the control logic is divided into four durations (paths 1, 3, 4, and 5), which stand for the four energy delivering paths in Fig. 4(b). At the beginning of path 1, the clock signal is triggered by positive edge, and its duty cycle is 90%. During Path 1, the energy is delivered to the multiple buck output terminals in Fig. 3. The input signal ( is 1 to ) is from one of the output voltages of the comparator array in Fig. 6, which decides the duty cycle of buck output . At the same time, the inductor current is also increased. Once the signal changes to a low level when the value of is larger than that of in Fig. 6, path 3 starts to ensure sufficient energy to be stored in the inductor. In path 3, the signal in (1) and the value of in Fig. 8 are used to determine the duty cycle of for increasing the inductor current to the level until the value of is large than that of .

However, the duty cycle of may be zero if the inductor current is increased to exceed the level during path 1. This means that the inductor current level is high enough to provide sufficient energy to the multiple boost output terminals after path 1. There is no need to store more charge in the inductor since it may cause current accumulation in Fig. 10. Once the value of is large than that of , changes to a low level. Path 4 starts to deliver energy to the multiple boost output terminals. At the same time, the inductor current is decreased according to the load condition of the boost output voltages. Once is changed to a low level by the comparator array when the value of is larger than that of , the energy delivery to the multiple boost output terminals is completed. Then the controlling sequence enters path 6 named as freewheeling stage. That is, the energy is reserved in the inductor. The longer the period of the freewheeling stage is, the lower the conversion efficiency. Owing to the adjustment of the inductor peak current, the inductor current level at the freewheeling stage is kept at a low level and thus the conduction loss can be reduced at light loads. All the output signals , , , and of the control logic generator are converted by the driver and the dead-time controller block shown in Fig. 6 to the gate control signals , ,

, and , which are used to control the power MOSFET switches , , , and .

As illustrated in Fig. 10, current accumulation occurs when the power of the buck output terminals is larger than that of the boost output terminals. The accumulated current causes serious cross-regulation and poor conversion efficiency at light loads. To address this problem, it is important to provide a hysteresis mode to alleviate the instability. In Fig. 3, at the hysteresis mode, path 1 is changed to path 0 to force the current to flow through switch to the buck output terminals. The energy of the buck output terminals does not cause current accumulation in the inductor. Thus, the converter works as a hysteresis buck con-verter, and the output voltage is directly regulated and limited

Fig. 8. The current sensor [2] and [3], charge reservation circuits, and the charge monitoring circuit for reducing output ripple.

Fig. 9. The control logic generator with the mode switch controller.

Fig. 10. Timing diagram of the transition from the PWM mode to the hysteresis mode.

by a hysteresis window. The control signal and inductor cur-rent waveform as depicted in Fig. 10 show the transition from the PWM mode to the hysteresis mode. To achieve the hys-teresis control mode, a mode switch, a power comparator, and a novel delta-voltage generator are proposed. The mode switch as shown in the sub-block of Fig. 9 is composed of only one AND gate, and the signal “ ” is kept at a high level during the PWM operation until the signal “ ” that comes from the power comparator circuit is changed to a low level. Then the opera-tion of the buck output is switched to the hysteresis mode. Since path 6 directly connects the buck output to the power supply, the

output ripple is slightly increased for ensuring system stability during hysteresis mode.

IV. POWERCOMPARATOR ANDDELTA-VOLTAGEGENERATOR

To smoothly switch between two operation modes, the power comparator and delta-voltage generators are proposed to decide the operation mode of the converter.

A. Power Comparator Circuit

The inductor current waveform as depicted in Fig. 11 pre-cisely describes the boundary condition between the PWM and

Fig. 11. The boundary waveform of the hysteresis control mode.

Fig. 12. The power comparator circuit.

hysteresis modes. Assume that the slopes of the inductor current for the buck and boost output terminals are expressed as (4). The operation modes and boundary condition can be determined by (5) and (7).

(4)

(5)

Fig. 13. (a) The power decision circuit for multiple buck output voltages. (b) The power decision circuit for multiple boost output voltages. (c) The differential transconductance amplifier for the generation of the inductor current slope.

(7) In Fig. 12, the power comparator is used to decide which one of the multiple buck output terminals needs to enter hysteresis operation according to the largest load current. The summation current and indicate the slope values of the multiple buck and boost output terminals, respectively. is used to discharge capacitor during the buck operation, and is used to charge capacitor during boost operation. At the free-wheeling stage, the sample and hold (S/H) circuit sample the voltage on capacitor and hold it on the capacitor . Thus, the boundary condition is monitored.

In the PWM mode, is smaller than , and is set to a low level in the first loop. The output signals

of registers are set to a low level to disable the mode switch of Fig. 9. Thus, the mirrored current signals sum up in , and all mirrored current sig-nals of the delta-voltage generator for buck are separately switched to detect the maximum slope by the current comparators in Fig. 12. In the meanwhile, the generated is compared with and outputs the low state of in

Fig. 14. Micrograph of the proposed SIMO converter, with the chip size being 18003 2100 m .

the second loop. This second loop is designed to detect the op-erating mode of each buck output according to the buck output with the largest load current selected for hysteresis mode. When the is low, the trigger signals of are in-hibited by and the output of delay circuit. The delay circuit is enabled to avoid the oscillation of the second loop and

Fig. 15. The inductor current controlling sequence measured waveform with heavy loads.

Fig. 16. The cross-regulation statistic chart of the SIMO DC-DC converter. (a) The cross-regulation at the buck outputV in the PWM and hysteresis modes. (b) The cross-regulation at the boost outputV in the PWM and hysteresis modes.

to ensure the storage charge in the steady state when one of the buck output terminals enters hysteresis mode.

When the loads of the buck output terminals are larger than those of boost the output terminals, and become high. flow into the current comparator and generate the detecting codes during the period of delay circuit. The code is converted by (8) to indicate which one of the buck output terminals has the maximum loads and needs to operate in hysteresis mode.

(8) where the index is from 1 to . Once one of the buck output terminals is selected, triggers to set the signal to a low level. Moreover, the in-verse of inhibits the related current signals and . As a result, can be expressed as , where the index is used to indicate the operating times of the second loop. and are the current signals by the operation of the second loop according to the priority

of loads. Once is smaller than , is set back to low. That is, the charge detection process is ended, and the proposed converter can really avoid the current accumulation and minimize the output ripples of the buck output terminals in hysteresis mode. The hysteresis mode can operate until is smaller than . is set to low, and the hysteresis mode is switched to PWM mode.

B. Delta-Voltage Generator

The novel delta-voltage generator is proposed in Fig. 13 to generate the different inductor current slopes for the smooth switching between the hysteresis and PWM modes. For the buck output terminals, the amplifier with multiple output voltages in-cluding , is depicted in Fig. 13(a). The block of the cancellation is used to remove the term in the difference voltage between and . The amplifier with multiple output voltages is used to generate the interme-diate values and from (9) to (10).

(9)

Fig. 17. The line and load regulation statistic charts. (a) The buck output voltage operates in the PWM mode when the boost output voltage operates at heavy loads. (b) The buck output voltage operates in hysteresis mode when the boost output voltage operates at light loads. (c) The boost output voltage in the PWM mode when the buck output voltage operates at light loads. (d) The boost output voltage in the hysteresis mode when the buck output voltage operates at heavy loads.

Similarly, for the multiple boost output terminals, the amplifier with multiple output voltages as shown in Fig. 13(b) can gen-erate intermediate values and from (11) to (12).

(11)

(12) The current slope of the buck output is derived as (13). The inductor current slope of the boost output is derived as (14).

(13) (14) (13) and (14) are implemented by the differential transconduc-tance amplifier, which is illustrated in Fig. 13(c). and are connected to the output of the delta-voltage generator. All

of output voltages and are sent to the input volt-ages of the power comparator circuit in Fig. 12. Therefore, the smooth transition between the PWM and hysteresis modes can be determined.

V. MEASUREMENTRESULTS

The proposed SIMO DC-DC converter with the load-de-pendent peak-current control technique was implemented in TSMC 0.25 m 2P5M technology. The micrograph of the SIMO DC-DC converter with 4 output terminals is shown in Fig. 14. The supply voltage is 1.8 V. The pre-defined output voltages are 1.25 V and 1.35 V for the two buck output volt-ages and 2.0 V and 2.25 V for the two boost output voltvolt-ages, respectively. The measured inductor current waveform of the PWM mode at heavy loads is shown in Fig. 15. The ac coupling measurement of clearly shows the controlling sequence-II in the inductor current, which is similar to the description in the previous section as illustrated in Fig. 4(b). Since large information was measured, the statistic chart is used to describe the performance of the proposed converter. The cross-regulation charts of the buck and boost output voltages are shown in Fig. 16(a) and (b), respectively. In Fig. 16(a), the load current of 50 mA is added to the boost output terminals in

Fig. 18. (a) The output ripples estimation of buck output in the SIMO converter. (b) The output ripples estimation of boost output in the SIMO converter. TABLE I

SUMMARY OF THEPERFORMANCE

order to show the cross-regulation of different operation modes. This indicates that the hysteresis mode increases the cross-reg-ulation from 0.07% to 0.22%. Similarly, the cross-regcross-reg-ulation of the boost output is shown in Fig. 16(b). It is slightly increased from 0.05% to 0.35% in the hysteresis mode. It is smaller than the value of 0.79% in the literature [1].

The line-and load-regulation charts of the buck output in PWM and hysteresis modes are shown in Fig. 17(a) and (b). In the PWM mode, the boost converter is operated at heavy loads. Contrarily, in the hysteresis mode, the boost converter is operated at light loads. The line-regulations of the buck output voltages are smaller than 0.8%/V, and the load-regulations of the buck output voltages are smaller than 2% in the two oper-ating modes. Fig. 17(c) and (d) show the boost output voltages in the PWM and hysteresis modes. The results depict that the line-and load-regulations between the two modes are similar. The load-regulations of the boost output voltages are smaller than 1%, and the line-regulations of the boost output voltages are smaller than 0.5%/V. The output ripples of the buck and boost output voltages are depicted in Fig. 18(a) and (b). In the

PWM mode, the output ripple is controlled by the values of the inductor and output capacitor, and thus the value is smaller than 4 mV . In the hysteresis mode, the output ripple of the buck output voltages is increased to 22 mV , and the output ripple of the boost output voltages is increased to 6 mV . The power conversion efficiency is shown in Fig. 19. The PWM operation with load-dependent peak-current control has improved highly power conversion efficiency from 85% to 93%. In the hysteresis mode, due to the energy delivering path without flowing through the inductor, the conversion efficiency drops to 80% 85%. The performance of the SIMO DC-DC converter is summarized in Table I.

VI. CONCLUSION

This paper proposes a compact-sized and highly efficient SIMO DC-DC converter for a portable device. The new proposed SIMO DC-DC converter with minimized switch tran-sistors utilizes only a single inductor to provide multiple buck and multiple boost output voltages. The energy stored in the inductor can be effectively delivered to the buck or boost output

Fig. 19. Power conversion efficiency of the SIMO DC-DC converter with the load-dependant peak current technique.

without inductor current accumulation. In other words, the proposed hysteresis mode operation and the new delta-voltage generator correct the current accumulation. Thus, the proposed SIMO DC-DC converter not only provides multiple output sources but also minimizes cross-regulation within 0.35%. Furthermore, owing to the load-dependant peak current tech-nique, the SIMO DC-DC converter achieves high conversion efficiency from 80% at light load condition to 93% at heavy load condition in the experimental results.

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Ming-Hsin Huang graduated from the Department

of Electronics of Municipal Kaohsiung Senior Vo-cational Industrial High School, Kaohsiung, Taiwan, and received a gold medal in industrial electronics from the 27th National Skills Competition in Taiwan. He received the B.S. degree in the Electronic group of the Department of Industrial Education and Technology, National Changhua University of Ed-ucation, Taiwan, in 2000, and the M.S. degree from the Department of Electrical Engineering, National Changhua University of Education, in 2002. He is currently pursuing the Ph.D. degree in the Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan. His current research interests include power ICs, LED drivers and backlights, switching power supplies, and PWM control ICs.

Ke-Horng Chen (M’04) received the B.S., M.S.,

and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1994, 1996, and 2003, respectively.

He is an Associate Professor in the Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan. He organized a mixed-signal and power management IC laboratory in National Chiao Tung University. He was a part-time IC designer with Philips in Taipei from 1996 to 1998. He was an application engineer with Avanti, Ltd. in Taiwan from 1998 to 2000. From 2000 to 2003, he was a project manager with ACARD, Ltd., where he worked on the designs of the power management IC. His current research interests include power management IC, mixed-signal circuit designs, display algorithms and driver designs of LCD TV, RGB color sequential backlight designs for OCB panels, and low-voltage circuit designs. He has published more than 25 papers in journals and conferences, and also holds several patents.