Investigation of source-follower type analog buffer using
low temperature poly-Si TFTs
Bo-Ting Chen
a,*, Ya-Hsiang Tai
b, Ying-Jyun Wei
a, Kai-Fang Wei
a, Chun-Chien Tsai
a,
Chun-Yao Huang
c, Yu-Ju Kuo
d, Huang-Chung Cheng
aaDepartment of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan, ROC bDepartment of Photonics and Display Institute, National Chiao Tung University, Hsinchu 300, Taiwan
cDepartment of Panel Design, R&D Design Division, Central Research Institute, Chunghwa Picture Tubes, Ltd, Taiwan dDepartment of Array Cell Design, LCD Product Technology Division, AU Optronics Corporation, Hsinchu 300, Taiwan
Received 3 March 2006; received in revised form 6 September 2006; accepted 27 December 2006 Available online 27 February 2007
The review of this paper was arranged by Prof. S. Cristoloveanu
Abstract
A new source follower circuit using low-temperature polycrystalline silicon thin film transistors (LTPS-TFTs) as analog buffer for the integrated data driver circuit of active matrix liquid crystal displays (AMLCDs) and active matrix light emitting diodes (AMOLEDs) is proposed and measured. Threshold voltage compensation circuit with two n-type thin film transistors, a capacitor, and four switches structure is used to enhance image quality for the display. The threshold voltage difference of driving TFTs and the unsaturated of output voltage are eliminated in this circuit. An active load is added and a calibration operation is applied to study the effects on the source follower circuit, the transistor operation mode region is also discussed. The proposed circuit is capable of minimizing the variation from both the signal timing and the device characteristics through the simulation and measured results.
Ó 2007 Elsevier Ltd. All rights reserved.
Keywords: Source follower; LTPS-TFTs (low-temperature polycrystalline silicon thin film transistors); AMLCDs (active matrix liquid crystal displays); AMOLEDs (active matrix light emitting diodes)
1. Introduction
Low temperature poly-Si (LTPS) TFTs have attracted much attention in the application on the pixel circuits and integrated peripheral circuits of active matrix liquid crystal displays (AMLCDs) and active matrix light emit-ting diodes (AMOLEDs) [1–18]. In a poly-Si TFT-LCD, poly-Si TFT is not only used to implement pixel circuit but also the driving circuit on a single glass substrate to reduce system cost and possess compact module which a-Si TFT is hard to achieve.
Although LTPS-TFTs have superior electrical charac-teristics compared with a-Si TFTs, the inevitable non-uni-formity issue is encountered because of process variation such as toughly controllable grain size of poly-Si and gate oxide/poly-Si varied interface trap density.
Among the many data driving circuits employing LTPS TFTs, the output buffer is indispensable to drive the large load capacitance of the data bus. There are several require-ments for the output buffer for a flat panel display data dri-ver [9]. For instance, as resolution getting higher and higher, more analog buffers are needed. Therefore, its lay-out area must be reduced as possible to fit the pitch size. In addition, displays toward portable applications so that power dissipation must be minimized to extend the battery lifetime. However, comparing to the MOSFETs, the LTPS
0038-1101/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2006.12.007
*
Corresponding author. Fax: +886 3 5738343. E-mail address:toni.ee87@nctu.edu.tw(B.-T. Chen).
TFTs suffer from poor electrical characteristics and huge device-to-device variations mainly due to the non-uniform grain structure and grain size across the whole glass sub-strate. Fig. 1a shows the threshold voltage variation of thirty poly-Si transistors fabricated in the factory and
Fig. 1b shows the field-effect mobility variation. It is obvi-ous that even though in the factory, the LTPS TFTs still have 1 V threshold voltage maximum difference and 36 cm2/v s field-effect mobility maximum differences. Since thousands of output buffers are necessary for a poly-Si TFT-LCD, it is very essential to develop novel analog buf-fers dealing with the device non-uniformity. Electrical char-acteristic variations of LTPS-TFTs will cause the real output voltage not the target value and lead to the wrong image data through the analog buffer which leads poor image quality. Therefore, compensation circuit is essential for highly integrated panel. The output deviation depends on product specification must be decreased as possible con-forming to high degree of matching among the data lines. Among output buffer circuits for displays, source fol-lower is considered an excellent candidate for the output buffer circuit for the ‘‘System on Panel’’ application because of its simple schematic and low power dissipation
[10–18].
2. Proposed analog buffer and its driving schemes
We have proposed a new type analog buffer for the com-pensation of the device variation and signal timing before
[17,18]. Fig. 2shows a schematic and the timing diagram of the proposed analog buffer which consisting of two n-type thin film transistors, one capacitor, and four switches. The gate voltage of the TFT as the active load is biased at Vbias. The driving schemes are as described follows: 2.1. Compensation period
During first operating period, SW1 and SW2 are turned on, and SW3 and SW4 are turned off. Thereby, a voltage corresponding to the threshold voltage of driving TFT, the threshold voltage of the active load and the bias voltage is stored in Cvt.
2.2. Data input period
After sampling period, SW3 and SW4 are turned on and SW1 and SW2 are turned off, then the voltage at the gate of the driving TFT is hold. Thus, the output voltage is com-pensated by the voltage stored in Cvt.
In order to investigate the output performance of the proposed analog buffer, HSPICE circuit simulator was introduced. In this work, the typical model of the poly-Si TFTs for simulation is expressed by the PRI parameters. The load capacitance of data line is assumed 20 pF which corresponds to a 2-inch QVGA LCD. Monte Carlo simu-lation with an assumption of normal distribution is exe-cuted to study the effect of the device variation on the circuit performance, where the mean value and the devia-tion of the threshold voltage and mobility are 1.45 V, 0.5 V and 65.69 cm2/v s, 15 cm2/v s, respectively. Table 1
shows the dynamic performance of settling time of the
Fig. 1. Thirty low-temperature poly-Si transistors of (a) threshold voltage variation, and (b) field-effect mobility variation.
Fig. 2. The proposed analog buffer and its timing diagram of signal lines.
Table 1
The output settling time of the proposed analog buffer with input voltage 1–5 V
Input voltage Vin(V) 1 2 3 4 5
proposed analog buffer as input voltage 1–5 V. Fig. 3
shows the twenty times of Monte Carlo simulation results of the proposed analog buffer when input voltages are 2– 4 V. The variations of the driving TFT and the active load are both taken into consideration in the Monte Carlo simulation. The output voltage variation of the proposed analog buffer is about 50 mV, which is much smaller than that of conventional source follower type analog buffer (550 mV). The output voltage variation decreases dras-tically.
3. Analog buffer circuit fabrication and measured results After analog buffer circuit design finished, testing analog buffer circuits were fabricated and measured. The circuit fabrication processes are described as follows. First, a buf-fer oxide and 500 A˚ -thick a-Si thin film was deposited on glass substrate. Then, the amorphous Si thin film was crys-tallized by KrF excimer laser annealing at room tempera-ture. After defining the active layer, a 1000 A˚ -thick gate oxide was deposited by plasma-enhanced chemical vapor deposition. A 3000 A˚ -thick Cr film was then deposited for gate electrode. Then, the Cr thin film and gate oxide were etched to form gate electrodes. After N+and P+ion implantation, a 4000 A˚ -thick SiNx was deposited by PECVD as interlayer. TFT testing analog buffer circuits were formed after contact-hole formation and 4000 A˚ -thick Cr metallization. The image of optical micrograph of the proposed analog buffer circuit is shown in Fig. 4. The cross-section of TFTs is inserted in Fig. 4. In the design, the W/L ratio of the driving TFT, the active load and the switching TFTs are 100 lm/8 lm, 8 lm/50 lm and 8 lm/8 lm, respectively.
After probing system ready for measuring, several pro-posed and conventional analog buffer circuits were mea-sured and gathered statistics. The conventional analog buffer is a simple source follower configuration consists of a driving TFT connected a capacitor in serial. Fig. 5
shows comparison of the offset voltage with various input voltages between the conventional and proposed analog buffers. It is observed that the output voltage of proposed analog buffer is closely equal to the actual input voltage.
On the other hand, the offset voltage of conventional ana-log is mostly above 1 V which is large compared with pro-posed analog buffers. Output deviation of the propro-posed
Fig. 3. Twenty times of Monte Carlo simulation results of the proposed analog buffer when input voltages are 2–4 V.
Fig. 4. Optical micrograph of the proposed analog buffer circuit. (Inset): Cross-section view of the driving TFTs.
Fig. 5. Comparison of the offset voltage versus input voltage curve of the conventional and proposed analog buffers measured results.
Fig. 6. Offset voltage variation of eight sets of analog buffer circuits are compared between the conventional and proposed analog buffer circuits with different input voltages measured results.
analog buffer is controlled under 50 mV regardless of threshold voltage variation showing extremely good results. We also measured five sets data in each source fol-lower circuits shown inFig. 6. The figure shows that offset voltage of conventional analog buffer suffers huge varia-tions and the proposed analog buffer has small output var-iability and better uniformity after threshold voltage calibration.
4. Bias voltage effect of active load
In this section, the operation of the driving TFT and the active load will be discussed in detail. During the first oper-ation period, the driving TFT and the active load are both working in the saturation region since the VDDpower line
compensation. Nevertheless, during the second operation period, the active load operates in linear or saturation region depending on input data voltage while the driving TFT still works in the saturation region. We divide it into two conditions for discussing.
4.1. A. Driving TFT in saturation region, active load in saturation region
These results can be expressed by formula as follows: (We assumed that the driving TFT as TFT1 and the active load as TFT2 here for convenience)
(1) Compensation period: ID¼ K1ðVGS1 VTH1Þ 2 ¼ K2ðVGS2 VTH2Þ 2 ! K1ðVDD Vout VTH1Þ 2 ¼ K2ðVbias VTH2Þ 2 ! a ¼ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiK1=K2 p ¼ Vbias VTH2 VDD Vout VTH1 aVDD aVout aVTH1¼ Vbias VTH2 Vout¼ VDD VTH1þ 1 aVTH2 1 aVbias )Cvt storageDV ¼ VDD Vout¼ VTH1 1 aVTH2þ 1 aVbias: ð1Þ
(2) Data input period:
ID¼ K1ðVinþ DV Vout VTH1Þ 2 ¼ K2ðVbias VTH2Þ 2 ! a ¼ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiK1=K2 p ¼ Vbias VTH2 Vinþ ðVTH11aVTH2þ1aVbiasÞ Vout VTH1
! aVin VTH2þ Vbias aVout¼ Vbias VTH2
) Vout¼ Vin ð2Þ
The Eq.(1)indicates that the variations of driving TFT and the active load both can be stored for the compensa-tion during the operacompensa-tion period. Therefore, the Eq. (2)
shows the output voltage equal to the input voltage theoretically.
4.2. B. Driving TFT in saturation region, active load in linear region
(1) Compensation period:
During the first operation period, the situation is the same as described previously which the voltage stored in the capacitor depending on the threshold voltage, bias voltage and the K1/K2ratio.
(2) Data input period:
ID¼ K1ðVinþ DV Vout VTH1Þ2 ¼ K2½ðVbias VTH2ÞVout 1 2V 2 out ! a2½V inþ DV Vout VTH1 2 ¼ ðVbias VTH2ÞVout 1 2V 2 out from Eq.(1): DV ¼ VDD Vout¼ VTH1 1 aVTH2þ 1 aVbias! a 2 V inþ VTH1 1 aVTH2þ 1 aVbias Vout VTH1 2 ¼ ðVbias VTH2ÞVout 1 2V 2 out) Vout¼
2ðVbias VTH2Þ þ 4aðVbias VTH2Þ þ 4a2Vin
2ð1 þ 2a2Þ
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A
þ
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ½ð4a þ 2ÞðVbias VTH2Þ þ 4aVin
2
4ð2a2þ 1Þ½2ðV2 bþ V
2
tÞ þ 4aVinðVbias VTH2Þ þ 2a2V2in 4VbiasVTH2
q
2ð2a2þ 1Þ
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We assume that 2a2 1, 4a 2
(A) term can be simplified to VinþðVbiasVa TH2ÞþðVbias2aV2TH2Þ
(B) term:
Therefore, the output voltage can be simplified as Vout¼ Vinþ ðVbias VTH2Þ a þ ðVbias VTH2Þ 2a2 ; ð3Þ where a2= K1/K2.
According to the Eq.(3)proved, the output voltage will be larger than the input voltage because that the bias volt-age must be higher than the threshold voltvolt-age of the active load to turn on the active load. Therefore, we know that if
the active load works in the linear region at the data input period, the output voltage will exceed the input data and thus a negative offset voltage is obtained. This situation will happen when the bias voltage is higher than the input volt-age. Furthermore, from the Eq.(3), we know that the out-put voltage almost equal to the inout-put voltage when the factor a large in design theoretically. The mobility of the driving TFT and the active load are assumed equal. There-fore, the driving TFT is designed larger W/L ratio and the active load is designed smaller W/L ratio to possess large factor a. The larger factor a, the output voltage is more accurate.
Fig. 7a shows the comparison of the offset voltage versus bias voltage curve of the simulation and measured results when input voltage 2 V. It is shown that the offset voltage has optimum value around 2 V which the active load just nearly turns on and leads to the saturation region. The sim-ulation and measured results of input voltage 3 V also shown in Fig. 7b. It is observed that the measured result trend is close to the simulation results. The larger bias volt-age is the larger offset voltvolt-age is. Proper design of the bias voltage is required to achieve total performance.
5. Summary and conclusions
A novel source follower type analog buffer have been presented and measured, where the driving circuit is formed by only two n-type thin film transistors, one capac-itor, and four switches. The large mismatch of LTPS-TFTs in threshold voltage is compensated and output voltage come very close to the actual input voltage. Much improved output voltage stability and simple configuration are achieved by adding the bias circuit and the compensa-tion operacompensa-tion. The operacompensa-tion of the driving TFT and the active load related to bias voltage are also discussed in detail. Through the simulation and measured results, the proposed source follower type analog buffer is capable of minimizing the variations from signal timing and the device varied characteristics. Proper design of the bias voltage ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
½ð4a þ 2ÞðVbias VTH2Þ þ 4aVin 2
4ð2a2þ 1Þ½2ðV2 bþ V
2
tÞ þ 4aVinðVbias VTH2Þ þ 2a2V2in 4VbiasVTH2
q
2ð2a2þ 1Þ
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ½ð4aÞðVbias VTH2Þ þ 4aVin
2
4ð2a2Þ½2ðV2 bþ V
2
tÞ þ 4aVinðVbias VTH2Þ þ 2a2V2in 4VbiasVTH2
q 4a2 ! ffiffiffi 0 p 4a2
Fig. 7. (a) Comparison of the offset voltage versus bias voltage curve of the simulation and measured results when input voltage 2 V. (b) Comparison of the offset voltage versus bias voltage curve of the simulation and measured results when input voltage 3 V.
applied to the active load is required to achieve excellent performance.
Acknowledgements
We thank the ChungHwa Picture Tubes for their techni-cal support. This work has been sponsored by the Ministry of Education of Taiwan, Republic of China, the Program for Promoting Academic Excellent of Universities under a Grant (No. 91-E-FA04-2-4-B) and ChungHwa Picture Tubes, Ltd. (CPT).
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