A Continuous-Time Delta-Sigma Modulator Using Feedback Resistors

A Continuous-Time Delta-Sigma Modulator

Using Feedback Resistors

Yung-Chou Lin1, Wen-Hung Hsieh2, and Chung-Chih Hung3 Department of Communication Engineering

National Chiao Tung University Hsinchu, Taiwan, R.O.C.

A

A third-order continuous-time delta–sigma comprised of Active-RC integrator and Gm-C integrator is presented. For the consideration of power, linearity and performance, the first integrator uses active-RC OpAmp and the others use Gm-C. To reduce the clock jitter sensitivity, we choose nonreturn-to-zero (NRZ) pulse shaping as our DAC type. For the realization of NTF zero optimization, we use resistors to reduce power consumption. The delta-sigma modulator is implemented in standard digital 0.18-m CMOS process which achieves a 60-dB SNDR or 10-bits ENOB over a 1-MHz signal bandwidth at an OSR of 50. The power consumption of the continuous-time delta-sigma modulator itself is 13.7 mW from the 1.8-V supply.

Index Term Ё continuous-time, delta-sigma, modulator, Gm-C

I

With the growth of wireless communication, there has been more focus on the analog-to-digital converter (ADC) for wireless applications. Among all ADCs, delta-sigma converters are preferable over flash and pipeline converters because they offer the most economic bandwidth and accuracy trade-off. Recently, continuous-time delta-sigma ADCs get growing interests in wireless applications for their lower power consumption and wider bandwidth as compared with the discrete-time counterparts. Because of the settling time requirement for the charge transfer between the switched-capacitor integrators, it boosts its power consumption. Therefore, they are used for low bandwidth applications. On the contrary, the sampling speed in CT isn’t limited by any settling requirements. Besides, the sample-and-hold circuit in the front-end doesn’t need and benefits from having inherent anti-aliasing filter. This leads to lower power consumption and less chip area. However, CT modulators suffer from the severe process-varying RC time constant, excess loop delay and clock jitter issues which require extra care. In this paper, the system level and circuit level design of this work is presented in detail, which includes the determination of the system level parameters. After that, the circuit blocks will be discussed, and the modulator is realized with a 0.18-m CMOS technology and 1.8 V power supply voltage.

S

L

D

A. System Level Parameters

First of all, to design the  modulator is determining the system level parameters. For a CT  modulator, the important specification is the clock jitter sensitivity. It will significantly affect the selection

of the system level parameters. We usually assume that the modulator will be evaluated with a clock signal generated by the instrument. Therefore, the jitter value of the clock signal entering the modulator is determined by the quality of the instrument signal. In this work, the RMS value of the target jitter tolerance is 15 ps to satisfy the specification, as shown in Figure. 1.

Besides, the system level parameters include the oversampling ratio (OSR), the loop filter order (L), the number of the quantizer level (M) and the aggressiveness of the noise shaping which is

0.5 1 1.5 2 2.5 -60 -40 -20 0 20 40 60 80 Out-of-Band Gain S NR ( d B ) 0 10 20 30 40 50 50 55 60 65 70 75 80 85 SND R ( dB) jitter (ps)

FIGURE.1SIMULATED SNDR AS A FUNCTION OF CLOCK JITTER

FIGURE.2SIMULATED SNR AS A FUNCTION OF OUT-OF-BAND GAIN FOR SINGLE BIT

2 S k sT 1 S k sT 3 S k sT 1

DAC DAC2 DAC3

g

determined by the maximum out-of-band quantization gain. Considering the gain-bandwidth requirement of the OpAmp with acceptable power consumption and the clock jitter sensitivity, we choose 50 as our OSR value. The power consumption of the quantizer increases proportionally to the number of quantization levels. Therefore, we determine the number of the quantizer be single. On the other hand, increasing the loop filter order is cheap, but the loop stability issue limits the loop order, so we choose 3 as our loop order. Besides, the aggressiveness of the noise shaping is also limited by the stability issue. After MATLAB Control System toolbox simulation, as shown in Figure. 2, we choose 1.6 as our out-of-band gain. Based on these requirements, a large amount of simulations were performed by using the MATLAB toolbox to explore the parameter space [1].

B. NTF Zero Optimization

When designing wide band  modulator, a technique is usually used. That is separating zeros on the unit circle, which means it spreads over the signal range, as shown in Figure. 3. By shifting the two zeros from dc ( = 0) to an optimized value, we can get the 8 dB SQNR improvement [2].

In Figure. 4, we show the architecture of CT  modulator using feedback resistors. The loop filter architecture we use is general feedback structure.

C

I

A. Loop Filter

The third-order loop filter of this work design is implemented with CRFB architecture, as shown in Figure. 5. The first stage is an active-RC integrator and the following resonators are realized by Gm-C integrators and the resistor. The role of the resonators is to shift the poles of the loop filter to optimum non-zero frequencies in order to reduce in-band quantization noise and get better performance, as mentioned before. There are two types of commonly

VSS VDD VIP M1 M2 VIN M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 Vcmfb Vb3 Vb3 VON VOP A A

used continuous-time integrators: active-RC integrators and Gm-C integrators. In this design, the first stage uses an active-RC integrator rather than the Gm-C integrator for its superior linearity. Gm-C integrators are chosen for the two resonators to save power.

B. First Stage

Ё

The OpAmp in the active-RC integrator uses a folded-cascode topology with a gain enhancement method by adding additional stages to increase DC gain. This method is called gain-boosting [3] [4]. Compared with the telescopic OpAmp and the two-stage OpAmp, the folded-cascode OpAmp achieve the tradeoff between the power consumption and output swing in this 0.18-m CMOS design. Figure. 6 shows the schematic of the gain-boosting folded-cascode OpAmp used in this design.

C. Following Stage

Ё

With the exception of the first stage integrator, the following two integrators are implemented with Gm-C integrators to save power. A folded-cascode architecture is used with source degeneration resistor, as shown in Figure. 7. It achieves the required linearity and it has wider output swing as well.

-1 -0.5 0 0.5 1 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Real Part Im ag inar y P ar t 104 105 106 107 -160 -140 -120 -100 -80 -60 -40 -20 0 SN D R ( dB ) Frequency (Hz)

FIGURE.3OPTIMAL THIRD–ORDER NTF FOR OSR=50

FIGURE.4THE SYTEM ARCHITECTURE OF THIS WORK

FIGURE.5SIMPLIFIED CIRCUIT BLOCK OF THIS WORK

FIGURE.6SCHEMATIC OF GAIN-BOOSTING FOLDED-CASCODE OPAMP

D. Feedback Resistors

As previous section mentioned, the role of the resonators is to shift the poles of the loop filter to optimum non-zero frequencies in order to reduce in-band quantization noise and get more performance. In the circuit level, we simplify Figure. 4 as Figure. 8 to express. We can get the transfer

function 2 3 1 2 3 2 3 4 2 3 out in Gm Gm V RC C C V Gm Gm s s C C = − § ₊ · ¨ ¸ © ¹

. Therefore, we get three

poles s=0 and 2 3 4 2 3 0 Gm Gm s C C

+ = , and find the shift

frequency 3 4 2 3 1 2 Z Gm Gm f C C π

= . In general, the implementation of Gm4 is gm cell which is the active component. Considering the

power consumption, we replace gm cell with the resistor, that is, 1

Gm R

= to save power.

E. Tuning Circuit

The time constant shift due to process variations in practical continuous-time circuits can degrade system performance to an unacceptable level. For CT  modulators, 20%± variation is more than enough to drive the modulator into unstable operation. To solute this issue, we apply a capacitor array tuning method to adjust the time constants, as shown in Figure. 9 [5]. The capacitors in the arrays are binary-sized except the always-in-use capacitors. This sizing method is to provide constant tuning step with the least number of

capacitors and to ease layout. The 4-bit digital control codes are fed externally to choose which capacitors to use.

The total capacitor value in use is: Cin use=8C+ ⋅ , k = 0~15. k C The maximum available capacitance in the array isCmax=23C, and

the minimum available capacitance in the array isC_min=8C. For normal operation, the capacitor value isCnormal=16C. Therefore, the tuning range of the integration capacitor arrays is23 16 ~8 16

23 16

C C C C

C C

− −

, that is, +43.75% ~ -50%, which suffices for the requirements of this modulator according to 20% capacitor process variations.

M

R

The chip is fabricated in a 0.18-m CMOS process. The die photo is shown in Figure. 10. The total area, including pad is 1.14 x 0.95 mm2. The captured output digital data is windowed by a Hann window and a Fourier transformation is applied using Matlab. The measured peak SNDR is 60 dB as shown in Figure. 11. The measured SNDR versus the relative input amplitude is shown in Figure. 12. The power consumption measured with 100 MHz sampling frequency is 13.7 mW. The measured performance is summarized in Table I.

To quantitatively evaluate the efficiency among power dissipation, signal bandwidth, and SNDR. We use the formulas for the effective number of bits (ENOB) and the figure-of-merit (FOM) as described below,

FIGURE.7SCHEMATIC OF GM WITH SOURCE DEGENERATION RESISTOR

FIGURE.8THE SIMPLIFIED SCHEMATIC OF LOOP FILTER

FIGURE.9TUNABLE CAPACITOR ARRAY

FIGURE.10DIE PHOTO OF THIS WORK

Refs SNDR Signal

Bandwidth OSR Architecture Process

Power Supply Die Size Power Dissipation FOM ( pJ/conv ) 1999 JSSC [6] 82 dB 1.1 MHz 24 MASH 2-1-1 0.5-m CMOS 3.3 V 5.06 mm2 200 mW 8.84 2000 JSSC [7] 79 dB 1.1 MHz 24 MASH 2-2-2 0.35-m CMOS 3.3 V 4.3 mm2 248 mW 15.48 This work simulation 67 dB 1 MHz 50 3 rd -order 0.18-m CMOS 1.8 V 1.08 mm2 13.6 mW 3.717 This work measured 60 dB 1 MHz 50 3 rd -order 0.18-m CMOS 1.8 V 1.08 mm2 13.7 mW 8.4 103 104 105 106 107 108 -140 -120 -100 -80 -60 -40 -20 0 S NDR (d B ) 100 -700 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 Input Amp (dB) SN D R ( d B) 2 2ENOB Power FOM BW = × × (1) and smaller FOM is better.

Table I lists previously reported SC delta-sigma modulators about 1 MHz signal bandwidth. Compared with them, the SNDR is not the best, but FOM is top. Therefore, we can find continuous-time

delta-sigma get growing apply to wireless applications for their lower power consumption and wider bandwidths as compared with the discrete-time counterparts.

C

A continuous-time delta-sigma modulator using feedback resistors is presented. This work is designed using 0.18-m CMOS technology in 1.8 V power supply voltage. With a 100 MHz clock, this modulator achieves 60 dB SNDR and 60 dB dynamic ranges with a 1MHz signal bandwidth. A technique of using feedback resistors is realized, the low jitter clock generator have the CT  modulator not be sensitive to clock jitter, and tuning circuits are employed to calibrate the time constant shift due to process variations.

R

[1] Zhimin Li, “Design of a 14-bit Continuous-Time Delta-Sigma A/D Modulator with 2.5MHz Signal Bandwidth” B.S. thesis,

University of Oregon State, 2006.

[2] R. Schreier, and G. C. Temes, Understanding Delta-Sigma

Data Converters, Piscataway NJ: IEEE Press, 2005.

[3] K. Bult and Govert J. G. M. Geelen, “A Fast-Settling CMOS OP Amp for SC Circuits with 90-dB DC Gain,” IEEE J.

Solid-State Circuits, vol. 25, no. 6, pp. 1379-1384, Dec. 1990.

[4] K. Nakamura and L. R. Carley, “A Enhanced Fully Differential Folded-Cascode Op Amp,” IEEE J. Solid-State

Circuits, vol. 27, no. 4, pp. 563-568, April. 1992.

[5] S. Yan and E. Sanchez-Sinencio, “A Continuous-Time Sigma-Delta Modulator with88-dB Dynamic Range and 1.1-MHz Signal Bandwidth,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 75-86, Jan. 2004.

[6] S. Paton, et al., “A 3.3V, 15-bit, Delta-Sigma ADC with a Signal Bandwidth of 1.1 MHz for ADSL Applications,” IEEE

J. Solid-State Circuits, vol. 34, no. 7, pp. 927-36, Jul. 1999.

[7] J. Morizio, et al., “14-bit 2.2-MS/s Sigma-Delta ADC’s,”

IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 968-76, Jul.

2000. FIGURE.11OUT SPECTRUM OF THE MEASURED RESULT

FIGURE.12SNDR VERSUS NORMALIZED INPUT AMPLITUDE

TABLE I

PERFORMANCE COMPARISON BETWEEN REPORTED DESIGNS AND THIS WORK