A Monolithic Current-Mode Buck Converter With
Advanced Control and Protection Circuits
Feng-Fei Ma, Wei-Zen Chen, and Jiin-Chuan Wu
Abstract—A monolithic current-mode pulse width modulation (PWM) step-down dc–dc converter with 96.7% peak efficiency and advanced control and protection circuits is presented in this paper. The high efficiency is achieved by “dynamic partial shutdown strategy” which enhances circuit speed with less power consumption. Automatic PWM and “pulse frequency modulation” switching boosts conversion efficiency during light load operation. The modified current sensing circuit and slope compensation circuit simplify the current-mode control circuit and enhance the response speed. A simple high-speed over-current protection circuit is proposed with the modified current sensing circuit. The new on-chip soft-start circuit prevents the power on inrush cur-rent without additional off-chip components. The dc–dc converter has been fabricated with a 0.6 m CMOS process and measured 1.35 mm2with the controller measured 0.27 mm2. Experimental results show that the novel on-chip soft-start circuit with longer than 1.5 ms soft-start time suppresses the power-on inrush cur-rent. This converter can operate at 1.1 MHz with supply voltage from 2.2 to 6.0 V. Measured power efficiency is 88.5–96.7% for 0.9 to 800 mA output current and over 85.5% for 1000 mA output current.
Index Terms—Compensation ramp, current sensing, current-mode control, over-current protection, power management, pulse frequency modulation (PFM), pulse width modulation (PWM), soft-start, switching dc–dc converter.
I. INTRODUCTION
P
ORTABLE battery-operated devices are more and more popular today. For these devices, small size, light weight, and long battery run-time are the main demands. The batteries had become a main portion in space and weight of these portable devices. As a result, enhancing the efficiency of power supply and management is very important to minimize the size and weight and to extend the battery run-time. The well-known power management strategy, sleep mode, shuts down the un-used partial circuit to effectively reduce the power consumption [1]. Although sleep mode can save the power effectively in standby mode, there is no power saving in active mode because it operates with full current. The way of saving the power is to reduce the operating current but this usually reduces the circuit performance such as speed and noise immunity.We focused on increasing the power efficiency and reducing die size without sacrificing high speed operation. Besides, safety Manuscript received November 10, 2006; revised April 25, 2007. Recom-mended for publication by Associate Editor Y. C. Liang.
The authors are with the Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: ffma.ee87g@nctu.edu.tw; wzchen@alab.ee.nctu.edu.tw; jcwu@gmt.com.tw).
Digital Object Identifier 10.1109/TPEL.2007.904237
operation is also an important consideration in power supply de-sign. In this paper, we propose the dynamic partial shutdown strategy (DPSS), current sensing, over-current protection, soft-start and pulsewidth modulation–pulse frequency modulation (PWM-PFM) operation to achieve our goal.
The DPSS manages the power consumption at active mode to enhance the circuit performance per power consumption. Im-provement was obvious, especially in lighter load with the PFM mode control [2].
Moreover, we modified the current sensing and slope com-pensation circuits in current-mode control [3]–[11] to simplify the design flows of various specifications. In current sensing circuit, a simple over-current protect comparator is developed. Its response speed is faster than the conventional comparator [10], [12], [13]. But it consumes no additional quiescent power. With this circuit, the over-current protection, which is essential to voltage regulator, can be designed easily.
Most portable electronic devices have more than one power supply modules. Anyone of them may be shut down when the circuit supplied by it is unused. However, if we turn on the power supply module and don’t handle the load current demand from next stage properly, the inrush current demand to previous stage will result in impulse voltage drop and affect the circuit opera-tion or shorten the life-time of batteries. On the other hand, in-rush current can also cause the output to overshoot [14]. To over-come the induced effects, a soft-start time, usually 1 10 ms for portable electronic devices, is required at the beginning of the turn-on stage for voltage regulators. During soft-start time, the corresponding voltage regulator charges the output capac-itor slowly, and then no inrush current is generated to affect the pre-stage circuit or to cause output overshoot. The conven-tional method of generating the soft-start time is costly in area [12], [15], [16] or need the extra pin-out and discrete capacitor [14], [17]–[20]. This method results in the increase in cost, size and weight. This paper also presents a simple and area-effective circuit to generate soft-start time without the extra pin-out and discrete capacitor. This circuit has the soft-start time propor-tional to the square of silicon area and is suitable for even longer soft-start time ( 10 ms) applications.
Structure of current-mode PWM and PFM control are intro-duced in Section II, [2], [21]. Circuit implementations of the controller are discussed in Section III.
All the circuits mentioned above are integrated in a mono-lithic buck converter and implemented in a 0.6 m CMOS process. It can operate in a wide input range from 2.2 to 6.0 V. Measurement results are shown in Section IV and conclusion is in Section V.
Fig. 1. Simplified structure of current-mode PWM control.
II. STRUCTURE OF THEMONOLITHICBUCKCONVERTER In this section, we will briefly introduce the structure of cur-rent-mode PWM and PFM operation in the developed mono-lithic buck converter [2], [21].
A. PWM
At moderate to heavy loads, the converter operates in PWM mode. The block diagram of a simplified current-mode PWM buck converter is illustrated in Fig. 1. A clock pulse at the (reset) input of SR Latch initiates the switching period, causing the latch output to be low. The latch output goes through Buffer and Dead Time Control to produce both DH and DL low to turn on the high side PMOS transistor and turn off the low side NMOS transistor. While the high side transistor conducts, its current is equal to the inductor current. This current increases in a certain positive slope according to the inductor value and converter voltages. We sense the high side transistor current and compare it with the control voltage . When the sensed cur-rent signal becomes higher than control voltage , the mod-ulator output will be high to set the SR Latch output high. Again the latch output goes through Buffer and Dead Time Control to produce both DH and DL high to turn off the high side PMOS transistor and turn on the low side NMOS transistor until next clock pulse. We see the current controlled through the control voltage and thus is named current-mode control. On the other hand, a compensation ramp is added to the sensed current signal to suppress sub-harmonic oscillation at duty ratio
50% [3].
B. PFM
With decreasing load current, the converter automatically switches into PFM mode in which the power stage operates intermittently, based on load demand. Due to reduced switching activity at power stage, the switching losses are minimized, and the device runs with a minimum quiescent current and maintains high efficiency. The block diagram of a simplified PFM mode buck converter is illustrated in Fig. 2. The output voltage is monitored with a voltage comparator. As soon as the
Fig. 2. Simplified structure of PFM control.
output voltage falls below the nominal value, the output of the voltage comparator resets the SR Latch. Through Buffer and Dead Time Control the high side PMOS transistor is turned on and the inductor current ramps up. When a current comparator detects that the inductor current reaches the preset peak current, its output sets the SR Latch and turn off the high side PMOS transistor and turn on the low side NMOS transistor. As the inductor current ramps down, a reverse current comparator de-tects if the inductor current begins to flow in reverse direction. When this is the case, the Reverse Current Comparator turns off the low side NMOS transistor to prevent drawing energy from output capacitor back to ground. When the output voltage falls below the nominal voltage again, the next cycle is started. As the load current decreases, the time interval between two successive pulses will become larger and vice versa.
C. Automatic PWM/PFM Mode Switching
There are many algorithms of switching between PWM and PFM. In this paper, we use a hysteresis switching algorithm to prevent repeatedly switching between two modes during steady state operation. The algorithm can be described as follows.
1) In PWM mode, as the load current decreases, the inductor current may ramp to zero before the end of each clock cycle. In order to increase the efficiency, the low side NMOS will be turned off when the inductor current ramps to zero. This action prevents the current flowing in reverse direction from output capacitor to ground through inductor and low side NMOS. Thus, the converter enters discon-tinuous conduction mode (DCM). When the converter operates in DCM, it means that the load current is small and we don’t need continuous full-cycle-pulses to sustain it. If the converter operates in DCM for about 20 s, it will automatically switch to PFM mode.
2) In PFM mode, the peak current of each pulse is preset to a constant value as described above. We monitor the output voltage to determine when the next pulse should be issue. The next pulse will be issue if the output voltage falls below the nominal value. When the load current increases, the
Fig. 3. Functional block diagram of the developed monolithic buck converter.
output voltage falls faster and the two pulses in succession will become closer. If the output voltage falls below the nominal value after the peak current is reached and before the current ramps back to zero, it means that we need to issue the next pulse even before the present pulse is com-pleted. In this condition, the load current is large and the output voltage cannot be sustained with this preset current pulse. Thus the converter will enter PWM mode again.
D. Proposed Converter
Fig. 3 shows the simplified block diagram of the developed converter chip. It uses PWM and PFM control as described above. Key elements such as on-chip soft-start, DPSS, current sensing, modulator, and over-current comparator will be de-scribed in the next section.
III. DESIGNCONSIDERATIONS ANDCIRCUITIMPLEMENTATIONS
A. On-Chip Soft-Start Circuit
There are mainly two kinds of conventional soft-start circuits. One is the clock-based soft-start circuit which raises the refer-ence voltage or maximum output current or duty cycle slowly [12], [15], [16]. In this method, the way to achieve the longer soft-start time ( 1 ms) is to reduce the clock frequency or in-crease the bit-length of counter. The former one fails to reach the goal of raising the switching frequency to minimize the energy storage elements (such as inductors and capacitors) and to en-hance the response speed in switching regulator design. A sep-arate clock can be used for soft-start, but it requires extra die area and power. The latter one, however, consumes large silicon area. Moreover, the clock-based soft-start needs time-to-voltage or time-to-current-limit circuits.
The other soft-start method charges the capacitor with a con-stant current to generate a steadily rising voltage. This steadily rising voltage can be used as reference voltage during startup or to limit the duty ratio or output current during startup [14], [17]–[20]. The soft-start time can be calculated as
(1)
Fig. 4. Soft-start ramp generator.
Note that is the reference voltage or a threshold voltage which determines the end of startup, is the capacitor value and is the charging current.
In previous works [14], [17]–[20], extra pin-out and discrete capacitor were needed to reach longer soft-start time ( ms). For example, if equals 0.6 V and 1 ms soft-start time is needed with 1 A charging current, a 1.67 nF capacitor is needed. Our goal is to minimize the capacitor using small charging current. For integration of capacitor on die, the order of capacitor is picofarad. Correspondingly, the charging current is in the order of nanoampere. In [22]–[25], complex bias circuit is needed to generate the bias current in nanoampere order. In addition, transistors must operate in deep subthreshold region. The – characteristic of MOS transistor operates in the deep subthreshold region is [26]
(2) where depends on process, 1.5 and is the threshold voltage of the transistor. The effectiveness of gate drive voltage to drain current is exponential. Noise on the gate drive voltage will greatly affect the drain current. So that deep subthreshold bias is not suitable for a noisy environment like switch-mode power supply with integrated power switches.
In this paper, a simple circuit is proposed as shown in Fig. 4. Note that, can be generated by a simple bias circuit or the existing bias voltage in the system. In Fig. 4, for a general bias circuit
(3) The transistor operates in saturation region. We can use simple MOS transistor equations in [26]:
Saturation region
(4) Triode region
(5) where is mobility and is oxide capacitance. When is well below VCC, transistor operates in saturation region. Other series transistors operate in triode region. Therefore, are like the ( 1) linear resistances
whose total voltage drop is slightly smaller than . For small , we approximate (5) to
(6) Then, according to Ohm’s law, we have
(7) As a result, the nanoampere order charging current can be achieved easily in today’s technology. For example, if equals to 0.6 V, 1 ms soft soft-start time is available with a 1-nA current to charge the 1.67-pF capacitor. In our design, the soft-start circuit occupies only 56.1 65.4 m and reaches longer than 1.5 ms soft-start time.
Another advantage of this circuit is that the soft-start time is proportional to the square of the silicon area. According to (1), for a fixed reference voltage, the soft-start time is proportional to the capacitor value and reverse proportional to the charging current. In (7), the charging current is reverse proportional to the summation of of transistors. Thus we have the soft-start time proportional to the series number of PMOS. If we increase both the capacitor value and the series number of PMOS with the same ratio, the soft-start time is proportional to the square of the silicon area. The proposed method can reduce the silicon area dramatically and this circuit does not need extra pin-out and discrete capacitor.
B. Dynamic Partial Shutdown Strategy
For extension of battery run time of portable devices, dynamic power management uses sleep mode which shuts down unused circuits to save power during standby mode [1]. However, in ac-tive mode, it cannot save the power consumption because of the full operating current. In this paper, the dynamic partial shut-down strategy (DPSS) controlling the turn off of partial circuits is proposed to save the power consumption, especially in ac-tive mode. During acac-tive mode, only the essential parts will be turned on in specific operating situation under DPSS. As a re-sult, the power consumption is minimized and battery run time is extended.
In a switch-mode power supply, the decision of when to turn on or turn off switches was made according to the output voltage and current condition in each switching cycle. When the switch is on, we need to decide when to turn it off; when the switch is off, we need to decide when to turn it on again. According to this characteristic of switch-mode power supply, we can turn off partial circuits which are not needed to decide when the switch should be turned off during “ON” state and vice versa. Since there are digital signals indicating the ON and OFF states of the power switches in the converter, we can use these digital signals to turn on and turn off the partial circuits which are not needed in each state.
Take the proposed converter as an example. In Figs. 5 and 6, we use horizontal, vertical, and oblique lines to indicate shut down parts. Blocks with horizontal lines are shut down when high side PMOS is turned on. Blocks with vertical lines are shut
Fig. 5. DPSS in PWM mode. Blocks with horizontal lines are shut down when high side PMOS is turned on. Blocks with vertical lines are shut down when low side NMOS is turned on.
Fig. 6. DPSS in PFM mode. Blocks with horizontal lines are shut down when high side PMOS is turned on. Blocks with vertical lines are shut down when low side NMOS is turned on. Blocks with oblique lines are shut down when both power transistors are turned off.
down when low side NMOS is turned on. Blocks with oblique lines are shut down when both power transistors are turned off. Fig. 5 shows circuits operate in PWM mode; and Fig. 6 in PFM mode. Note that the soft-start time has been completed and the Soft-Start in Figs. 5 and 6 is always shut down.
In PWM mode, when high side PMOS is turned on, the slope of inductor current is positive. So we don’t need to detect re-verse inductor current and the Rere-verse Inductor Current De-tector can be turned off. When low side NMOS is turned on and that the slope of inductor current is negative, there is no need to detect the over-current and the Current Sensing and Over-current Comparator can be shut down. Since the slope of inductor current is negative, the Over-voltage Comparator cannot do anything more to prevent output voltage from going too high. Thus the Over-voltage Comparator can be shut down. Besides, the next turning on of high side PMOS is decided by clock pulse in constant frequency leading edge modulation [27].
The Saw-tooth Generator, Analog Adder, and Modulator can also be shut down.
In PFM mode, the Error Amplifier, Oscillator, Saw-tooth Generator, Analog Adder, and Modulator all can be shut down. When high side PMOS is turned on, only the peak inductor current decides when to turn it off. As a result, the Voltage Comparator and Reverse Inductor Current Detector can be shut down. When low side NMOS is turned on, the Current Sensing and Over-current Comparator can be shut down. When both high side PMOS and low side NMOS are turned off, only the Voltage Comparator is active to decide when the high side PMOS should be turned on again.
When using DPSS, care must be taken as dealing with analog signal level between ON and OFF states. For example, if the analog signal level of the Current Sensing is not preset correctly when the Current Sensing is turned off, the Current Sensing may give wrong information about the inductor current at the begin-ning of next cycle. This wrong information may result in un-stable operation. On the other hand, timing of digital signal is also an important issue. For example, if the Over-voltage Com-parator is not turned on slightly before the next cycle, the next pulse may cause the output voltage goes even higher during tran-sient conditions. This high voltage may damage the circuits in load stage.
Simulation results show that in PWM mode, operating cur-rent can be reduced from 500 A to 250 300 A, depending on the duty ratio. In PFM mode, operating current can be re-duced from 200 A to 50 A. The reduced operating current can effectively boost conversion efficiency especially in light
load operation. For example, when 3.6 V, 2.5 V
and 1 mA, the conversion efficiency is 89% and 75% with and without DPSS, respectively. Higher input voltage and lower load current will increase the difference. When
4.2 V, 2.5 V and 1 mA, the results are 88%
and 72% with and without DPSS, respectively. When
3.6 V, 2.5 V and 0.5 mA, the results are
84% and 62% with and without DPSS, respectively.
C. Current Sensing and Slope Compensation
The current sensing circuit is one of the most important building blocks in current-mode control. There are many current sensing circuits available [4]–[11]. Among them we choose the current-conveyor-based sense-FET current sensing [5]–[10], [28] because it has some good features as follows.
1) It dose not need the extra pin-out and external component. 2) Its quasi-lossless characteristic could enhance the
effi-ciency [9].
3) Matching devices, instead of of MOSFET or pas-sive component such as resistors, are used to improve ac-curacy (reported higher than 94% acac-curacy [5], [6]). 4) It can operate in low voltage [6] and has improved noise
immunity [10].
5) It can be easily compensated [10] and has high speed re-sponse [10].
The current sensing circuit is shown in Fig. 7. The second generation negative current conveyor (CCII-) [28] is enclosed in the dashed box. In our current sensing circuit design, we use the second generation current conveyor (CCII-) instead of the
Fig. 7. Current-conveyor-based sense-FET current sensing.
first generation current convey (CCI) used in [5]–[8]. The CCII has no current flow in terminal , thus eliminates the unused power dissipation and extra circuits. According to the principles of CCII-[28], (8) and (9) were shown as follows:
(8) (9)
According to (4) and (5), when and
, we obtained
(10) From (9) and (10)
(11) And the relationship of the sensed current and the inductor cur-rent can be determined by the aspect ratio of and . As a result, accurate current information is obtained for the control loop of the current-mode control.
When dealing with current-mode control, there is a well known instability problem for duty ratio greater than 50% [3]. An artificial ramp acts as slope compensation must be added to the sensed current signal to suppress the sub-harmonic oscillation of the converter. How to generate a compensation ramp and add it to the sensed current signal is another issue. Conventionally, both the output of current sensing and the compensation ramp are expressed in “voltage” form [4]–[11]. We need a summing amplifier to add the compensation ramp to the sensed current signal as shown in Fig. 8(a) [4]. Another solution is to convert the current
infor-mation and compensation ramp to “current”
form by -to- converters, respectively. Then we add these two current together and get the summing voltage through a single resistor as shown in Fig. 8(b), [5], [6]. These methods
Fig. 8. Different methods of adding compensation ramp to sensed inductor cur-rent signal. (a) Summing amplifier. (b) Use twoV -to-I converters and adding the current signals by a resistor. (c) Proposed summing circuit.
need multiconverts with complex circuits, and correspondingly, inducing more distortion to the desired signal.
To solve the above problem, we propose a simple and ef-fective circuit as shown in Fig. 8(c). Because the output signal of the current-conveyor-based sense-FET current sensing mentioned above is in current form, it does not need a -to-converter. On the other hand, the compensation ramp can be generated by charging a capacitor with a constant current and discharging it with clock pulses. In Fig. 8(c), we leave out an-other -to- converter and directly connect the capacitor to a resistor . One end of the resistor is grounded. and a constant current flow into the top of and , respec-tively. The capacitor and resistor were grounded periodi-cally by clock pulses. And we have the summing voltage at the top of . We can calculate the and as follows: (12) (13)
where is the time elapsed from the end of clock pulse in each cycle. Except the desired sum of current information and com-pensation ramp, here we have an extra term “ ” in . This extra term is a constant value and can be used as a dc bias to avoid falling into the nonlinear region of error amplifier output [11]. For different applications of converter design, we can simply adjust the values of and to change the com-pensation slope or current gain to have the desired result.
D. Over-Current Protection
Over-current protection is very important in power supply de-sign for safety reason. One of the benefits of current-mode con-trol is cycle-by-cycle current limitation. However, because of the minimization of the inductor and the higher slope of cur-rent ramp, the switching frequency goes higher. As a result, the over-current protection needs higher speed in response to ensure safety.
The conventional over-current protection compares the sensed current signal (in voltage) with a reference voltage [10], [12]. If the sensed signal is higher than the threshold, it turns off the main switch (In our case the main switch is the high side PMOS) with an over-current signal as shown in Fig. 9(a). The comparator delay was undesirable. In traditional voltage comparator design, for most circuit topology, the basic way to increase response speed is to increase operating current [13]. However, it is at the expense of power consumption and also conversion efficiency. Moreover, when the operating current goes higher, the speed of traditional voltage comparator will saturate due to the increase of parasitic capacitance and even larger operating current cannot help either.
To solve this problem, we propose a new over-current pro-tection circuit as shown in Fig. 9(b). As mentioned in the pre-ceding section, the is in current form. We utilize this char-acteristic of current sensing circuit and use a single transistor to achieve over-current protection. Note that the bias circuit lo-cated in left-down of Fig. 9(b) can be any simple bias circuit used by other circuits in the converter to generate a bias voltage
. From (4) and (5), we know that when
(14)
the drain voltage increases dramatically and the speed is deter-mined by the excess current and parasitic capacitance at drain node. Inherently, it operates faster than the conventional voltage comparator. Moreover, because the current sensing and bias cir-cuits are not newly created parts in the circuit, the quiescent cur-rent of the over-curcur-rent protection circuit is zero. As a result, the simple circuit deals with the comparator response speed and power consumption at the same time.
This circuit can be easily adjusted to fit various applications. As we know the value of and the aspect ratio of , we can easily adjust the aspect ratio of to reach the desired current
limit. Note that the (equals to ) must be
smaller than the logic threshold to avoid operating in triode region, or the current limit will be smaller than the expected value and cannot be well defined.
Fig. 9. Over-current protection circuit. (a) Conventional over-current protec-tion circuit. (b) Proposed over-current protecprotec-tion circuit.
IV. EXPERIMENTALRESULTS
All circuits described above are integrated in a monolithic current-mode buck converter and realized using a 0.6- m 1P2M logic CMOS process. Fig. 10 shows the microphotograph of the silicon chip. The whole chip area is 1.35 mm including the power MOSFETs and voltage reference circuit. The controller is measured 0.27 mm including frequency compensator and on-chip oscillator. It doesn’t need any pin-out and off-chip com-ponent for frequency compensation, voltage reference and clock
Fig. 10. Chip microphotograph.
Fig. 11. Experimental setup of the monolithic buck converter.
TABLE I
LIST OFCOMPONENTVALUESUSED INTESTSETUP
generator. The experimental setup is shown in Fig. 11. There are only six off-chip components needed, including bypass
ca-pacitor for , filtering inductor and capacitor
, resistors ( and ) for setting the output voltage and a small capacitor for compensation of the parasitic capac-itance at . The total PCB area was minimized. A typical set of component values is listed in Table I. Unless otherwise spec-ified, the following results are measured using the component values listed in Table I.
A. Soft-Start
The soft-start function has been tested. Fig. 12 shows the sim-ulated input current and output voltage waveforms for 2.5 ( 1000 mA) load at startup. Fig. 13 shows the measured input cur-rent and output voltage waveforms at startup. We can see the experimental results match the simulation prediction. The soft-start function with soft-soft-start time longer than 1.5 ms effectively suppresses the inrush current and overshooting of output voltage during startup. The measured soft-start time doesn’t change for various input voltage, output voltage and load current. It can be seen that both the input current and the output voltage follow the internal soft-start ramp until they reach the steady-state values.
Fig. 12. Simulated waveforms of input current and output voltage during startup with 2.5 load (1000 mA at steady-state).
Fig. 13. Measured input current and output voltage during startup with 2.5 load (1000 mA at steady-state). From top to bottom: Channel 3 is chip enable, Channel 1 is output voltage, and Channel 4 is input current.
B. Efficiency
The proposed converter incorporated with DPSS in both PWM and PFM mode gives very high conversion efficiency 88.5%) in a wide load range from 0.9 to 800 mA. The mea-sured efficiency is greater than 85.5% even at 1000 mA load. The results are shown in Fig. 14(a). Since we use a hysteresis switching algorithm for automatic PWM/PFM mode switching, the efficiency curves of PWM and PFM mode are overlapped over certain load range in Fig. 14. The maximum efficiency is over 96% at 60–200 mA load and peaks over 96.7% at 100 mA load under PWM mode. In PFM mode, the maximum efficiency is over 95% at 100–200 mA load.
Fig. 14(b) shows the measured conversion efficiency for 4.2 V. The efficiency still peaks over 96% for 120–200 mA load and is greater than 86% for 0.8–1000 mA load.
Fig. 14. Measured conversion efficiency. (a)V = 3.6 V and V = 2.5 V. (b)V = 4.2 V and V = 2.5 V.
C. Steady-State and Transient Response
In PFM mode, the measured quiescent current is 48.6 A with DPSS. The waveforms of PFM operation are shown in Fig. 15. The interval between two switching pulses is defined by load current. For heavier load, the switching pulses will get closer, and vise versa.
Fig. 16 shows the steady-state waveforms in PWM mode. It can be seen that the converter is stable without sub-harmonic os-cillation in both duty ratio greater and smaller than 50%. Ripples on output voltage are less than 3 mV. Measured line and load regulation are 0.07%/V and 0.08%/A, respectively. Transient re-sponse is shown in Fig. 17. The recovery time for a 500 mA step load-transient is less than 20 s for 1% (25mV) tolerance of the final settling value. The output voltage drops and peaks less than 80 mV ( 3.2% of the nominal value of output voltage 2.5 V) during the 500 mA load step-up and step-down transient, respectively.
D. Over-Current Protection
Fig. 18(a) shows the waveforms of output voltage and in-ductor current at 2.5 ( 1000 mA) load (normal operation). Fig. 18(b) shows the waveform of inductor current when over-loaded 1 . The proposed over-current protection circuit successfully limits the output current when overloaded. The cycle-by-cycle peak inductor current is limited to 1.28 A.
Fig. 15. Steady-state waveforms of PFM mode operation. From top to bottom: Channel 1 is output ripple voltage (ac coupled), Channel 4 is inductor current and Channel 2 is switch node LX: (a) 10 mA load and (b) 20 mA load.
E. Comparison
Table II summarizes the measured performance of the pro-posed converter. Table III shows a comparison with previously reported works [5], [29]–[32]. Incorporates with all the ad-vancements described above, our design features the smaller die size and controller size with fewer off-chip components, higher conversion efficiency and wider operating range. Small output ripple voltage and fast transient response are also in-cluded. Besides, on-chip soft-start and over-current protection functions ensured safety. All these features are realized in a low cost 0.6 m 1P2M logic CMOS process.
V. CONCLUSION
A compact high efficiency monolithic current-mode buck converter is presented in this paper. Novel features including on-chip soft-start, dynamic partial shutdown strategy, slope compensation and over-current protection circuits are demon-strated. These techniques reduce pin-outs and external compo-nents, upgrade efficiency, reduce circuit complexity and silicon
Fig. 16. Steady-state waveforms of the output ripple voltage (Channel 1, ac coupled) and the switch node LX (Channel 2) in PWM mode. (a) Duty cycle >50%. (b) Duty cycle <50%.
Fig. 17. 500 mA step load-transient response. Channel 1 is output voltage (ac coupled) and Channel 2 is output current (step from 200 to 700 mA and from 700 mA to 200 mA).
Fig. 18. Over-current protection test. From top to bottom: Channel 1 is output voltage (dc coupled), Channel 4 is inductor current and Channel 2 is switch node LX. (a) Normal operation with 2.5 (1000 mA) load. (V = 2.5 V). (b) The converter is overloaded(R = 1 ). The peak inductor current is limited to 1.28 A and the output voltage falls from 2.5 V to1.2 V.
TABLE II SUMMARY OFPERFORMANCE
area, ease design effort, ensure safety and can be applied to a wide operating range. The experimental results show that these novel features work well and the converter achieves very good
TABLE III PERFORMANCECOMPARISON
performance at many aspects. The proposed converter is suit-able especially for mobile devices that require high efficiency, small size, and safety operation.
REFERENCES
[1] L. Benini, A. Bogliolo, and G. De Micheli, “A survey of design tech-niques for system-level dynamic power management,” IEEE Trans.
Very Large Scale Integr. Syst., vol. 8, no. 3, pp. 299–299, Jun. 2000.
[2] H. Deng, X. Duan, N. Sun, Y. Ma, A. Q. Huang, and D. Chen, “Mono-lithically integrated boost converter based on 0.5-m CMOS process,”
IEEE Trans. Power Electron., vol. 20, no. 3, pp. 628–628, May 2005.
[3] S.-P. Hsu, A. Brown, L. Rensink, and R. D. Middlebrook, “Modelling and analysis of switching dc-to-dc converters in constant-frequency current-programmed mode,” in Proc. IEEE Power Electron. Spec.
Conf., Jun. 1979, pp. 284–301.
[4] S. W. Bryson, T. Wong, and B. C. Lombard, “Programmable Syn-chronous Step Down DC–DC Converter Controller,” U.S. Patent 5 943 27, Aug. 24, 1999.
[5] C. F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique,” IEEE J.
Solid-State Circuits, vol. 39, no. 1, pp. 3–14, Jan. 2004.
[6] C. Y. Leung, P. K. T. Mok, K. N. Leung, and M. Chan, “An integrated CMOS current-sensing circuit for low-voltage current-mode buck reg-ulator,” IEEE Trans. Circuits Syst. II, vol. 52, no. 7, pp. 394–394, Jul. 2005.
[7] J.-J. Chen, Y.-T. Lin, H.-Y. Lin, J.-H. Su, W.-X. Chung, Y.-S. Hwang, and C.-L. Tseng, “On-chip current sensing techniques for hysteresis current controlled DC-DC converters,” Electron. Lett., vol. 41, pp. 95–95, Jan. 2005.
[8] C.-H. Chang and R. C. Chang, “A novel current sensing circuit for a current-mode control CMOS DC-DC buck converter,” in Proc. IEEE
Int. Symp. VLSI Des. Autom. Test, Apr. 2005, pp. 120–123.
[9] H. P. Forghani-zadeh and G. A. Rincon-Mora, “Current-sensing tech-niques for dc–dc converters,” in Proc. 45th IEEE Midwest Symp.
Cir-cuits Syst., Aug. 2002, vol. 2, pp. 577–580.
[10] S. Chen and W. T. Ng, “High-efficiency operation of high-frequency DC/DC conversion for next-generation microprocessors,” in Proc.
IEEE Int. Conf. Ind. Electron. Soc. (IECON’03), Nov. 2003, vol. 1,
pp. 30–35.
[11] P. K. T. Mok, “Design of power management IC—Voltage reference, low-dropout regulator and switching regulator,” presented at the Mixed Signal IC Design Workshop, Hsinchu, Taiwan, R.O.C., Jun. 2005. [12] Y. C. Ryu and Y. W. Hwang, “A new soft-start method with abnormal
over-current protection function for switching power supplies,” in Proc.
IEEE Int. Conf. Elect. Mach. Drives, May 2005, pp. 421–425.
[13] R. Gregorian, Introduction to CMOS Op-Amps and Comparators. New York: Wiley, 1999.
[14] J. Rosales, DN365-ThinSOT switching regulator controls inrush
current. Los Angeles, CA: Linear Tech. Corp., Dec. 2005 [Online]. Available: http://www.linear.com/pc/downloadDocument.do?navId= D7838
[15] C.-S. Shieh, “Soft Start Techniques for Control Loops That Regulate DC/DC Converters,” U.S. Patent 6 933 710, Aug. 23, 2005.
[16] T. Sase, F. Murabayashi, and M. Kikuchi, “Soft Start Circuit for Switching Power Supply,” U.S. Patent 6 377 480, Apr. 23, 2002. [17] M. J. Callahan, Jr., “DC-to-DC Converter With Soft-Start Error
Am-plifier and Associated Method,” U.S. Patent 5 917 313, Jun. 29, 1999. [18] G. J. Smith, “Soft-Start Voltage Regulator Circuit,” U.S. Patent
6 969 977, Nov. 29, 2005.
[19] E. M. Solie, “Soft Start Precharge Circuit for DC Power Supply,” U.S. Patent 6 998 829, Feb. 14, 2006.
[20] T. Sheehan, “Versatile controller simplifies high voltage DC/DC con-verter designs,” Linear Technol. Mag., pp. 28–34, Sep. 2005. [21] R. W. Erickson and D. Maksimovic, Fundamentals of Power
Elec-tronics. Norwell, MA: Kluwer, 2001.
[22] B. Linares-Barranco and T. Serrano-Gotarredona, “On the design and characterization of femtoampere current-mode circuits,” IEEE J.
Solid-State Circuits, vol. 38, no. 8, pp. 1353–1353, Aug. 2003.
[23] E. M. Camacho-Galeano, C. Galup-Montoro, and M. C. Schneider, “An ultra-low-power self-biased current reference,” in Proc. Symp.
In-tegr. Circuits Syst. Design, Sep. 2004, pp. 147–150.
[24] T. Delbruck and A. van Schaik, “Bias current generators with wide dynamic range,” in Proc. IEEE Int. Symp. Circuits Syst., May 2004, vol. 1, pp. 337–340.
[25] B. A. Minch, “A low-voltage MOS cascode bias circuit for all current levels,” in Proc. IEEE Int. Symp. Circuits Syst., May 2002, vol. 3, pp. 619–622.
[26] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated
Circuits. New York: Wiley, 1993.
[27] Z. Lai and K. M. Smedley, “A general constant-frequency pulsewidth modulator and its applications,” IEEE Trans. Circuits Syst. I, vol. 45, no. 4, pp. 386–386, Apr. 1998.
[28] A. S. Sedra and K. C. Smith, “A second-generation current conveyor and its applications,” IEEE Trans. Circuits Syst., vol. CAS-17, no. 1, pp. 132–134, Feb. 1970.
[29] J. Kim and M. A. Horowitz, “An efficient digital sliding controller for adaptive power-supply regulation,” IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 639–647, May 2002.
[30] D. Ma, W.-H. Ki, and C.-Y. Tsui, “An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 140–140, Jan. 2004.
[31] J. Xiao, A. V. Peterchev, J. Zhang, and S. R. Sanders, “A 4-A quies-cent-current dual-mode digitally controlled buck converter IC for cel-lular phone applications,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2342–2342, Dec. 2004.
[32] M. Y.-K. Chui, W.-H. Ki, and C.-Y. Tsui, “A programmable integrated digital controller for switching converters with dual-band switching and complex pole-zero compensation,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 772–772, Mar. 2005.
Feng-Fei Ma was born in Taichung, Taiwan, R.O.C.,
in 1975. He received the B.S. degree from the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, in 1998 where he is currently pursuing the Ph.D. degree.
His current research interests include analog IC de-sign and power electronics IC dede-sign.
Wei-Zen Chen received the B.S., M.S., and Ph.D.
degree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1992, 1994, and 1999, respectively.
He worked for Industrial Technology Research Institute (ITRI), Hsinchu, on RF integrated circuit design in 1999. From 1999 to 2002, he was with the Department of Electrical Engineering, National Central University, Chung-Li, Taiwan. Since 2002, he has been with the Department of Electronics Engineering, National Chiao Tung University, where he is currently an Associate Professor. His research interests are integrated circuits and systems for high speed networks, and wireless communications.
Dr. Chen is a member of Phi Tau Phi.
Jiin-Chuan Wu was born on April 22, 1956. He
re-ceived the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1977 and the M.S. and Ph.D. degrees in electrical engineering from Carnegie Mellon University, Pitts-burgh, PA, in 1981 and 1986, respectively.
In 1988, he joined the Jet Propulsion Laboratory, NASA/Caltech, Pasadena, CA, where he was in-volved in the development of mass storage systems for spacecraft. In 1992, he joined the Electronics Engineering Department, National Chiao Tung University, Taiwan, R.O.C., where he is currently a Professor. His research interests include wireless communication IC design, analog IC design, high-speed digital IC design, and power electronics IC design.
