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Production Planning & Control: The Management of
Operations
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Control wafers inventory management in the wafer
fabrication photolithography area
S.-H. Chung a , W. L. Pearn a & H.-Y. Kang b a
Department of Industrial Engineering and Management , National Chiao Tung University , Taiwan
b
Department of Industrial Engineering and Management , National Chin-Yi Institute of Technology , Taiwan
c
Department of Industrial Engineering and Management , National Chiao Tung University , Taiwan E-mail:
Published online: 21 Feb 2007.
To cite this article: S.-H. Chung , W. L. Pearn & H.-Y. Kang (2005) Control wafers inventory management in the wafer fabrication photolithography area, Production Planning & Control: The Management of Operations, 16:3, 286-296, DOI: 10.1080/095372890500088001
To link to this article: http://dx.doi.org/10.1080/095372890500088001
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Vol. 16, No. 3, April 2005, 286–296
Control wafers inventory management in the
wafer fabrication photolithography area
S.-H. CHUNG*y, W. L. PEARNy and H.-Y. KANGz
yDepartment of Industrial Engineering and Management, National Chiao Tung University, Taiwan zDepartment of Industrial Engineering and Management, National Chin-Yi Institute of Technology, Taiwan
An important variable affecting the production throughput in the wafer fabrication photo-lithography area is the work-in-process (WIP) level of control wafers. Previous research work has focused on control wafers downgrading problem, and little work has been done for WIP level of control wafers. The objective of this paper is to develop methods for estimat-ing the WIP level of control wafers for each grade, while maintainestimat-ing the same level of production throughput. Two factors are considered, the re-entrant of control wafers within the same grade and the downgrading of control wafers among different grades. Under pulling control production environment, a multi-loop algorithm is developed for estimating the WIP control wafers for each grade. We conduct some simulation experiments based on a real-world factory production environment to demonstrate the effectiveness of the proposed algorithm. The results show that the algorithm is an efficient tool for estimating the cycle time and WIP level for each grade of control wafers.
Keywords: Photolithography area; Control wafers; Inventory; Multi-loop; Re-entrant; Downgrade
1. Introduction
In the wafer fabrication photolithography area, con-trol wafers are utilized for monitoring and measuring the particle content, measuring photo-resist coat thick-ness and uniformity, examining focus and de-focus, checking critical dimension, and inspecting overlaps (Lin 2000). The purpose of using control wafers is to assure that manufacturing process in a wafer fabri-cation can satisfy the required specififabri-cations. Control wafers are repeatedly used until their quality and thickness no longer conform to the process requirement. For control wafers that do not conform to the process requirements, they are either downgraded or discarded. To avoid pollution to factory machines due to the misuse of control wafers, managers often apply grade concepts of control wafers for diverse machine types according to the requests of processing circumstances,
such as the degree of quality. Any shortage of control wafers may result in a halt of machine operations and as a consequence, may seriously affect the process yield and production planning. To avoid such situations occurring, a large number of control wafers are usually prepared and stored for use. This, however, unnecessa-rily increases the WIP level of control wafers. For most factories, the work in process (WIP) level of control wafers is 30–50% of that for normal products, with 30% being the benchmark as indicated by Lin (2000).
Existing methods for estimating cycle time include the simulation approach, statistical regression approach, analytical method, and hybrid method. The pros and cons of these existing methods have been examined by several researchers (Lawrence 1995, Glynn and O’Dea 1997, Raddon and Grigsby 1997). Discrete event simulations are used to create shop floor condition and are a useful tool for performance prediction. The use of statistical regression approach with variance anal-ysis explores the relationship between cycle time and system variables to construct a cycle time forecasting
*Corresponding author. Email: shchung@mail.nctu.edu.tw
Production Planning & Control
ISSN 0953–7287 print/ISSN 1366–5871 online # 2005 Taylor & Francis Group Ltd http://www.tandf.co.uk/journals
DOI: 10.1080/095372890500088001
model. Wang et al. (1997) combined Little’s formula (Hiller 1995) with Kingman’s equation (Kleinrock 1975) to develop a regression function for estimating cycle time at each work station. Analytical method uses the queuing systems theory as a base to develop formulas for flow time estimation according to the distri-bution hypothesis on parameter setting. The hybrid method combines various methods to provide the cycle time estimation. Chung et al. (1999) studied analytical methods incorporating simulation techniques to develop a cycle time estimation method.
Spearman and Woodruff (1990) evaluated the Kanban’s CONWIP system and pointed out that CONWIP is a suitable pull system in many dynamic environments. Popovich et al. (1997) designed a re-use matrix that takes into account the contamination level of the used test wafers as well as other characteristics of wafers. This is useful in determining possible usage for the used wafers. Although the re-use process requires manual operation, it provides a less expensive alterna-tive to buying new wafers. Kroese and Nicola (1999) suggested a two-node tandem Jackson (1963) network model with simulation for general arrival and service system to estimate the ratio of overflow in the second buffer. Chen and Lee (2000) studied the effect of control/ dummy (C/D) wafers downgrading based on push or pull systems. They concluded that the pull system is preferred if machine delay time is the primary concern, whereas the push system leads to a better utilization of C/D wafers and a lower C/D wafers level. Kumar and Kumar (2001) introduced the queuing network models to analyse system performance of semiconduc-tor wafer fabrications. They surveyed some sequenc-ing rules and release policies used in semiconductor manufacturing.
Although these studies have provided some impor-tant information regarding the cycle time and WIP level estimation, there has been little research done on control wafers inventory management. The purpose of this paper is to present an algorithm for estimating the control wafers cycle time and the WIP level for each control wafer grade. Under the production control environment with a pulling system, a multi-loop control wafers (MCW) algorithm is developed, and the re-entrant and downgrade manufacturing factors to set the WIP level of control wafers for each grade are considered. This investigation provides a useful refer-ence to the management level for setting the WIP level for each grade and to increase inventory management performance. The remainder of this paper is organized as follows. Section 2 describes the control wafers man-agement problem and assumptions. Section 3 presents the construction of control wafers multi-loop man-agement system and describes the MCW algorithm.
In section 4, some simulation experiments are con-ducted, and the simulation results are presented to show the effectiveness of the proposed algorithm. In section 5, some conclusion remarks are made.
2. Problem description and assumptions
Control wafers are employed for monitoring machine parameters in the production process and for main-taining manufacturing conditions of semiconductor wafer fabrication. Control wafers are used not only to control the machine manufacturing capability, but also to increase the process yield. An increase in con-trol wafers WIP level would result in an increase in the holding cost but with a decrease in the shortage cost; therefore, a trade-off decision must be made. Most common decisions in current industrial practice often result in maintaining each grade of control wafers at its maximum service level. This paper attempts to determine appropriate WIP level of control wafers for each grade in the system. How to determine the optimal WIP level of control wafers for each grade is important to the performance of the inventory man-agement system. This paper considers a control wafers management problem where control wafers can be re-used in the same grade, downgraded for use in a different grade or discarded in the last grade. In order to simplify the complexity of the environment, we shall restrict our investigation of control wafers to the photolithography area in a wafer fabrication.
In general, the re-use status of control wafers can be divided into (1) pre-disposition, (2) in-use, and (3) recycle, termed the PUR process (Chen and Lee 2000). The in-use control wafers in the photolithography area provide functions for product monitoring, equipment monitoring, breakdown and recovery monitoring, and preventive maintenance (Lin 2000). In this paper, multi-loop system concept is applied to the establishment of the downgrade and PUR process.
A diagram of multi-loop control wafers system is depicted in figure 1. In figure 1, node Start contains new control wafers, node Finish is the discard wafers collection, and a01 is the new wafers depletion rate to
loop 1. Each loop can be considered as a neuron, and the jth loop can be considered as the jth grade of control wafers process. The depletion rate of jth grade control wafers is dj, re-entrant ratio is Pij (for i ¼ j),
downgrade ratio is Pij (for i < j), discard ratio is Pij
(for j ¼ D), and arrival rate is j. Figure 2 displays the
relationship between PUR and downgrade in the jth loop system of control wafers. In figure 2, the loop consists of three stages, and each stage consists of one
machine for processing. Xj1 represents the
pre-disposi-tion stage, Xj2 represents the in-use stage, and Xj3
represents the recycling stage. At the pre-disposition stage, operations must be completed to make sure that the control wafers comply with the manufacturing condition before they can be used. At the in-use stage, control wafers are employed in wafer fabrication to monitor and control some machine functions. After control wafers passing through the pre-disposition and in-use stages, they either enter the re-entrant state, or are downgraded or discarded. For the jth grade of control wafers, re-entrant arrival rate is ij (for i ¼ j),
downgrade arrival rate is ij (for i < j), discard rate
is jD, and arrival rate is j. If the control wafers enter
the re-entrant state, they will be repeatedly used and remain in the PUR process. Figure 3 is a specific case for the loop system shown in figure 2. It displays the relationship between PUR and new arrival rate in the 1st loop system of control wafers, where the new arrival rate of control wafers is a01.
The MCW algorithm developed here is based on the following assumptions:
. Daily demand rate for each grade is given. It is related to the schedule for normal product fabrication.
. Demand rate equals supply rate. In a pull system, when a control wafer is required in a grade, it will be pulled from the upper grade. With no shortage permitted, demand rate (dj)
should equal to supply rate (j). The interval time
between two pulls is set to 1/dj(1/j) for loop 2 and
loop 3.
. The process time in each machine is given. The
process of C/D wafers in a machine normally includes tasks such as the measurement of particle content, and the process time is usually a constant or normally distributed.
. Each PUR process consists of three stages of operation, and each stage has one machine to pro-cess corresponding operations, while the machine in the in-use stage is a dummy machine.
. Control wafers are classified into three grades.
. Control wafers with particle numbers of less than 100 in 1 m3are classed grade one, less than 500 in 1 m3are grade two, and less than 1000 in 1 m3are grade three.
. The safety inventory is set to 0 for loop 1 and to
1 lot for loop 2 and loop 3.
. The releasing batch size for control wafers is one lot. Loop 1 d1 Loop 2 d 2 Loop 3 d 3 λ 1 λ 2 λ11 = λ1×P 11 λ 3 λ 22=λ 2 × P22 λ33=λ 3 × P33 Finish Start Loop j d j λ 12 = λ 1 × P12 λ 13 = λ 1 × P13 λ 23=λ 2 × P23 λ 1D=λ 1 × P1D λ3D=λ 3 × P3D λ 2D=λ 2 × P2D λ jD=λ j × PjD 01 a λ D
Figure 1. The multiple loop control wafers system.
Loop j j 1 ij j 2 j j jj 1 jj+ 2 jj+ jD j 3 j X 1 j X 2 j X Pull Control j 1 j− λjj λ λ λ λ λ λ λ λ λ λ λ
Figure 2. The relationship of downgrade, pull control and PUR process in the jth loop system.
Loop 1 01 a 11 1 1 11 12 13 D 1 1 13 X 11 X 12 X Pull Control λ λ λ λ λ λ λ λ
Figure 3. The relationship of new control wafers, pull control and PUR process in the 1st loop system.
. The dispatching rule adopted is first-in, first-out (FIFO).
3. Control wafers inventory management system
This paper develops an MCW algorithm to estimate the most appropriate WIP level of control wafers for each grade. The proposed algorithm can be divided into two phases: (1) calculating new control wafers arrival rate, downgrade ratio and re-entrant ratio, and (2) esti-mating control wafers cycle time and WIP level for each grade.
The multi-loop system presented here can supply new control wafers in the 1st loop and downgrade control wafers to the jth loop (1<j). When supply and demand are in balance, we can calculate the new control wafers supply rate, the re-entrant control wafers arrival rate and the downgrade control wafers arrival rate. The cycle time for each grade of control wafers is calculated by adding up the downgrade waiting time, the re-entrant waiting time and the PUR process time for each grade of control wafers. The WIP level for each grade of control wafers is obtained by multiplying the arrival rate (consisting of new control wafers arrival and downgrade arrival)
and cycle time of control wafers. The estimation pro-cedures for the two phases are depicted in figure 4 and described in the next section.
3.1 Calculation of downgrade and re-entrant ratios The multi-loop system of control wafers is constructed by the downgrade and PUR process procedures. In the jth loop, the supply and depletion of control wafers continue repeatedly, and a balanced production and exhaustion multi-loop system is adequate to solve control wafer problems. In figure 2, when the jth loop declares a need of control wafers, control wafers can be supplied from the pre-disposition stage. The pre-disposition stage (Xj1) supplies downgraded
trol wafers to meet the demand. If the downgraded con-trol wafers are not sufficient to meet the demand, the first loop can pull new control wafers for use. However, for other loops, downgraded control wafers will be pulled from upper grade. In a stabilized system, the arrival rate of control wafers is equal to the leaving rate of control wafers. The relationship between re-entrant arrival ratio and downgrading arrival ratio can be found in Chung et al. (2004).
Given the demand rate :
Calculate the downgrading rate:
Calculate the re-entrant rate: Calculate the new control
wafers arrival rate:
Estimate downgrade waiting time: Estimate PUR process
time:
Estimate re-entrant waiting time:
Estimate the PUR cycle time for each grade:
Estimate the WIP level for each grade:
Process related data Product related data Machine related data Control rule parameter
Second phase First phase j
d
ij jj 01 a jPUR
DWT
jRWT
j jCT
jWIP
λ
λ
Figure 4. Flow process of the MCW algorithm.
The multi-loop system must supply enough control wafers for use in time, and shortage is not allowed. The operative constraints are as follows. By equation (1), the demand rate of control wafers is equal to the supply rate of control wafers for each loop. In the first loop, the supply rate of control wafers is equal to the new arrival rate of control wafers and the re-entrant rate, and this relationship is shown in equation (2). For other loops, the supply rate of control wafers is equal to the control wafers re-entrant rate and down-grade rates from up-stream loops, as shown in equation (3). The constraints are as follows:
dj¼j j ¼1, 2, . . . , c: ð1Þ j¼a01þ1P11 j ¼1: ð2Þ j¼X j i¼1 iPij j ¼2, . . . , c: ð3Þ where dj is the demand rate of control wafers per day,
jis the supply (arrival) rate of control wafers per day,
a01 is the supply rate of new control wafers per
day, Pij (i ¼ j) is the re-entrant ratio and Pij (i<j) is
the downgrading ratio.
3.2 Estimation of cycle time and WIP level
The cycle time of control wafers is defined to be the time interval from control wafers entering the jth loop system to leaving the jth loop system. Cycle time consists of downgrading waiting time, re-entrant waiting time and process time. They are defined as follows:
1. The downgrading waiting time: DWTj. The
down-grading waiting time is the time interval between downgrade arriving of control wafers and the pre-disposition of PUR process in loop j. In the first loop, new control wafers are pulled, and no down-grading waiting time is required. For loop 2 and loop 3, control wafers have to be pulled from the upper grade, not from new control wafers. The downgrading waiting time can be obtained by deducting the interval time (1/j) from the average
downgrading arrival time of the upper grade (1/j(1 Pjj)): DWTj ¼ 0 j ¼1 1 j 1 Pjj 1 j j ¼2, . . . c 8 < : ð4Þ
where (1 Pjj) is equal to the sum of
down-grading arrival rate (Pj1i¼1ij).
2. The re-entrant waiting time: RWTj. The re-entrant
waiting time is caused from control wafers
re-entrant arriving to in-use in the PUR process in loop j. The difference between re-entrant arrival time and in-use time is multiplied by the number of repeat times to estimate the re-entrant waiting time: RWTj ¼ k j 1 j1 1 j2 1 j3 Pjj 1 Pjj j ¼1, 2, . . . , c ð5Þ where jis the total arrival rate of the jth loop, jr
is the rth service rate of the jth loop, Pjj is
re-entrant ratio of the jth loop as 0 1 j1 þ 1 j2 þ 1 j3 1 j k ¼1 1 j 1 j1 þ 1 j2 þ 1 j3 2 j k ¼2 .. . n 1 j 1 j1 þ 1 j2 þ 1 j3 n j k ¼ n:
3. Theoretical process time: PURj. The theoretical
process time includes the PUR process time, load-ing and unloadload-ing time of control wafers in loop j. Process time is obtained by multiplying process service time by the number of repeat times.
PURj ¼ 1 j1 1 1 Pjj þ 1 j2 1 1 Pjj þ 1 j3 Pjj 1 Pjj j ¼1, 2, . . . , c: ð6Þ Cycle time for each loop j, CTj, equals the sum of
DWTj, RWTj and PURj (CTj¼DWTjþRWTjþ
PURj) and is calculated by equation (7):
CT j¼ 1 j1 1 1 Pjj þ 1 j2 1 1 Pjj þ 1 j3 Pjj 1 Pjj þ k j 1 j1 1 j2 1 j3 Pjj 1 Pjj j ¼1 1 j1 1 1 Pjj þ 1 j2 1 1 Pjj þ 1 j3 Pjj 1 Pjj þ k j 1 j1 1 j2 1 j3 Pjj 1 Pjj þ 1 j 1 Pjj 1 j ! j ¼2, . . . , c: 8 > > > > > > > > > > > > > > > > > > > > < > > > > > > > > > > > > > > > > > > > > : ð7Þ
The WIP level of a loop can be estimated by equations (8) and (9). The WIP level of loop j is
WIPj¼j 1 Pjj CTj j ¼1, 2, . . . , c ð8Þ j 1 Pjj ¼ a01 j ¼1 Xj1 i¼1 ij j ¼2, . . . , c 8 > < > : ð9Þ
where WIPj is the work-in-process in the jth loop
and CTjis the cycle time of the jth loop. The system
WIP level, WIPs, of control wafers is as follows:
WIPs¼
Xc j¼1
WIPj: ð10Þ
3.3 Algorithm procedures
The procedures of the MCW algorithm are as follows: Step 1. By equation (1) to (3), given the demand rate
(dj¼j), re-entrant arrival ratio Pjj and
downgrad-ing arrival ratio Pij, calculate the new control
wafers arrival rate a01, re-entrant arrival rate jjand
downgrading arrival rate ijfor each loop j.
Step 2. By equation (7), calculate cycle time (CTj)
of control wafers for the jth loop.
Step 3. By equations (8) and (9), calculate WIP level of control wafers for the jth loop.
Step 4. By equation (10), calculate WIP level of control wafers for the system.
4. Numerical example and simulation results
In order to justify the applicability of the proposed MCW algorithm, we consider some cases to investigate the effects of different demand rates on the system. We compare our estimated parameter values with the results obtained from simulations by eM-Plant simula-tion programming software (Teconmatix Technologies Ltd. 2000). The simulation horizon is set to 110 days, in which the first 10 days are a warm up period. In order to eliminate simulation errors, simulations with dif-ferent seeds are run ten times, and the average value of simulation results is used as the comparison object.
4.1 Basic system input
To investigate the effects of planning on the manage-ment system, actual data is taken from a wafer fabrica-tion factory located on the Science-Based Industrial
Park in Hsinchu, Taiwan. The basic information is as follows:
1. Demand rate. In the photolithography area, there are three grades of control wafers in the process. The demand rate per day for each grade (dj, j ¼ 1, 2, 3) is given.
2. PUR process. In each loop j, the in-use service is the bottleneck. The service rates are shown in table 1.
3. Machine data for the control wafers. The distribu-tion of the mean time between failures (MTBF ), the mean time to repairs (MTTR), the mean time between preventive maintenance (MTBPM) and the mean time to preventive maintenance (MTTPM) for each work station are known.
4.2 Numerical example
The cycle time of loop 1 with different demand rates and re-entrant ratios under MCW algorithm and sim-ulation are compared in table 2. The WIP level of loop 1 with different demand rates and re-entrant ratios by two methods are compared in table 3. Tables 4–7 show the information for other loops. The relationship of cycle time, demand rate and re-entrant ratio for loop 1 under MCW algorithm is depicted in figure 5, and that for simulation is shown in figure 6. The relationship of WIP level, demand rate and re-entrant ratio for loop 1 under MCW algorithm is depicted in figure 7, and that for simulation is shown in figure 8.
Figures 5 and 6 show very similar graphs obtained from MCW algorithm and from a simulation. When re-entrant ratio (P11) increases in loop 1, the cycle time
of control wafers in the loop increases too; thus, a posi-tive relationship between the two factors is present. Next, when demand rate (dj) increases, a greater
num-ber of control wafers are demanded, and the cycle time of control wafers in the loop decreases. From table 2, we can notice that the greatest difference in cycle times among different demand rates is (1.5 1.5 ¼ 0) when P11¼0, and the greatest difference in cycle times is
(44.7 25.5 ¼ 22.2) when P11¼0.9. From table 4, we
can notice that the greatest difference in cycle times
Table 1. The service rate for each process (unit: day). Loop j uj1 uj2 uj3
j ¼1 144 18 24
j ¼2 288 16 20
j ¼3 192 24 24
among different demand rates is (1.583 1.583 ¼ 0) when P22¼0, and the greatest difference in cycle times
is (66.383 42.083 ¼ 24.3) when P22¼0.9. From table 6,
we can notice that the greatest difference in cycle times among different demand rates is (1.125 1.125 ¼ 0) when P33¼0, and the greatest difference in cycle times
is (38.69 37.125 ¼ 1.565) when P33¼0.9. This means
that when the re-entrant ratio gets smaller, the cycle times among different demand rates will be closer.
Figures 7 and 8 show the relationship among re-entrant ratio, demand rate and WIP level. When the re-entrant ratio (P11) increases in loop 1, the WIP level
of control wafers in that loop also increases. When the demand rate (dj) increases, the WIP level in the
loop also increases. Therefore, a positive relationship is found both between re-entrant ratio and WIP level, and between demand rate and WIP level. Table 3 shows that the greatest difference in WIP levels among different demand rates is (1.125 0.625 ¼ 0.5) when P11¼0, and
the greatest difference in WIP levels is (1.913 1.863 ¼ 0.05) when P11¼0.9. From table 5, we can see that
the greatest difference in WIP levels among different
demand rates is (1 0.625 ¼ 0.375) when P22¼0, and
the greatest difference in WIP levels is (2.8 2.763 ¼ 0.037) when P22¼0.9. Table 7 also shows that
the greatest difference in WIP levels among different demand rates is (1.125 1.078 ¼ 0.047) when P33¼0,
and the greatest difference in WIP levels is (3.713 3.708 ¼ 0.005) when P33¼0.9. This indicates that
when the re-entrant ratio gets bigger, the WIP levels among different demand rates will be closer.
The relationships of the above factors for loop 2 and 3 also show that the results obtained from the MCW algorithm and from simulation are pretty similar.
4.3 Result analysis
The results of the MCW algorithm are compared with those of simulation. As shown in tables 2–7, the absolute percentage of discrepancy in cycle time estimation is between 0.008% and 4.324% among all cases in loop 1, between 0.005% and 1.227% in loop 2, and between 0.002% and 1.489% in loop 3. The absolute percentage
Table 2. The cycle time of 1st loop under MCW and simulation with demand rate¼ 10(1)18 and re-entrant ratio ¼ 0.0(0.1)0.9 (unit: hour).
Demand rate Ratio
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 MCW 1.500 2.033 2.700 3.557 4.700 6.300 8.700 12.700 20.700 44.700 Simulation 1.517 2.051 2.798 3.575 4.643 6.306 8.062 12.572 20.608 44.316 D.R. (%) 1.121 0.861 3.503 0.500 1.228 0.095 7.914 1.018 0.446 0.867 11 MCW 1.500 1.985 2.591 3.370 4.409 5.864 8.045 11.682 18.955 40.773 Simulation 1.517 2.001 2.708 3.442 4.525 5.869 8.047 11.917 18.883 40.455 D.R. (%) 1.121 0.807 4.324 2.088 2.562 0.091 0.019 1.973 0.379 0.785 12 MCW 1.500 1.944 2.500 3.214 4.167 5.500 7.500 10.833 17.500 37.500 Simulation 1.517 1.962 2.597 3.247 4.233 5.496 7.502 11.188 17.442 37.234 D.R. (%) 1.121 0.895 3.735 1.008 1.567 0.073 0.027 3.170 0.333 0.714 13 MCW 1.500 1.910 2.423 3.082 3.962 5.192 7.038 10.115 16.269 34.731 Simulation 1.517 1.927 2.517 3.086 4.007 5.197 7.032 10.404 16.221 34.503 D.R. (%) 1.121 0.869 3.732 0.116 1.135 0.090 0.092 2.774 0.297 0.660 14 MCW 1.500 1.881 2.357 2.969 3.786 4.929 6.643 9.500 15.214 32.357 Simulation 1.517 1.917 2.447 2.961 3.889 4.933 6.645 9.628 15.176 32.162 D.R. (%) 1.121 1.880 3.672 0.283 2.656 0.090 0.032 1.329 0.252 0.607 15 MCW 1.500 1.856 2.300 2.871 3.633 4.700 6.300 8.967 14.300 30.300 Simulation 1.517 1.862 2.378 2.888 3.618 4.704 6.303 8.918 14.268 30.130 D.R. (%) 1.121 0.346 3.280 0.574 0.424 0.085 0.048 0.546 0.224 0.564 16 MCW 1.500 1.833 2.250 2.786 3.500 4.500 6.000 8.500 13.500 28.500 Simulation 1.517 1.851 2.336 2.805 3.564 4.501 6.002 8.621 13.475 28.350 D.R. (%) 1.121 0.954 3.682 0.688 1.796 0.022 0.033 1.404 0.186 0.529 17 MCW 1.500 1.814 2.206 2.710 3.382 4.324 5.735 8.088 12.794 26.912 Simulation 1.517 1.828 2.282 2.735 3.433 4.323 5.731 8.273 12.773 26.778 D.R. (%) 1.121 0.781 3.336 0.911 1.475 0.012 0.075 2.233 0.165 0.500 18 MCW 1.500 1.796 2.167 2.643 3.278 4.167 5.500 7.722 12.167 25.500 Simulation 1.517 1.813 2.241 2.651 3.309 4.167 5.502 7.881 12.151 25.381 D.R. (%) 1.121 0.921 3.317 0.307 0.944 0.008 0.036 2.015 0.129 0.469
*The discrepancy ratio, D.R. (%), is defined as:ðMCW result simulation resultÞ=ðsimulation resultÞ 100%:
Table 3. The WIP level of 1st loop under MCW and simulation with demand rate¼ 10(1)18 and re-entrant ratio ¼ 0.0(0.1)0.9 (unit: lot).
Demand rate Ratio
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 MCW 0.625 0.763 0.900 1.038 1.175 1.313 1.450 1.588 1.725 1.863 Simulation 0.624 0.762 0.899 1.037 1.174 1.311 1.447 1.584 1.719 1.847 D.R. (%) 0.096 0.079 0.100 0.058 0.085 0.107 0.235 0.253 0.349 0.867 11 MCW 0.688 0.819 0.950 1.081 1.213 1.344 1.475 1.606 1.738 1.869 Simulation 0.687 0.818 0.949 1.081 1.212 1.343 1.472 1.603 1.732 1.854 D.R. (%) 0.087 0.079 0.063 0.060 0.074 0.086 0.204 0.228 0.318 0.785 12 MCW 0.750 0.875 1.000 1.125 1.250 1.375 1.500 1.625 1.750 1.875 Simulation 0.749 0.874 0.999 1.124 1.249 1.374 1.497 1.622 1.745 1.862 D.R. (%) 0.080 0.069 0.060 0.053 0.064 0.073 0.180 0.203 0.287 0.714 13 MCW 0.813 0.931 1.050 1.169 1.288 1.406 1.525 1.644 1.763 1.881 Simulation 0.812 0.931 1.049 1.168 1.287 1.405 1.524 1.641 1.758 1.869 D.R. (%) 0.074 0.070 0.057 0.056 0.062 0.068 0.098 0.186 0.262 0.661 14 MCW 0.875 0.988 1.100 1.213 1.325 1.438 1.550 1.663 1.775 1.888 Simulation 0.874 0.987 1.099 1.212 1.324 1.437 1.548 1.660 1.771 1.876 D.R. (%) 0.069 0.061 0.055 0.050 0.053 0.056 0.142 0.175 0.243 0.608 15 MCW 0.938 1.044 1.150 1.256 1.363 1.469 1.575 1.681 1.788 1.894 Simulation 0.937 1.043 1.149 1.256 1.362 1.468 1.573 1.679 1.784 1.883 D.R. (%) 0.064 0.062 0.052 0.052 0.051 0.051 0.127 0.158 0.224 0.566 16 MCW 1.000 1.100 1.200 1.300 1.400 1.500 1.600 1.700 1.800 1.900 Simulation 0.999 1.099 1.199 1.299 1.398 1.498 1.598 1.698 1.796 1.890 D.R. (%) 0.120 0.118 0.100 0.092 0.136 0.127 0.119 0.147 0.212 0.524 17 MCW 1.063 1.156 1.250 1.344 1.438 1.531 1.625 1.719 1.813 1.906 Simulation 1.062 1.156 1.249 1.343 1.436 1.529 1.624 1.716 1.809 1.897 D.R. (%) 0.057 0.056 0.048 0.048 0.125 0.121 0.074 0.137 0.193 0.498 18 MCW 1.125 1.213 1.300 1.388 1.475 1.563 1.650 1.738 1.825 1.913 Simulation 1.124 1.211 1.299 1.386 1.473 1.561 1.648 1.735 1.822 1.904 D.R. (%) 0.098 0.091 0.085 0.079 0.115 0.109 0.097 0.127 0.181 0.468
Table 4. The cycle time of loop 2 under MCW and simulation with demand rate¼ 10(1)16 and re-entrant ratio ¼ 0.0(0.1)0.9 (unit: hour).
Demand rate Ratio
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 MCW 1.583 2.383 3.383 4.669 6.383 8.783 12.383 18.383 30.383 66.383 Simulation 1.601 2.401 3.401 4.683 6.383 8.777 12.349 18.303 30.015 65.881 D.R. (%) 1.103 0.736 0.519 0.298 0.005 0.072 0.278 0.439 1.227 0.762 11 MCW 1.583 2.311 3.220 4.389 5.947 8.129 11.402 16.856 27.765 60.492 Simulation 1.601 2.328 3.233 4.402 5.952 8.124 11.374 16.794 27.574 60.076 D.R. (%) 1.103 0.747 0.411 0.306 0.085 0.059 0.242 0.370 0.693 0.693 12 MCW 1.583 2.250 3.083 4.155 5.583 7.583 10.583 15.583 25.583 55.583 Simulation 1.601 2.267 3.101 4.170 5.589 7.581 10.563 15.533 25.425 55.234 D.R. (%) 1.103 0.750 0.570 0.365 0.101 0.031 0.192 0.324 0.623 0.632 13 MCW 1.583 2.199 2.968 3.957 5.276 7.122 9.891 14.506 23.737 51.429 Simulation 1.601 2.217 2.985 3.972 5.283 7.119 9.877 14.467 23.603 51.131 D.R. (%) 1.103 0.825 0.571 0.379 0.139 0.039 0.142 0.272 0.568 0.584 14 MCW 1.583 2.155 2.869 3.787 5.012 6.726 9.298 13.583 22.155 47.869 Simulation 1.601 2.172 2.887 3.803 5.022 6.724 9.298 13.554 22.027 47.613 D.R. (%) 1.103 0.794 0.622 0.410 0.201 0.033 0.004 0.216 0.580 0.538 15 MCW 1.583 2.117 2.783 3.640 4.783 6.383 8.783 12.783 20.783 44.783 Simulation 1.601 2.133 2.807 3.653 4.797 6.382 8.777 12.758 20.685 44.560 D.R. (%) 1.103 0.766 0.843 0.343 0.285 0.021 0.072 0.199 0.475 0.501 16 MCW 1.583 2.083 2.708 3.512 4.583 6.083 8.333 12.083 19.583 42.083 Simulation 1.601 2.103 2.727 3.525 4.595 6.075 8.325 12.063 19.505 41.888 D.R. (%) 1.103 0.935 0.685 0.371 0.254 0.137 0.100 0.169 0.402 0.466
of discrepancy in WIP level for MCW and simulation is between 0.048% and 0.867% among all cases for loop 1, between 0.040% and 4.810% in loop 2, and between 0 and 0.317% in loop 3. The system WIP level is the sum
of WIP level for each loop, and the WIP level for a single loop can be obtained with the given demand rate and re-entrant ratio. The absolute percentage of discrepancy in system WIP level under MCW and
Table 5. The WIP level of loop 2 under MCW and simulation with demand rate¼ 10(1)16 and re-entrant ratio ¼ 0.0(0.1)0.9 (unit: lot).
Demand rate Ratio
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 MCW 0.625 0.863 1.100 1.338 1.575 1.813 2.050 2.288 2.525 2.763 Simulation 0.650 0.894 1.128 1.362 1.595 1.829 2.060 2.290 2.526 2.745 D.R. (%) 3.846 3.523 2.482 1.770 1.229 0.880 0.485 0.122 0.040 0.638 11 MCW 0.688 0.919 1.150 1.381 1.613 1.844 2.075 2.306 2.538 2.769 Simulation 0.716 0.953 1.181 1.408 1.634 1.862 2.087 2.311 2.540 2.754 D.R. (%) 3.967 3.634 2.608 1.893 1.340 0.969 0.561 0.201 0.087 0.554 12 MCW 0.750 0.967 1.183 1.400 1.617 1.833 2.050 2.267 2.483 2.700 Simulation 0.788 1.013 1.234 1.454 1.674 1.895 2.113 2.331 2.553 2.762 D.R. (%) 4.810 4.555 4.075 3.727 3.436 3.254 3.000 2.777 2.744 –2.234 13 MCW 0.813 1.031 1.250 1.469 1.688 1.906 2.125 2.344 2.563 2.781 Simulation 0.848 1.072 1.286 1.500 1.714 1.928 2.140 2.352 2.567 2.770 D.R. (%) 4.175 3.810 2.830 2.109 1.540 1.133 0.706 0.342 0.175 0.421 14 MCW 0.875 1.088 1.300 1.513 1.725 1.938 2.150 2.363 2.575 2.788 Simulation 0.914 1.132 1.339 1.547 1.754 1.961 2.167 2.372 2.581 2.777 D.R. (%) 4.256 3.889 2.920 2.211 1.631 1.208 0.771 0.405 0.213 0.364 15 MCW 0.938 1.144 1.350 1.556 1.763 1.969 2.175 2.381 2.588 2.794 Simulation 0.980 1.191 1.392 1.593 1.793 1.994 2.193 2.392 2.594 2.785 D.R. (%) 4.327 3.959 3.010 2.301 1.718 1.281 0.834 0.462 0.251 0.314 16 MCW 1.000 1.200 1.400 1.600 1.800 2.000 2.200 2.400 2.600 2.800 Simulation 1.045 1.250 1.444 1.638 1.832 2.025 2.220 2.413 2.607 2.793 D.R. (%) 4.334 3.977 3.054 2.314 1.725 1.230 0.896 0.518 0.284 0.269
Table 7. The WIP level of loop 3 under MCW and simulation with demand rate¼ 23(1)24 and re-entrant ratio ¼ 0.0(0.1)0.9 (unit: lot).
Demand rate Ratio
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 23 MCW 1.078 1.370 1.663 1.955 2.247 2.539 2.831 3.123 3.416 3.708 Simulation 1.078 1.370 1.663 1.954 2.246 2.538 2.829 3.121 3.413 3.696 D.R. (%) 0.007 0.001 0* 0.025 0.043 0.042 0.069 0.078 0.086 0.317 24 MCW 1.125 1.413 1.700 1.988 2.275 2.563 2.850 3.138 3.425 3.713 Simulation 1.125 1.412 1.700 1.986 2.273 2.560 2.847 3.133 3.421 3.701 D.R. (%) 0.027 0.021 0.024 0.060 0.079 0.090 0.091 0.150 0.120 0.303
*Denotes a value less than 0.001.
Table 6. The cycle time of loop 3 under MCW and simulation with demand rate¼ 23(1)24, and re-entrant ratio ¼ 0.0(0.1)0.9 (unit: hour).
Demand rate Ratio
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 23 MCW 1.125 1.589 2.168 2.914 3.908 5.299 7.386 10.864 17.821 38.690 Simulation 1.142 1.607 2.186 2.925 3.922 5.305 7.386 10.819 17.757 38.317 D.R. (%) 1.489 1.135 0.802 0.382 0.367 0.115 0.002 0.417 0.358 0.974 24 MCW 1.125 1.569 2.125 2.839 3.792 5.125 7.125 10.458 17.125 37.125 Simulation 1.142 1.587 2.142 2.851 3.805 5.137 7.127 10.419 17.067 36.784 D.R. (%) 1.489 1.106 0.794 0.411 0.350 0.234 0.028 0.378 0.340 0.927
simulation is less than 5%. Based on the above analysis, we can see that the proposed MCW algorithm performs quite well in estimating cycle time and WIP level for each control wafers grade.
5. Conclusions
In most wafer fabrications today, the WIP level of con-trol wafers is set to 30–50% of that for normal products, with 30% being the benchmark as indicated by Lin (2000). As the WIP level of control wafers increases, the capacity for processing normal products decreases. However, without the necessary control wafers utiliza-tion, the production process cannot be maintained effec-tively and the yield of product wafers is affected in consequence. In consequence, a decision must be made to minimize the total control wafer costs and to deter-mine the optimal inventory level of control wafers while maintaining the same level of production throughput.
Control wafers inventory management is a challenge to wafer fabrication, and estimating depletion rate
correctly for each grade becomes an important task. Demand rate and WIP level of control wafers are closely related to many factors such as throughput target, product mix and priority mix. In this paper, the MCW algorithm is proposed to estimate the control wafers WIP level for each grade. By estimating processing time, downgrading waiting time, and re-entrant wait-ing time for each PUR process, cycle time and WIP level for each grade can be determined. From the results obtained in the example, the MCW algorithm showed a promising performance estimating the depletion rate and WIP level. The percentage of discrepancy in system WIP level between the MCW algorithm and simulation result is less than 5%. The results showed that the pro-posed methodology is very accurate.
Future research could focus on different depletion cost for each grade of control wafers, to find the minimum cost curve as well as to achieve manufacturer’s planning target. In this research, only one machine is present in each work station, and how the model should be con-structed under the environment of multiple machines in work stations is our future research direction.
Figure 6. The cycle time of 1st loop under simulation with demand rate ¼ 10(1)18 and re-entrant ratio ¼ 0.0(0.1)0.9.
Figure 8. The WIP level of 1st loop under simulation with demand rate ¼ 10(1)18 and re-entrant ratio ¼ 0.0(0.1)0.9. Figure 7. The WIP level of 1st loop under MCW with demand rate ¼ 10(1)18 and re-entrant ratio ¼ 0.0(0.1)0.9.
Figure 5. The cycle time of 1st loop under MCW with demand rate ¼ 10(1)18 and re-entrant ratio ¼ 0.0(0.1)0.9.
Acknowledgement
This research is supported in part by Grant NSC91-2416-H-009-014.
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Dr. Shu-Hsing Chung is Professor of the Department of Industrial Engineering and Management, National Chiao-Tung University, Taiwan, ROC. She received her PhD degree in industrial engineering from Texas A&M University, College Station, TX, USA. Her research interests include production planning, scheduling, and cycle time estimation. She has published and presented research papers in the areas of production planning and scheduling for IC manufacturing.
Dr. Wen Lea Pearnis Professor of the Department of Industrial Engineering and Management, National Chiao-Tung University, Taiwan, ROC. He received his PhD degree in operations research from the University of Maryland, College Park, MD, USA. He worked for AT&T Bell Laboratories Switch Network Control and Process Quality Centers. He has published numerous papers in the areas of network optimization, machine scheduling, and process capability analysis.
Dr. He-Yau Kang is Associate Professor of the Department of Industrial Engineering and Management, National Chin-Yi Institute of Technology, Taiwan, ROC. He received his PhD degree in industrial engineering and management from National Chiao-Tung University. His research interests include production planning, scheduling, and performance evaluation.
