Logic Design Lab 邏輯設計實驗

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Logic Design Lab 邏輯設計實驗

Instructor: Kuan Jen Lin (林寬仁) E-Mail: [email protected]

Web: http://vlsi.ee.fju.edu.tw/teacher/kjlin/kjlin.htm

Room: SF 727B

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Textbook

Recommended Texts 編撰之講義

References

1. M. Morris Mano, “Digital Design,” Prentice Hall, 3^rdEdition 2. T. L. Floyd, “Digital Funcanentals with VHDL,” Prentice Hall.

3. www.cic.edu.tw 4. www.altera.com

5. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL,” Prentice Hall, 2003

6. Thomas & Moorby’s, “The Verilog Hardware Description Language,” 5th edition, KAP, 2002.

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Grading

兩人一組

每次實驗均須助教驗收，下次實驗前繳交實驗報告

每次驗收 (3%)

每次報告與基本驗收以外之實驗成果(3%)

共計12次實驗

期末個別上機測試(28%) （公開題庫）

曠課一次扣總分 10 分，滿 3 次即不及格

遲到一次扣總分 3 分，病假需有醫師之診斷證明

上課期間，使用電腦進行非關本課程之事者，每紀錄

一次，扣總分 10 分。

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Part 1: Solderless breadboard (麵

包板)

Goal: Use standard (fixed-function) IC to design digital circuits on solderless

breadboard.

Lab Room: SF550

Lab 1: Decision machine表決器

Lab 2: Frequency devider 除頻電路

Lab 3: BCD-counter and Display

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Part 2: Design with Verilog HDL

Goal: Design circuit with HDL and use CAD tool to synthesize and simulate the design.

Lab Room: SF 742

Lab 4: Verilog Introduction

Lab 5: Quatus II (CAD tools) (Draw schematic & use HDL)

Lab 6: Basic combinational circuit module: MUX, decoder, encoder

Lab 7: Basic Arithmetic combinational circuit: A 4-bit Adder-subtractor

Lab 8: Latch and Flip-flip

Lab 9: Counter

Lab 10: shifter and Johnson counter

Lab 11: State machine

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Part 3: Prototyping design on CPLD(FPGA) with UP2 board

Goal: Prototype your digital design on a CPLD(FPGA) board

Lab Room: SF 742

Lab 12: Sequence detector

Lab 13: Digital timer

Lab 14: Traffic light

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IC Packages

Source: Floyd, Digital Fundamentals with VHDL, Fig. 1-28

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SMT Package Configuration

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Pin Numbering

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IC Function and Parameters

Function

TTL series

Performance characteristics

Propagation delay time

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Fixed-Function ICs’ Pin Configuration

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Partial Data Sheet for a 74HC00 (Quad 2- Input NAND Gate)

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DC Characteristics

V_IH(V_IL): input high (low) voltage

V_OH (V_OL): output high (low) voltage

I_IH (I_IL): input high (low) current

I_OH (I_OL): output high (low) current

I_CCH(I_CCL): Total supply current when the output is high (low).

Note the range: min, typ, max

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Performance (AC) Characteristics

Propagation delay time = (t_PHL+ t_PLH)/2

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Power Dissipation

I_CCL(I_CCH): The supply current for the low (high) output state

P = Vcc x (I_CCH+I_CCL)/2

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IC Technologies

High speed MOS 0.17

8 74HC00

Advanced S 8

3 74AS00

Advanced LS 1.3

3.5 74ALS00

High-speed 22

6 74H00

Schottky 19

3 74S00

LP Schottky 3.75

9.5 74LS00

Low-power 1

33 74L00

Standard TTL 10

10 7400

Characteristics Power

dissipation (mW) Propagation

delay (ns) Logic family

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Fan-out and Loading

Fan-out: the maximum number of inputs of the same series in an family that can be connected to a gate’s output an still maintain the output voltage levels within specified limits

I_OH/ I_IH

I_OL/I_IL

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Printed Circuit Board

Source: Floyd, Digital Fundamentals with VHDL

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Solderless breadboard

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Logic Design with Verilog

g2 B A

g1

~D C

g3

~D

~B

g4 C A

g5 p1

p2

p3

p4

eSeg

C e

B

D A

eSeg

modulebinaryToESeg (input A, B, C, D, outputeSeg);

nandg1 (p1, C, ~D);

nandg2 (p2, A, B);

nandg3 (p3, ~B, ~D);

nandg4 (p4, A, C);

nandg5 (eSeg, p1, p2, p3, p4);

endmodule

Schematic

Verilog structural description

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Logic Design with Verilog (Behavioral description)

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Design creation and simulation using

EDA tools (Quatus II)

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UP2 Block Diagram

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PLD (Programmable Logic Device)

Source: Mano, Digital Design, 3th edition.

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Types of PLDs

Source: Mano, Digital Design, 3th edition.

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FLEX 10K Device block diagram

Source: Altera

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Logic Element

Source: Altera

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Logic Design Lab 1:

Decision machine

Room: SF 727B

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實驗目的

練習設計組合邏輯電路之方法，並使用標準 IC，在麵包板上實現之。

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Design Procedures for Combinational Circuits

From the specification, determine the number of input/output variables and assign a letter symbol to each.

Derive the truth table that defines the required relationships between inputs & outputs.

Obtain the simplified Boolean function for each output.

Draw the logic diagram Function

Select appropriate ICs to realize the circuit

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3-input Decision machine

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Logic Circuit

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IC (integrated Circuit)

SSI (Small Scale IC): gate number <=10

MSI (medium Scale IC): 10 <gate number <=100

LSI (Large Scale IC): 100 < gate number <=1000

VLSI (Very Large Scale IC) : gate number > 1000

不同製程技術

TTL ：速度較快，面積較大

CMOS：速度較慢，面積較小

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Standard ICs

7400

7410

Function table

注意VCC 與GND的位置^，接腳輸入或輸出方向^。

Source: http://www.alldatasheet.com/

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IC Family and Characteristics

High speed MOS 0.17

8 74HC00

Advanced S 8

3 74AS00

Advanced LS 1.3

3.5 74ALS00

High-speed 22

6 74H00

Schottky 19

3 74S00

LP Schottky 3.75

9.5 74LS00

Low-power 1

33 74L00

Standard TTL 10

10 7400

Characteristics Power

dissipation (mW) Propagation

delay (ns) Logic family

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IC Characteristics

Propagation delay:

T_pd=(t_PLH+t_PHL)/2

Power dissipation per gate:

P_d=(V_cc(I_CCH+I_CCL)/2)/G (per gate)

Max fanout

the number of gate inputs that a gate output can connect to

I_OH/I_IH= I_OL/I_IL

Source: Floyd, Digital Fundamentals with VHDL 10

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麵包板

＋極和－極整列相連

每行的a ~ e及f ~ j相連接

使用0.5mm 單心線

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電阻值

第一位數第二位數指數容許誤差

20%

± 5% 10%

容許誤差

-2 -1 7

6 5 4 3 2 1 指數10^x x= 0

9 8 7 6 5 4 3 2 1 第二位數 0

9 8 7 6 5 4 3 2 1 第一位數 0

無色銀金白灰紫藍綠黃澄紅棕黑顏色

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注意事項

接線與安插元件時，關掉電源

電源供應器勿超過5V

麵包板上，電源線 (紅色)與接地線(藍色)勿短路

瞭解IC腳位

LED（二極體）正負端勿接反(長腳為正）。

指撥開關ON代表短路。

使用正確之電阻

LED：限流10mA~30mA

TTＬ：高電位直接輸入，接1k～10K電阻

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問題與討論

為何連接LED之電阻選用330Ω，而連接IC輸入端之電阻使用10KΩ之電阻？

請使用本實驗IC實現一個3-input XOR function。

利用成本接近之IC，來完成本實驗電路 (只需畫出電路即可)。

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實驗報告撰寫 (1/2)

限用A4 邏輯設計實驗報告

實驗名稱：表決器設計

學生：王大公 918888990

李小門 918000000

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實驗報告撰寫 (2/2)

一、實驗目的二、實驗器材三、實驗內容四、實驗結果五、問題與討論

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Logic Design Lab 2:

Frequency Divider

Room: SF 727B

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實驗目的

瞭解循序邏輯電路，熟悉計數器使用方法，用以設計除頻電路。

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4-bit Binary Counter with Parallel Load (74163)

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Waveform of 4-Bit Synchronous Counter

Clock

QA

QB

QC

QD

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Mod 10 (Divide-by-10) Waveform

QD and Clear both are divide-10 wave

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Circuit Diagram

Correct

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Use carry out (mode 12)

Source: Mano, Logic Design, 3th edition, Problem 6-22

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Construct a counter that counts from 0 to 64 (mod 65)

Source: Mano, Logic Design, 3th edition, Problem 6-20.

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問題與討論

1. 請利用IC 74163設計出一個除8的除頻器(畫出電路圖即可)。

2. 實驗結果我們所得除頻之duty cycle並非為1 比1，請問要如何使duty cycle為1比1？

3. 請利用數個IC 74163設計出一個除100的除頻器(畫出電路圖即可)

今日完成驗收3者可加分。

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Logic Design Lab 3:

BCD Counter and 7-Segment Displayer

Room: SF 727B

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實驗目的

瞭解循序邏輯電路，熟悉BCD 計數器原理與使用方法，並使用七段LED顯示器來顯示計數數值。

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Circuit Diagram

BCD counter 7-Segment LED controller

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BCD Ripple

counter (Fig. 6-10)

Source: Mano, Logic Design, 3th edition, Fig. 6-10.

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Synchronous BCD counter (Fig. 6-15)

Source: Mano, Logic Design, 3th edition, Fig. 6-15.

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BCD counter (7490)

(Ripple & Synchronous )

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BCD counter (7490)

‧JK未接者視為接地。

‧為何使用兩個clock 訊號?

‧Q2 clock係Q1 (ripple)

‧Q2, Q3, Q4 係synchronous

‧Q3何時為1? 此counter如何從9歸0?

Source:

http://www.alldatasheet.com/

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BCD Counter Waveform

Clock / CP0 Q0 /CP1

Q1

Q2

Q3

1 2 3 4 5 6 7 8 9 10

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Multi-digit BCD counter

Q3 (本圖之Q8) 作為下一級之clock (CP0)

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7 Segment LED

5V

共陽 (共陰)

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BCD-To-7-Segment Decoder

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問題與討論

參考Fig.3-3真值表，畫出IC 7447的電路圖。

請將此次實驗電路的IC 7490改由IC 74163實現，畫

出電路圖即可。

七段顯示器有共陰及共陽兩種，請說明此兩種七段顯

示器有何區別，如何辨識？

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Logic Design Lab 4 Verilog—introduction Logic Design Lab 4 Logic Design Lab 4 Verilog

Verilog— — introduction introduction

Instructor:

Instructor: KuanKuanJen Lin (Jen Lin (林寬仁林寬仁)) E-E-Mail: Mail: [email protected][email protected] Web:

Web: http://vlsi.ee.fju.edu.tw/teacher/kjlin/kjlin.htmhttp://vlsi.ee.fju.edu.tw/teacher/kjlin/kjlin.htm Room: SF 727B

Room: SF 727B

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Use CAD Tools to design and verify logic circuits

• Create design – Draw schematic

– Use HDL (e.g. Verilog), like C programming

• Verify design: give test patterns, and check if outputs meet specification.

– Simulation

• Graphical input/ouput

• Embedded test_modules in HDL programs

– Emulation (Prototyping):

• FPGA/CPLD

• Discrete components

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What is an HDL?

• A Hardware Description Language (HDL) is a high level programming language with special language constructs used to model the function of

hardware logic circuits.

• The special language constructs provide you the ability to:

– Describe the connectivity (structure) of a circuit – Describe the functionality (bhavior) of a circuit – Describe a circuit at various levels of abstraction – Describe the timing information and timing constraints

of a circuit

– Express concurrency

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Why Use an HDL?

• Model the design in higher level of abstraction

– Reduce the design capturing effort – Easy for handling complex design

– Separate from implementation, increase the protability – Potential for design re-use

• Mix behavioral/structural descriptioms in adesign

– Model datapath and regular portion of circuit structurally

– Model control and regular portion of circuit behaviorally

• Model the design and testbench with the same language

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Overview of Verilog Module

• A verilog module includes the following parts:

module module_name(port_name) ;

Port declaration

Data type declaration Task and function declaration

Functionality and structure Timing specification

endmodule

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Structural Description (An SR Latch)

name of the module

Port declaration Type declaration

primitive gates with names and interconnections type and delay of

primitive gates

module nandLatch (q, qBar,set, reset);

ouput q, qbar;

input set, reset;

nand #2

g1 (q, qBar, set), g2 (qBar, q, reset);

endmodule

A module is defined

g1

g2

q qBar set

Reset

Not for synthesis!

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Structural Description (A combinational circuit)

module binaryToESeg (input A, B, C, D, outputeSeg);

nandg1 (p1, C, ~D);

nandg2 (p2, A, B);

nandg3 (p3, ~B, ~D);

nandg4 (p4, A, C);

nandg5 (eSeg, p1, p2, p3, p4);

endmodule

g2 B A

g1

~D C

g3

~D

~B

g4 C A

g5 p1

p2

p3

p4

eSeg

C e

B

D A

eSeg

Gate output is an implicit wires

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Verilog Operator (PP. 152)

modulebinaryToESeg (A, B, C, D, eSeg);

input A, B, C, D;

outputeSeg;

wire p1, p2, p3, p4;

assign p1= c & ~D;

assign p2= A & B;

assign p3=~B & ~D;

assign p4=A & C;

assign eSeg= ~(p1 & p2 & p3 & p4)

// assign eSeg = (c & ~D) | (A & B) | (~B & ~D)

| (A & C);

endmodule

g2 B A

g1

~D C

g3

~D

~B

g4 C A

g5 p1

p2

p3

p4

eSeg

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A behavioral Model of BinaryToESeg

module

binaryToESeg_Behavioral (input A, B, C, D,

outputregeSeg);

always@(A, B, C, D) begin eSeg =1;

if (~A & D) eSeg=0;

if (~A & B & ~C) eSeg = 0;

if (~B & ~C & D) eSeg = 0;

end endmodule

1 1 1 1

1 1 0 0

0 1 0 0

1 1 0 1

AB CD eSeg

C-like

Procedural statements Sensitive list

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Behavioral modelling

• A behavioral model of a module is an abstraction of how the module works.

• alwaysÆ defines a process

– Suspend execution of this “always process”

until a change occurs one of variable in the sensitive list.

• Procedural statement – C programming-like

– Conversely, structural descriptions are concurrent statements.

• Within an “always” process, the left side of “=“ must be declared as register.

– Register does not always need a physical storage.

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Verilog 程式結構

module name signal 宣告

assign ……

always@(...) begin

…….

end

always@(...) begin

…………..

end

Concurrent running

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Why use behavioral descrption?

• Use behavioral model on early design stage.

–HDLs are designed originally for simulation

• Write testbench

• Partial behavioral descriptions can be synthesized to circuits.

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Create a Testbench For a Module

testbench

Test Generator And Monitor

Design Under Test (DUT)

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module_testBench

module testBench;

wire w1, w2, w3, w4, w5;

binaryToESeg d (w1, w2, w3, w4, w5);

test_bToESeg t (w1, w2, w3, w4, w5);

endmodule

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Test module

module test_bToESeg

(output regA, B, C, D, input eSeg);

initial // two slashes introduce a single line comment begin

$monitor( $time,,

"A = %b B = %b C = %b D = %b, eSeg = %b", A, B, C, D, eSeg);

//waveform for simulating the nand lip lop

#10 A = 0; B = 0; C = 0; D = 0;

#10 D = 1;

#10 C = 1; D = 0;

#10 $finish;

endendmodule

0 A = x B = x C = x D = x, eSeg = x 10 A = 0 B = 0 C = 0 D = 0, eSeg = x 12 A = 0 B = 0 C = 0 D = 0, eSeg = 1 20 A = 0 B = 0 C = 0 D = 1, eSeg = 1 22 A = 0 B = 0 C = 0 D = 1, eSeg = 0 30 A = 0 B = 0 C = 1 D = 0, eSeg = 0 32 A = 0 B = 0 C = 1 D = 0, eSeg = 1

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Interconnection of Design and Test Modules

testbench

Test Generator And Monitor

Design Under Test (DUT)

eSeg A B C D

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Standard Model of a Moore FSM

00/0 01/1

11/0 0

1 0

0 1 1 reset

Comb.

Circuit

State Registers

Output Input

Comb.

Circuit

Z D Q

clk

D Q clk

~Q1

Q0 Q0

x

x Q1

clk reset

//D flip-flop

module D_FF(D, Q, CLK, RST);

input D, CLK, RST;

output Q;

reg Q;

always @(posedge CLK or negedge RST)

if(~RST) Q = 1'b0;

else Q = D;

endmodule

module state_machine(x, reset, clk, z);

input x, Reset, clk;

output z;

wire D1, D0;

assign z =~Q1 &Q0;

assign D1 =Q0 &x;

assign D0= x | Q1;

D_FF A1(D1, Q1, clk, reset);

D_FF A0(D0, Q0, clk, reset);

endmodule

Z D Q

clk

D Q clk

~Q1

Q0 Q0

x

x Q1

clk reset

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Continuous assignment

• Continuous assignments provide a means to abstractly model combinational hardware driving values onto nets.

• always@(Q1, Q0) z=~Q1 & Q0;

e.g. assign a = (b & c) | (~a & d); // bitwise logic assign a = b+c; //arithmetic

assign a = b >> 2; //shift

assign z = ~Q1 & Q0;

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behavioral model of FSM

module fsm (output reg z,

input x, clk, reset

reg [1:0] curStste, nextStste;

always @(x, curState) begin z=~curState[1] & curState[0];

nextState=0;

if (curState ==0)

if (x) nextState=1;

if (curState ==1)

if (x) nextState=3;

if (curState ==3)

if (x) nextState=3;

else nextState =1;

end end

00/0 01/1

11/0 0

1 0

0 1 1 reset

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D_FF

always @(posedge clk, negedge reset) begin if (~reset)

curState = 0;

else

curState = nextState;

end endmodule

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Model hardware concurrency

• Verilog is a parallel HDL.

• Model HW concurrency:

– Continuous assignment assign v = x + y + z;

– Procedural block

always @(posedge c or d) begin v = c +d + e;

w = m –n;

end

– Note: Any continuous assignment can be rewritten as a procedural block.

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Nondeterminism

• When multiple processes execute

simultaneously, how these processes are scheduled?

• Example 1:

– Execute in zero time.

– Different order of execution gives different but correct results.

always @(d) q = d;

assign q = ~d;

Two processes

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Nonblocking assignment

• Use nonblocking assignment to remove the race.

• Scheduling of nonblocking assignments sample the values of the variables on the right-hand side at the moment the assignment is encountered, and assigns the result to the left-side variables at the end of the current simulation time.

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Non-blocking assignment (cont.)

module D_FF (D, CLK, Q);

input D, CLK;

output Q;

reg Q;

always @(posedge CLK) Q = D;

endmodule

module D_FF (D, CLK, Q);

input D, CLK;

output Q;

reg Q;

always @(posedge CLK) Q <= D;

endmodule

D Q

clk

D Q

clk

1 0 1

D_FF dff1(D, CLK, q1);

D_FF dff2(q1, CLK, Q);

D Q

這兩行敘述對調某些模擬器會有不同結果

q1

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Module Hierarchy

board

Display driver

m16 m555

A counter example clk count

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Top module

module boardWithConcatenation;

wire clock, eSeg, w3, w2, w1, w0;

m16 counter ({w3, w2, w1, w0}, clock);

m555 clockGen (clock);

binaryToESeg disp (eSeg, w3, w2, w1, w0);

initial

$monitor ($time,,,"count=%d, eSeg=%d", {w3, w2, w1, w0}, eSeg);

endmodule instantiate

Bus concatenation

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m16 (Counter)

module m16

(output reg [3:0] ctr = 1, input clock);

always @(posedge clock) ctr <= ctr + 1;

endmodule

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A clock generator (simulation)

module m555

(output reg clock);

initial

#5 clock = 1;

always

#50 clock = ~ clock;

endmodule

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Identifier

• A sequence of letters, digits and underscore (_) except that:

– The first character must not be a digit

• Upper and lower case letters are considered to be different

• Escaped identifiers: allow for any printable ASCII character.

– Start with “\”, terminate with white space.

\bus-index

\a+b

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Constants

3’b001 792 10’d17

12’b00001111_1100 12’h7d9

12’o3456

size binary value

可加入_， Improve readability

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module _4bit_adder (S,C4,A,B,C0);

input [3:0] A,B;

input C0;

output [3:0] S;

output C4;

wire C1,C2,C3; //Intermediate carries //Instantiate the fulladder

fulladder FA0 (S[0],C1,A[0],B[0],C0);

endmodule

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Rules for Synthesizable Combinational Circuits

• All inputs to your combinational function must be listed in the sensitive list.

• Combinational output(s) must be assigned to every control path.

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Example: Mux2to1

module Mux2to1 ( input a, b, c,

output reg f);

always @( a, b ,c) if (a == 1)

f = b;

else f = c;

endmodule

always @( *)

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Example: Mux2to1 (cont.)

module Mux2to1 ( input a, b, c,

output reg f);

always @(*) begin f = c;

if (a == 1) f = b;

end

endmodule

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Inferred Latches

amodule

synAutoSensitivity (

input a, b, c, output reg f);

always @(*) if (a == 1)

f = b & c ; // else f = ? endmodule

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Use case Statement

• Using Case Statement

–Using full_case (attributes)、 explicitly specify (truth table form) or a default item to fully specify.

–Specify Don’t Care situations for input and output.

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Use case Statement (cont.)

• Truth table method – List each input

combination

– Assign to output(s) in each case item.

module fred (output reg f, input a, b, c);

always @ (a or b or c) case ({a, b, c})

3’b000: f = 1’b0;

3’b001: f = 1’b1;

3’b010: f = 1’b1;

3’b011: f = 1’b1;

3’b100: f = 1’b1;

3’b101: f = 1’b0;

3’b110: f = 1’b0;

3’b111: f = 1’b1;

endcase endmodule

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39

Use case Statement (cont.)

module fred

(output reg f,

input a, b, c);

always @(a or b or c) case({a,b,c})

3’b000: f = 1’b0;

3’b101: f = 1’b0;

3’b110: f = 1’b0;

default: f = 1’b1;

endcase endmodule

40

Don’t care in Synthesis

• Rules

– You can’t say

“if (a == 1’bx)…”

this has meaning in simulation, but not in synthesis.

– However, an unknown x on the right-handside will be interpreted as a

don’t care. The inverse function was implemented;

x’s taken as ones.

00 01 11 10 0

1 ab c

1 1

1

1 1

x 0

x

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41

Specify don’t care (cont.)

module caseExample(

(output reg f, input a, b, c);

always @ (a or b or c) case ({a, b, c})

3’b001: f = 1’b1;

3’b010: f = 1’b1;

3’b011: f = 1’b1;

3’b100: f = 1’b1;

3’b110: f = 1’b0;

3’b111: f = 1’b1;

default: f = 1’bx;

endcase endmodule

42

Rules for Synthesizable Sequential Circuits

• The sensitive list includes only the edges of the clock, reset and preset conditions.

• Inside the always block, the reset and preset conditions are specified first.

– if (~reset),,,,

• Any register assigned to in the sequential always block will be implemented using flip- flops.

• The “<=“ states that all the transfers in the whole system that are specified should occur concurrently.

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43

Latch inferences

module synLatchReset( Q, g, d, reset);

input g, d, reset;

output Q;

reg Q;

always @(*) if (~reset)

Q = 0;

else if (g) Q = d;

// else Q = ? endmodule

• To infer a latch, two situations must exist in the always statement:

– At least one control path must exist that does not assign to an output.

– The sensitivity list must not contain any edge-sensitive specifications. (level- sensitive )

44

Flip Flop inferences

module synDFF( q, clock, d);

input clock, d;

output q;

reg q;

always @(posedge clock, negedge reset, posedge set)

begin if (~reset)

q <=0;

else if (set) q <=1;

else q <=d;

endmoduleend

• The form of the description must follow these rule :

– Always statement must specify the edge for each signal.

– The first statement follow the always must be if.

– procedural assignments must either be blocking or non-blocking

assignment.

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45

Conclusion

Required – from the presence of an edge specifier, the tool infers a flip flop. All registers in the always block are clocked by the specified edge.

No affect.

Inferred flip flop

Not allowed.

There must exist at least one control path where an output is not assign to. From this

“omission,”the tool infers a latch.

Interred latch

Not allowed. The whole input set must be in the sensitivity list.The construct @(*) assure this.

An output must be assigned to in all control path Combinational

Edge Specifiers in Sensitivity List Output Assign To

Type of Logic

46

Lexical convention (1/2)

• White space -> ignored

• Comments – // single line

– /* multiple lines */

• Value:

– <size><base><value>: 8’b10100011, 8’hA3 – <base><value>: ‘h83a

– <value>: 626

• Real value & strings used in writing testbench

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47

Lexical convention (2/2)

• Identifiers

– Letters, digits, $, _

– The first character shall be a letter or _.

• Escaped identifier – Start with \

– Let you use “illegal” charater – Ex. \4:1MUX

• Special token:

– Start with $ : system task, $monitor – Start with # : delay specification, #10 – Start with ` : compiler directives

• `define, `include, `timescale

48

Four-Valued Logic

• Verilog Logic Values

– The underlying data representation allows for any bit to have one of four values

– 1, 0, x (unknown), z (high impedance)

– x — one of: 1, 0, z, or in the state of change

• There is no real gate that drives an x on to a wire.

– z — the high impedance output of a tri-state gate.

.

Nand 0 1 x z

0 1 1 1 1

1 1 0 x x

x 1 x x x

z 1 x x x

A 4-valued truth table for a Nand gate with two inputs

Input A

Input B A

B

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49

Data type --Net

• wire– modeling a standard net

– wire #3 x2; // a net x2 having a delay

• Other types:

50

Implicit declaration

• If an identifier appears in the connection list of an instance of a gate primitive, module, or on the left-hand side of a continuous assignment, it will implicitly be declared a net.

• If the net is connected to a module port, its default width will be that of the port declaration. Otherwise, it will be a scalar. By default, the type of an implicit declaration is wire.

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51

Data type--register

• reg – reg a;

– reg [7:0] a; //specify a range, also used in net – reg [7:0] table [0:31] // 2³²x 8 memory

– reg [8:1] table [31:0][15:0];

• integer – integer a

• real – float a

• time – time a

52

Describing Mealy FSM(1/3)

• Example

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53

Describing FSM(2/3)

module Mealy_md1 ( x, y, CLK, RST);

input x, CLk, RST;

output y;

reg [1:0] Prstate, Nxtstate;

parameter S0=2’b00, S1=2’b01, S2=2’b10, S3=2’b11;

// DFF

always @ (posedge CLK or negedge RST)

if (!RST ) Prstate=S0;

else Prstate = Nxtstate;

//Output function

always @ (Prstate or x ) case (Prstate)

S0: y=0;

S1: if (x) y=1’b0;

else y= 1’b1;

S2: if (x) y=1’b0;

else y= 1’b1;

S3: if (x) y=1’b0;

else y= 1’b1;

// y = (x) ? 1’b0:1’b1 ; endcase

54

Describing FSM(3/3)

//next state function always @ (Prstate or x )

case (Prstate)

S0: if (x) Nxtstate=S1; else Nxtstate = S0;

// Nxtstate = (x) ? S1:S0 ; endcase

endmodule

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55

Operators (1)

• Are all Verilog operators synthesizable?

• Conditional operators

e.g. assign a = c ? x : y ;

• Shift operators

e.g. assign a = b << 2;

• Arithmetic operators

e.g. assign a = b+c;

assign a = b-c;

assign a = b*c;

assign a = b/c;

assign a = b%c;

Writing test bench or in process, do not use assign.

56

Operators (2)

• Logic operators : return a value.

&&, ||, !

assign a = b && c;

• Bitwise logic operators : return result in bus form.

&, |, ~,

assign a[2:0] = b[2:0] & c[2:0];

• Equality operator: ==, !=

• Reduction operator: a = &b;

• Relational operator: >=, > , <=, <

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Department of Electronic Engineering, FJUQuartusII (CAD Tools)

邏輯設計實習

Lab 5：Quartus II (CAD Tools)

實驗目的

藉由 draw schematic 與edit Verilog HDL file 設計一個 4- bit adder 使大家熟悉 Quartus II (CAD Tools) 的使用。

2

Field Programmable Gate Array (FPGA)

Complex Programmable Logic Device (CPLD)

FPGA consists of an N x N array of PLB and programmable I/O blocks, connected by a programmable interconnect network.

Programmable Logic Blocks

Programmable I/O Blocks

Programmable Interconnect

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3

Configuration Memory

4

Configuration Memory

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5

Simplified Block Diagram of a CLB (XC4000-Family FPGA by Xilinx)

Logic function of F’, G’ and

H1 G4

G3 G2 G1

F4 F3 F2 F1

S/R control

G’H’

DINF’

G’H’

H’

F’

DINF’

G’H’

H1 DIN S/R EC C1 C2 C3 C4

G’

F’

(clk)K

SD RD D Q EC

SD RD D Q

EC 1

YQ

XQ

X 1

Y Logic

Function of G1-G4

Logic Function of F1-F4

6

FPGA Configuration

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7

Altera: The Programmable Solutions Company^®

Programmable Devices

Design Software

Intellectual Property (IP)

8

Programmable Logic Families – High & Medium Density FPGAs

• Stratix^™II, Stratix, APEX^™II, APEX 20K, & FLEX^®10K – Low-Cost FPGAs

• Cyclone^™& ACEX^®1K – FPGAs with Clock Data Recovery

• Stratix GX & Mercury^™ – CPLDs

• MAX^®7000 & MAX 3000 – Embedded Processor Solutions

• Nios^™, Excalibur^T™

– Configuration Devices

• EPC

Introduction to Altera Devices

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9

Introduction to Altera Design Software

Software & Development Tools:

– Quartus II

• Stratix II, Stratix, Stratix GX, Cyclone, APEX II, APEX 20K/E/C, Excalibur, &

Mercury Devices

• FLEX 10K/A/E, ACEX 1K, FLEX 6000, MAX 7000S/AE/B, MAX 3000A Devices

– Quartus II Web Edition

• Free Version

• Not All Features & Devices Included

– MAX+PLUS^®II

• All FLEX, ACEX, & MAX Devices

10

Quartus II Operating Environment