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Analysis of Temperature Effects on High-Frequency Characteristics of RF Lateral-Diffused
Metal–Oxide–Semiconductor Transistors
View the table of contents for this issue, or go to the journal homepage for more 2008 Jpn. J. Appl. Phys. 47 2650
(http://iopscience.iop.org/1347-4065/47/4S/2650)
Analysis of Temperature Effects on High-Frequency Characteristics
of RF Lateral-Diffused Metal–Oxide–Semiconductor Transistors
Hsin-Hui HU, Kun-Ming CHEN1, Guo-Wei HUANG1, Alex CHIEN2, Eric CHENG2, Yu-Chi YANG2, and Chun-Yen CHANGDepartment of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan
1National Nano Device Laboratories, Hsinchu 300, Taiwan 2United Microelectronics Corporation, Hsinchu 300, Taiwan
(Received October 1, 2007; accepted November 16, 2007; published online April 25, 2008)
In this work, the effects of temperature on the DC and RF characteristics of lateral-diffused metal–oxide–semiconductor (LDMOS) transistors were studied. Devices with different layout structures were fabricated using a 40 V LDMOS process. The temperature coefficients of the threshold voltage and channel mobility are negative and their values are similar for devices with fishbone and ring structures. In addition, we found that both the cutoff frequency ( fT) and the maximum oscillation frequency ( fmax) decrease with increasing temperature. The variations of fTwith different temperatures are not only affected by the change in transconductance but also affected by the drain resistance. Finally, the temperature behaviors of S-parameters were measured, and the ring structure showed less S22 variation with different temperatures than the fishbone structure. We extracted the model parameters of the devices to explain this observation. [DOI:10.1143/JJAP.47.2650]
KEYWORDS: cutoff frequency, layout structure, LDMOS, maximum oscillation frequency, S-parameters, temperature
1. Introduction
Lateral-diffused metal–oxide–semiconductor (LDMOS) transistor technology has played a predominant role in wireless base-station applications for frequencies ranging from 450 MHz to 2.7 GHz owing to its advantages in performance, cost, reliability, and power capability.1) For high-power applications, temperature is an important issue. The cutoff frequency ( fT) and maximum oscillation fre-quency ( fmax) are critical figures of merit for evaluating the performance of RF transistors. For conventional MOS transistors in RF applications, the temperature effect was investigated by studying the temperature dependence of fT, which is proportional to the transconductance.2) With an increase in temperature, the fTand fmaxhave been shown to decrease. According to its structure, the parasitic drain resistance of the LDMOS becomes more important than that of the conventional MOS field-effect transistor (MOSFET) for the present drift region. However, in most of the studies, the effect of the parasitic resistance was not considered when analyzing the temperature effect on the device character-istics.2–4)By de-embedding the effect of the parasitic source and drain resistors from the measured S-parameters, the temperature dependence of the intrinsic fT can be analyzed. Several researchers have investigated the effects of temper-ature on the reliability and dc performances of LDMOS transistors.5–7)However, the temperature effects on the high-frequency characteristics of LDMOS have seldom been addressed.
In this work, the DC and high-frequency characteristics of LDMOS transistors with different layout structures were studied at various temperatures. From the DC characteristics, we found that fishbone and ring structures have similar variations in threshold voltage and channel mobility for different temperatures. However, the measured S-parameters of the two structures show different temperature behaviors. Electrical parameters have been extracted to describe the temperature behavior of the transistors. In addition, the variations of fT and fmax with different temperatures were also investigated. The LDMOS transistors with different
layout structures have different drain resistances.8)In order to eliminate the effect of drain resistance, the intrinsic fTwas extracted from the de-embedded S-parameters. The results of extrinsic and intrinsic fT variations with temperature are compared.
2. Experiments
The RF LDMOS transistors used in this study were fabricated using a 40 V LDMOS process. The schematic cross section of the device is shown in Fig. 1. The drain region was extended under the field oxide (FOX) and consisted of a lightly doped N-well drift region and an N region with higher doping doses for on-resistance control. The source region and the p-body were tied together to eliminate extra surface bond wires to reduce the source inductance and improve the RF performance in a power amplifier configuration.9) The gate oxide thickness was 135 A˚ and the mask channel length (LCH) was 0.5 mm. The drift length (LDrift¼LOVþLFOX) was fixed at 3.6 mm in this investigation. The LDMOS transistors were designed with two types of layout structures, as shown in Fig. 2. In the ‘‘fishbone’’ structure, all the gate fingers are divided into several subcells, in each of which 6 gate fingers are grouped together with a finger width (LF) of 10 mm. To achieve a lower on-resistance and a more compact device, we adopted a ‘‘ring’’ structure in the layout design. All the rings were arranged as a 3 3 array in one device. In each ring, the source region was surrounded by the drain region, while the
Fig. 1. (Color online) Schematic cross section of an LDMOS transistor. Vol. 47, No. 4, 2008, pp. 2650–2655
gate was located between the source and the drain. The width of each gate ring, which is defined at the center of the channel region, was 4 10 mm. To compare the perform-ances of the fishbone and ring structures fairly, both structures had the same total channel width (W ¼ 360 mm). Additionally, the contact placement in the ring structure corresponded to that in the fishbone structure. Because the effective width of the drift region in the ring structure is larger than that in the fishbone structure, the ring structure has a lower drain resistance.8)
The DC characterization of the test devices was per-formed using an HP4156 semiconductor parameter analyzer. To characterize the high-frequency performance, the S-parameters were measured on-wafer from 0.1 to 10 GHz for different temperatures using an HP8510 network analyzer and then de-embedded by subtracting the OPEN dummy. Different control biases were applied from an HP4142B source measure unit.
3. Results and Discussion 3.1 DC characteristics
The DC characteristics of the LDMOS transistor with different layout structures at 0 and 50C are compared in Fig. 3. At low gate voltages (VGS< 1 V), the transconduc-tance (gm) and drain current at 50C are higher those that at 0C owing to the decrease in the threshold voltage. At high gate voltages, because the channel mobility decreases with increasing temperature, the gm and drain current at 50C become lower than that at 0C. In low- and medium-bias regions, the ring structure showed a higher drain current and gmthan the fishbone structure. For a high drain bias (VDS ¼28 V), the drain current and extrinsic gm had zero-temperature-coefficient biases near VGS¼1:3 V and VGS¼1 V, respectively. The zero-temperature-coeffi-cient bias point results from the negative temperature coefficients of both the effective mobility and threshold voltage.6)
Figure 4 shows the threshold voltage plotted against temperature. The threshold voltage variations are 1:66 and 1:68 mV/C for the fishbone and ring structures, respec-tively. The values in the literature vary from 1 to 4 mV/ K with the most frequently noted value of 2 mV/K for the conventional complementary MOS (CMOS).10) For the LDMOS transistors, the threshold voltage variation in our
study is smaller than the proposed values of 5:2 mV/C,6) 3:2 mV/K,11) and 2:8 mV/C.12) This results from the lighter doping in the double-diffused channel.
The extracted channel mobility for different temperatures is shown in Fig. 5. The LDMOS channel mobility was deducted from the first-order one-dimensional model in the
(a) (b)
Fig. 2. (Color online) LDMOS layout structures: (a) fishbone and (b) ring. 0 1 2 3 4 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 0 5 10 15 20 25 30 35 VDS=28V Transconductance (mA/V)
Drain Current (A)
Gate Voltage (V) Fishbone_0°C Fishbone_50°C Ring_0°C Ring_50°C (a) 0 5 10 15 20 25 30 35 0 10 20 30 40 50 60 70 80 Fishbone_0°C Fishbone_50°C Ring_0°C Ring_50°C
Drain Current (mA)
Drain Voltage (V) VGS=1V VGS=2V VGS=3V VGS=4V (b)
Fig. 3. (Color online) (a) Subthreshold and (b) output characteristics of LDMOS transistors with different layout structures at 0 and 50C.
-60 -40 -20 0 20 40 60 80 100 120 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 -1.66mV/°C -1.68mV/°C Threshold Voltage (V) Temperature (°C) Fishbone Ring
Fig. 4. (Color online) Threshold voltage variation with temperature for different layout structures.
linear mode.6) This method is applicable for low drain voltages. The temperature dependence of the channel mobility can be modeled as ¼ 0 ðT=T0Þm, where m ¼ 1:35 for the fishbone structure and 1:36 for the ring structure. For intermediate inversion layer concentrations [N ¼ ð0:5 { 5Þ 1012cm3] at room temperature, the pho-non-scattering-limited channel mobility has been observed to be dependent on N and T (ph/TnN1=), where ¼ 3 { 6 and n ¼ 1{1:5.13)Therefore, the mobility in our devices is dominated by the phonon scattering.
3.2 Cutoff frequency and maximum oscillation frequency The cutoff frequency ( fT) and maximum oscillation frequency ( fmax) versus the gate voltage for the LDMOS transistors at various temperatures are shown in Fig. 6. We calculated the maximum stable gain/maximum available gain (MSG/MAG) and short-circuit current gain (h21) from the S-parameters. The fT and fmaxwere determined to be the frequencies at which the current gain was 0 dB and the MAG was 0 dB, respectively. As shown in Fig. 6, the ring structure has better high-frequency performance than the fishbone structure owing to a lower drain resistance.8) In addition, both fT and fmax decrease with increasing temperature for the two structures. The degradations of fT and fmax are attributed to the lower gm, as shown in Fig. 7. The variations in fT and intrinsic gm are 17 and 20%, respectively at VGS ¼2 V, as temperature changes from 25 to 50C. Because the temperature dependence of fmaxis also affected by the drain resistance (Rd) and drain–substrate junction capacitance (Cjdb), the variation in fmax is approximately 15%. It should be noted that the fT and gm have zero-temperature-coefficient bias points near VGS¼1 V. In Fig. 7, at a higher gate voltage, both the intrinsic and extrinsic gmvalues of the ring structure are lower than those of the fishbone structure owing to the self-heating effect. Owing to the series resistance, the intrinsic gm for the two
structures was higher than the extrinsic gm. The variation in both the intrinsic and extrinsic gm values are approximately 20% at VGS¼2 V as temperature changes from 25 to 50C. However, the variation changes to 17% for the fishbone structure and 15% for the ring structure at a high gate voltage (VGS¼4 V). The higher gate voltage leads to severe surface scattering and lowers the effective mobility. As the gate voltage increases, the effect of surface scattering is more prominent resulting in smaller changes in gm and also in fT and fmax with temperature.
Figure 8 shows the variations in extrinsic and intrinsic fT values versus the variation in intrinsic gmat VGS¼2 V when temperature changes from 25C. The usual approximate relation of extrinsic fT and intrinsic gm can be expressed as follows:14) fT¼ g0m0 2 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðC0 gsþCgdÞ2 1 þ rd R0 dskR0sub 2 ðg0 m0Cgs0 R0gsCgdÞ2 s ; ð1Þ 0.1 1 10 100 1000 Channel Mobility (cm 2 / (V· ·s)) Temperature (K)/300 Fishbone Ring
Fig. 5. (Color online) Temperature dependence of channel mobility for different layout structures.
1.0 1.5 2.0 2.5 3.0 3.5 4.0 2 4 6 8 10 12 Fishbone fT Frequency (GHz) Gate Voltage(V) -25°C 0°C 25°C 50°C fmax Ring
Fig. 6. (Color online) Cutoff frequency and maximum oscillation fre-quency versus gate voltage at various temperatures.
1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.005 0.010 0.015 0.020 0.025 0.030 0.035 Extrinsic T ransconductance (A/V) Gate Voltage (V) -25o C 0oC 25oC 50oC VDS=28V Intrinsic Ring Fishbone
Fig. 7. (Color online) Extrinsic and intrinsic transconductances versus gate voltage at various temperatures for different layout structures.
where g0
m0¼gm0=ð1 þ gm0RsÞ. The extrinsic fT in eq. (1) was extrapolated assuming a 20 dB/decade roll-off for the short-circuit current gain jh21j. Rgs refers to the channel resistance and leads to an additional term related to the gmin the denominator. The sign of this term in the denominator is negative, making the slope of the extrinsic fT variation versus the intrinsic gm variation larger than 1. This is contradictory to our measured results in Fig. 8(a). Moreover, in eq. (1), the small-signal equivalent circuit can be viewed as a dual-feedback circuit in which Rs is the local series–
series feedback element and Cgd is the local shunt–shunt feedback element.14)Even though R
smakes the extrinsic gm smaller than the intrinsic gm by a factor of 1=ð1 þ gmRsÞ, it also decreases Cgs and Cgd by the same factor and thus should not affect fT.
In LDMOS, however, the effect of drain parasitic resistance is also important, which is ignored in eq. (1). Tasker and Hughes reported a more rigorous derivation for the short-circuit current gain of a FET that takes source and drain resistance into account:15)
fT¼
gm
2fðCgsþCgdÞ ½1 þ ðRSþRdÞ=Rds þCgdgm ðRSþRdÞg
; ð2Þ
According to eq. (2), the sign of the term related to the gmin the denominator is positive, making the slope of the fT variation versus the intrinsic gm variation smaller than 1. In Fig. 8(a), the extrinsic fT includes the effects of source and drain resistances and the values of the curve slope are smaller than 1. This might be attributed to the effect of (RsþRd) being more prominent than the effect of Rgs. Furthermore, the fishbone and ring structures we studied here have difference drain resistances, resulting in the distinct values of the curve slopes in Fig. 8(a). To eliminate
the effect of parasitic resistance, the intrinsic fT was extrapolated after de-embedding the effect of the parasitic resistors from the measured S-parameters. As shown in Fig. 8(b), the curve slopes of the intrinsic fTvariation versus the intrinsic gmvariation for the fishbone and ring structures are quite similar (0.95 for fishbone and 0.94 for ring) and approach 1.
Figure 9 shows the variation in the extrinsic fmax versus the variation in the intrinsic gm at VGS¼2 V when temper-ature changes from 25C. The approximate relation of the extrinsic fmax and intrinsic gm can be expressed as follows:16) fmax fT ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 4gDSRgþ8 fTCgdðRgþRdÞ p ; ð3Þ
The intrinsic gmdependence of fmaxcomes about through the fT we mentioned above. The positive relation of fT in the denominator results in a lower value for the curve slope in Fig. 9 than that in Fig. 8(a). In addition, the parasitic drain resistance in the denominator indicates that the Rd has a larger effect on fmax. Therefore, the ring structure, which has a lower drain parasitic resistance, shows more improvement on fmax than fT.
3.3 S-parameters characteristics
Figure 10 shows the measured and simulated S-parame-ters of the fishbone and ring structures at various
temper--10 -5 0 5 10 15 20 -10 -5 0 5 10 15 20 VGS=2V, VDS=28V Extrinsic fT (%) Intrinsic Transconductance (%) Fishbone Ring Fishbone: slope=0.84181 Ring: slope=0.94085 (a) -10 -5 0 5 10 15 20 -10 -5 0 5 10 15 20 Intrinsic fT (%) Intrinsic Transconductance (%) Ring: slope=0.93838 Fishbone: slope=0.94856 Fishbone Ring VGS=2V, VDS=28V (b)
Fig. 8. (Color online) (a) Extrinsic fT and (b) intrinsic fT variations
versus intrinsic transconductance variation when temperature changes from 25C. -10 -5 0 5 10 15 20 -8 -4 0 4 8 12 16 Extrinsic fmax (%) Intrinsic Transconductance (%) Fishbone: slope=0.75841 Ring: slope=0.73295 Fishbone Ring V GS=2V, VDS=28V
Fig. 9. (Color online) Extrinsic fmax variation versus intrinsic
transcon-ductance variation when temperature changes from 25C.
atures. The transistors were measured at VGS¼2 V and a drain voltage (VDS) of 28 V for the maximum value of fT. In order to demonstrate the temperature dependence of the S-parameters, the model parameters of the small-signal equivalent circuit of the LDMOS transistors were extracted. The simulated results are also shown in Fig. 10. As illustrated in Fig. 10, the deviation of S11 with temperature is not marked. This suggests that the input impedance is affected by temperature slightly. Because the gm decreases with increasing temperature, both S21 and S22 change significantly. At low frequencies, S21 can be approximated by17)
S21¼ 2 g0mRL ZO ZOþRd
; ð4Þ
where ZO¼50 and RL¼RDSk ðRdþZOÞ. It is propor-tional to gm. However, at low frequencies, S12¼2sC0gd ZO is only related to the gate-to-drain capacitance (Cgd). Therefore, S21changed significantly owing to the decrease in gm, and S12 showed minor changes owing to the slight variation in Cgdwith increasing temperature. It is interesting that the temperature-induced variation in S22 in the ring
structure is lower than that in the fishbone structure. Figure 11 shows the measured and simulated results of jS22j for the fishbone and ring structures. The extracted Rd and Cjdb of the ring structure are 7.8 and 149 fF, respectively, which are lower than those of the fishbone structure (the extracted Rd and Cjdb are 18 and 244 fF, respectively).8) This is a possible reason for the lower S22 variation in the ring structure with different temper-atures.
4. Conclusions
The effects of temperature on the DC and high-frequency characteristics of RF LDMOS transistors were investigated in this study. The transconductance, threshold voltage, and channel mobility decrease with increasing temperature. The decrease in transconductance degrades the fT and fmax at high temperatures. Owing to the higher drain resistance in the LDMOS transistors, the fT is also affected by drain resistance. After de-embedding the effect of drain resistance, the temperature-induced fT variation is almost proportional to the gm variation. In addition, we found that the temperature dependence of fmax is also affected by the drain resistance and drain–substrate junction capaci-tance. Finally, we discussed the measured S-parameters at various temperatures. Because the LDMOS transistors with the ring structure have a lower drain resistance and a lower drain–substrate junction capacitance, the variation in S22 with temperature is smaller than that in the fishbone structure.
Acknowledgements
The authors would like to thank the staff of UMC for their helpful comments and the staff of the High Frequency Technology Center in NDL for measurement support. This work was supported in part by the R.O.C.’s National Science Council through contract NSC96-2221-E-492-014.
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