IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 4, APRIL 2012 471
LDMOS Transistor High-Frequency Performance
Enhancements by Strain
Kun-Ming Chen, Guo-Wei Huang, Bo-Yuan Chen, Chia-Sung Chiu, Chih-Hua Hsiao,
Wen-Shiang Liao, Ming-Yi Chen, Yu-Chi Yang, Kai-Li Wang, and Chee Wee Liu
Abstract—The effects of mechanical stress on the dc and high-frequency performances of laterally diffused MOS (LDMOS) transistors with different layout structures were investigated by using the wafer bending method. A 3.1% peak cutoff frequency (fT) enhancement is achieved for the multifinger device under
0.051% biaxial tensile strain. For LDMOS with annular layout, the fT enhancement is increased to 3.7% due to the various
channel directions. Our results suggest the strain technology can be adopted in LDMOS for RF applications. The transconductance and gate capacitance were also extracted to clearly demonstrate the fT variations.
Index Terms—Annular layout, biaxial tensile strain, cutoff fre-quency, laterally diffused MOS (LDMOS), mechanical stress.
I. INTRODUCTION
T
HE RAPID growth of wireless communication prod-uct markets has created a huge demand for low-cost, high-efficiency, and good-linearity radio-frequency (RF) power amplifiers. Among power devices, laterally diffused MOS (LDMOS) transistors are the most attractive in cost and po-tential improvements in performance and integration. LDMOS transistors have been widely used in RF power amplifier mod-ules for a high-frequency range up to 3.8 GHz [1]–[3]. Recently, CMOS device improvements with mechanical strain have pro-duced large IC performance gains [4]–[7]. The strain on the Si channel can be induced by using process technology (e.g., silicon nitride cap, SiGe source/drain, and SiGe buffer layer) and/or by bending the Si wafer directly.In the case of LDMOS transistors, the strained Si channel upon a relaxed SiGe buffer layer was presented by Kondo
Manuscript received December 7, 2011; accepted December 28, 2011. Date of publication February 7, 2012; date of current version March 23, 2012. This work was supported in part by the R.O.C.’s National Science Council through contracts NSC99-2221-E-492-027-MY2. The review of this letter was arranged by Editor W. T. Ng.
K.-M. Chen, B.-Y. Chen, C.-S. Chiu, and C.-H. Hsiao are with the National Nano Device Laboratories, Hsinchu 30078, Taiwan (e-mail: kmchen@ndl. narl.org.tw; bychen@ndl.org.tw; cschiu@ndl.org.tw; chhsiao@ndl.org.tw).
G.-W. Huang is with the National Nano Device Laboratories, Hsinchu 30078, Taiwan and also with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan (e-mail: gwhuang@ ndl.org.tw).
W.-S. Liao is with the Faculty of Physics and Electronic Technology, Hubei University, Wuhan 430062, China (e-mail: wsliaoumc@yahoo.com.tw).
M.-Y. Chen, Y.-C. Yang, and K.-L. Wang are with the United Micro-electronics Corporation, Hsinchu 300, Taiwan (e-mail: m_y_chen@umc.com; y_c_yang@umc.com; kai_li_wang@umc.com).
C.-W. Liu is with the National Nano Device Laboratories, Hsinchu 30078, Taiwan and also with the Department of Electrical Engineering, National Taiwan University, Taipei 10617, Taiwan (e-mail: chee@cc.ee.ntu.edu.tw).
Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2011.2182494
Fig. 1. Layout structures of LDMOS cell. (a) Multifinger. (b) Annular ring. The black arrow indicates the electron current direction.
[8]. Better RF power performances were demonstrated as com-pared to the conventional LDMOS. However, a comprehensive analysis of device performance enhancements under strain was not accomplished. Owing to the existence of a drift region in LDMOS, the strain effects on the LDMOS performance might be different from those on the CMOS device perfor-mance. Therefore, it is interesting to investigate the electrical characteristics of LDMOS under strain. In this letter, we study the effects of mechanical stress on the dc and high-frequency characteristics of LDMOS by using wafer bending method. The external mechanical stress can provide biaxial tensile strain on the devices without changing the process flow parameters. It is helpful for studying the strain effect alone. The strain-induced performance enhancements in different layout structures were also compared. The strain-induced high-frequency performance enhancements were observed and were understood by analyz-ing the changes in transconductance and gate capacitance.
II. EXPERIMENTS
The n-channel LDMOS transistors were fabricated by a 0.5 μm CMOS-DMOS process with a gate oxide thickness of 135 Å. The substrate is (100) silicon wafer. The effective channel length and drift length are 1.1 and 2.4 μm, respectively. Detailed description of the device structure can be found in [9]. Two device layouts are studied in this work (see Fig. 1). Since the drift region of the annular structure is located on the outside, it is less susceptible to quasi-saturation at high current [10]. More significantly, it has higher cutoff frequency, which cannot be improved by increasing the width of the multifinger structure.
A wafer bending apparatus is used to apply external biax-ial tensile stress [4], [5]. The strain on the silicon substrate was estimated by the ANSYS simulation. The dc and
472 IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 4, APRIL 2012
Fig. 2. Output characteristics of the multifinger (left) and annular (right) LDMOS transistors with and without 0.051% mechanical strain. The on-resistances shown in this figure were extracted at VGS= 4 V.
Fig. 3. IDenhancements of a multifinger device with different biaxial strains. At VGS= 1.5 V, the current enhancements are similar as the nMOSFET in
low-voltage CMOS technology [4]. The inset shows the IDenhancement under
0.051% strain as a function of gate voltage.
frequency characteristics of the test devices were measured on chip using an Agilent 4142B modular source/monitor and an Agilent 8510C network analyzer from 100 MHz to 20 GHz.
III. RESULTS ANDDISCUSSION
The dc characteristics of LDMOS under strain are shown in Fig. 2. The drain currents (ID) in both multifinger and annular
LDMOS devices are enhanced by applying the biaxial stress, owing to the strain-induced mobility enhancement [11]. Since the change in silicon energy bandgap is small under the low strain (0.051%), the breakdown voltages are nearly unchanged (< 1%). By plotting the current enhancements with different strains, we found that the current enhancements are nearly proportional to the strain (see Fig. 3). At low gate voltages (VGS), the ID improvements are similar as today production
low-voltage CMOS transistor for the same biaxial strain [4] suggesting that improvement as large as 30% maybe obtainable, as in CMOS transistor if large biaxial strain is applied with stressor as in strained CMOS technology. However, unlike strained CMOS transistors, LDMOS current enhancement is significantly lower at high VGSthan at low VGS. With 0.051% biaxial strain, the enhancement of ID decreases from 6.7% to
Fig. 4. Cutoff frequency and maximum oscillation frequency of the LDMOS transistors with and without 0.051% mechanical strain. Solid symbols are the measured data, and open symbols are the calculated data.
3.7% when VGS increases from 1.5 V to 2.5 V for multifinger device.
For LDMOS transistors, the drain current is dominated by the channel current at low VGS, while it is dominated by the drift region resistance at high VGS. Therefore, the smaller enhancement at higher VGS indicates that the drift resistance cannot be changed as much as the channel current by the tensile stress. When the electrons emit from channel to drift region, the applied stress is not parallel to the current direction. In addition, the electron velocity in the drift region is closer to saturation than in the channel. These differences may degrade the enhancement and even increase the resistivity in the drift region. The increase of the drift resistivity can be confirmed by the increase of on-resistance (RON), as shown in Fig. 2.
The inset of Fig. 3 compares the strain-induced current enhancements between multifinger and annular devices. The annular device has better improvement than the multifinger one at all gate biases. For multifinger device, the current flows in the 110 direction, while for annular device, the current flows through all directions in the (100) plane (see Fig. 1). Since the piezoresistance coefficients increase from 110 to
100 [12], the current in annular device could have larger
increase than that in multifinger counterpart. Present production techniques produce uniaxial strains, 100 current flow would be advantageous. Owing to a higher drain current and strain sensitivity, the annular layout would be a better choice for power-amplifier applications.
To study the high-frequency behavior under strain, the ac current gain (H21) and unilateral power gain (U ) were calcu-lated from S-parameters to extract the cutoff frequency (fT)
and maximum oscillation frequency (fmax), respectively. Fig. 4 shows the strain effects on the measured fT for the two layouts.
Similar to the dc performance, the strain-induced improvement of cutoff frequency is better in annular device. 3.7% peak fT
improvements are observed versus 3.1% for the multifinger device. Moreover, the strain-induced fT enhancement closes
to the ID enhancement at the same bias condition, indicating
that the applied stress can also have large influence on the RF performance. Since the fT is related to the small-signal
transconductance (gm) and gate capacitance (Cgg), we are interested to analyze their variations after applying stress.
CHEN et al.: LDMOS TRANSISTOR HIGH-FREQUENCY PERFORMANCE ENHANCEMENTS BY STRAIN 473
Fig. 5. Extracted gmand Cggof a multifinger LDMOS with and without
0.051% mechanical strain.
When ignoring the parasitics, gmand Cggcan be extracted from Y parameters at low frequencies directly [13]. The ex-tracted results of a multifinger LDMOS are shown in Fig. 5. Similar results are also obtained for annular devices. We ob-served that the gmincreases with increasing tensile strain, while
Cgg is nearly unchanged at VGS< 3.5 V. Hence, the strain-induced increase in fT is mainly attributed to the increase in
gm. At VGSnear the peak fT, the enhancements of gmand fT
are 3.3% and 3.1%, respectively. The strain-induced enhance-ment of fT is slightly lower than that of gm. It is probably
due to the influence of drain resistance [9]. At VGS> 3.5 V, the Cgg begins increasing with strain. In pre-quasi-saturation region, the inversion charges may be injected from the intrinsic MOSFET to the depleted area of the drift, so the Cggincreases rapidly with increasing gate voltages [14]. Therefore, the strain-induced Cggvariation at high gate voltages suggests the quasi-saturation effect may become more serious under strain. For-tunately, for RF applications, the gate biases of LDMOS are below the pre-quasi-saturation region.
Because the measurement uncertainty of fmax could be higher than 3% owing to the influence of gate resistance (Rg),
we compared the fmaxvariation under strain using the calcu-lated data based on [15]
fmax≈
fT
2gdsRg+ 2πfTCgd(Rg+ αRd)
(1)
where gds is the channel conductance, Cgd is the gate-to-drain capacitance, Rd is the drain resistance, and α is the
ratio of drain capacitance to Cgg. Since the terms gdsRg and
2πfTCgdαRd in (1) are much lower than the 2πfTCgdRg
in our devices, the strain-induced variations of gds and Rd
can been ignored. In addition, Rg could not be changed by
the strain. Therefore, all parameters except fT in (1) were
derived from the measured S-parameters without strain, while the measured fT with and without strain were substituted into
(1) to obtain the fmaxwith and without strain, respectively. The calculated fmaxwithout strain quite approaches to the measured
fmax (see Fig. 4). The strain-induced enhancements of peak
fmax for multifinger and annular devices are 1.6% and 2.0%, respectively.
IV. CONCLUSION
The enhancements of high-frequency performances of LDMOS transistors by mechanical tensile stress have been observed in this study. By analyzing the gmand Cggvariations with strain, we know the strain-induced fT enhancement is
mainly related to the gm enhancement. In addition, owing to
the different channel directions, the annular devices have more improvement than the multifinger ones. Our results suggest that applying a tensile stress to LDMOS is an effective and attractive method to improve its performance for RF applications.
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