Performance and characteristics of double layer porous silicon oxide resistance
random access memory
Tsung-Ming Tsai, Kuan-Chang Chang, Rui Zhang, Ting-Chang Chang, J. C. Lou, Jung-Hui Chen, Tai-Fa Young, Bae-Heng Tseng, Chih-Cheng Shih, Yin-Chih Pan, Min-Chen Chen, Jhih-Hong Pan, Yong-En Syu, and Simon M. Sze
Citation: Applied Physics Letters 102, 253509 (2013); doi: 10.1063/1.4812474 View online: http://dx.doi.org/10.1063/1.4812474
View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/102/25?ver=pdfcov Published by the AIP Publishing
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Performance and characteristics of double layer porous silicon oxide
resistance random access memory
Tsung-Ming Tsai,1,a)Kuan-Chang Chang,1Rui Zhang,2Ting-Chang Chang,3,4,a)J. C. Lou,2 Jung-Hui Chen,5Tai-Fa Young,6Bae-Heng Tseng,1Chih-Cheng Shih,5Yin-Chih Pan,1 Min-Chen Chen,3Jhih-Hong Pan,1Yong-En Syu,3and Simon M. Sze7
1
Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, 70 Lien-hai Road, Kaohsiung 804, Taiwan
2
School of Software and Microelectronics, Peking University, Beijing 100871, People’s Republic of China 3
Department of Physics, National Sun Yat-Sen University, 70 Lien-hai Road, Kaohsiung 804, Taiwan 4
Advanced Optoelectronics Technology Center, National Cheng Kung University, Tainan, Taiwan 5
Department of Chemistry, National Kaohsiung Normal University, Kaohsiung, Taiwan 6
Department of Mechanical and Electro-Mechanical Engineering, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 804, Taiwan
7
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan
(Received 11 March 2013; accepted 9 June 2013; published online 28 June 2013)
A bilayer resistive switching memory device with an inserted porous silicon oxide layer is investigated in this letter. Compared with single Zr:SiOx layer structure, Zr:SiOx/porous SiOx
structure outperforms from various aspects, including low operating voltages, tighter distributions of set voltage, higher stability of both low resistance state and high resistance state, and satisfactory endurance characteristics. Electric field simulation by COMSOLTM Multiphysics is
applied, which corroborates that intensive electric field around the pore in porous SiOxlayer guides
the conduction of electrons. The constraint of conduction path leads to better stabilization and prominent performance of bilayer resistive switching devices.VC 2013 AIP Publishing LLC.
[http://dx.doi.org/10.1063/1.4812474]
Among the candidates for future non-volatile memory,1–3 resistive random access memory (RRAM) has great potential for next-generation nonvolatile memory due to their superior characteristics such as low cost, simple structure, high-speed operation, and non-destructive readout.4–7
Various materials have been reported to possess the resistive switching behaviors, and silicon oxide based RRAM has shown lots of merits in RRAM switching proper-ties.8,9Stable device characteristics such as concentrated dis-tribution of reading states and lower operation power are required for the applications of next generation nonvolatile memory. Various methods can be used to modify the RRAM working properties such as material modification10,11 and structure alteration.12 Definitely the research using different methods to improve RRAM performance is worthy of investigation.
In our research, a single layer Zr metal doped into SiO2
(Zr:SiOx) by co-sputtering and a porous SiOx fabricated by
inductively coupled plasma (ICP) O2plasma processes were
constructed to form a Zr:SiO2/porous SiO2 structure RRAM
(inset of Fig.2(b) is real picture of the device). ICP etching has always been a popular method to modify film structure, especially fabricating porous structure.13–15 Moreover, by etching carbon elements in the SiO2film, nanopores can be
formed.16To make a comparison, single Zr:SiOxlayer RRAM
was also fabricated. Resistive switching characteristics of both single Zr:SiOxlayer and bilayer Zr:SiO2/porous SiO2RRAM
devices have been investigated. FinallyCOMSOLMultiphysics17
was applied to simulate the electrical field concentrating capa-bility of nanopores.
The experimental specimens were prepared as follows: for the single layer specimen, the Zr:SiOxthin film (about
20 nm) was deposited on the TiN/Ti/SiO2/Si substrate by
co-sputtering with the pure SiO2 and Zr targets. The patterned
substrate was obtained by standard deposition and etching process, after which 1 lm 1 lm via holes were formed. Also, the three dimensional view of the device is shown as the inset of Fig. 4. The sputtering power was fixed at RF power 200 W and 20 W for SiO2and Zr targets, respectively.
The co-sputtering was executed in argon ambient (Ar¼ 30 sccm) with a working pressure of 6 mTorr at room temperature. However, for the double resistive switching layer specimen, at beginning a C:SiOxfilm (about 6 nm) was
deposited by co-sputtering with the SiO2 and C targets and
then processed by ICP O2plasma. The sputtering power was
fixed at RF power 200 W and 5 W for SiO2 and C targets,
respectively. The co-sputtering was also executed in argon ambient (Ar¼ 30 sccm) with a working pressure of 6 mTorr at room temperature. The ICP oxygen plasma etching pro-cess is shown schematically in Fig.1. By burning carbon ele-ments in the SiO2 layer, nanopores are formed. Fourier
transform infrared (FTIR) spectroscope was applied after the ICP etching process, from which we found the concentration of carbon elements dropped drastically (not shown here). The ICP power was fixed at 600 W with a treatment period of 5 s. Then the layer of Zr:SiOx(about 14 nm) was deposited
with the same RF power, argon ambient, and working pres-sure as antecedent single Zr:SiOxlayer specimen.
a)Authors to whom correspondence should be addressed. Electronic addresses: [email protected] and [email protected]. edu.tw
Ultimately, the Pt top electrode of 200 nm thickness was deposited on both specimens by DC magnetron sputtering. The entire electrical measurements of devices with the Pt electrode were performed using Agilent B1500 semiconduc-tor parameter analyzer.
The electroforming process is required to activate all of the RRAM devices, using dc voltage sweeping with a com-pliance current of 10 lA. Then, dc voltage sweeping cycling test is performed to evaluate both types of devices. During the dc sweeping test of more than 10 samples, we find that Zr:SiOx/porous SiOx RRAM devices have smaller working
currents on both low resistance state (LRS) and high resist-ance state (HRS) compared with single layer devices. Figure
2(a)compares the I-V curve of both types of devices, from which working current reduction phenomenon can be observed. It is also noted that the single Zr:SiOxlayer device
has less uniform set voltage during dc sweeping cycles, which is further revealed in the distributions comparison of set voltage of single layer and bilayer RRAM devices (Figure 2(b)). Furthermore, from Figures 2(c) and 2(d) we
can see that the stability between HRS and LRS of Pt/Zr:SiOx/TiN RRAM exhibit more fluctuations compared
with Pt/Zr:SiOx/porous SiOx/TiN structure devices.
To further evaluate the memory performance, measure-ment of endurance of both kinds of devices was performed, as shown in Figure3. During 104sweeping cycles, HRS and LRS of Zr:SiOx RRAM overlap each other (Figure 3(a))
while to Zr:SiOx/porous SiOxRRAM device it exhibits
sta-ble HRS and LRS even after more than 106sweeping cycles (Figure3(b)).
During the test process of endurance, we find porous structure RRAM devices need less time (30 ns) in the set-ting process compared with single layer structure, whose positive pulse lasts 40 ns, which can been seen from the bottom diagrams of Figure 3. In order to clarify that bilayer RRAM devices need less time in the setting pro-cess, we apply fast I-V measurement to measure setting time more accurately. From Figure 4, it can be observed that single Zr:SiOx layer device needs almost 400 ns to
change from HRS to LRS, while it needs only half of that
FIG. 1. Schematic view of ICP oxygen plasma process. Nanopores are formed by etching carbon elements in SiO2 layer.
FIG. 2. (a) Resistive switching characteristics comparison of normal and porous oxide structure RRAM. (b) Distributions of set voltage. Inset is the real picture of device. (c), (d) Distributions of HRS and LRS within 100 cycles of single Zr:SiO2layer and porous oxide structure RRAM, respectively.
time to Zr:SiOx/porous SiOx RRAM device for resistance
switching.
To understand the impact of the inserted porous SiOx
layer, we utilizeCOMSOLMultiphysics17software to simulate
the distribution of electric field and to confirm the electrical field concentrating capability of nanopores. As carbon ele-ments are burned in the ICP process leaving pores in the SiO2layer, the permittivity is set as 1, which is equal to the
permittivity of vacuum,18 and the permittivity of silicon dioxide equals to 3.9.19 The permittivity of metal filament which formed after electro-forming process is set with 1 106, high enough to comply with metal property.
Besides, because the film fabricated by sputter process has a lower density compared with chemical vapor deposition and the total film thickness of porous SiO2layer is 6 nm, pore’s
size is set with an estimated radius of 0.7 nm in the simula-tion process.13,16 The mesh size is applied with extra fine mode with minimum element size of 2.7 1012m to get precise enough electrical field distribution, and the voltage applied on the bottom electrode is 2 V with the top electrode
grounded. Electrostatics(es) under AC/DC module is used to calculate stable state electrical field distribution, as shown in Figure 5; it can be obviously seen that there exists higher density of electric field in and around the area of the pore in porous SiOxlayer, confirming the electrical field
concentrat-ing capability of nanopores. Compared with SiO2, pore in
porous SiOx layer works much like low-k (low dielectric
constant) dielectric,20 which has a tendency to concentrate electric field. Thus during the forming process, metal con-duction filaments have an inclination to form towards the direction of pore, which means we can obtain a relative strong and stable filament. As electrons tend to conduct through a relative uniform path, we can observe that Zr:SiOx/porous SiOxRRAM devices work much more stable
and have tighter distribution of set voltage.
The resistive switching mechanism of single Zr:SiOx
layer RRAM can be explained by the stochastic formation and rupture of conduction filaments.21Due to the stochastic
FIG. 3. (a) and (b) Endurance characteristics of Zr:SiO2and Zr:SiO2/porous SiO2RRAM, respectively. The bottom diagrams are the corresponding device structures and endurance testing pulse.
FIG. 4. Setting time comparison under fast I-V test. Inset is the 3-D sche-matic structure of device.
FIG. 5. Electric field simulation of HRS and LRS of Zr:SiOx/porous SiOx RRAM.
formation of conduction filaments process, single active layer RRAM device exhibits less stable set voltage and lower degree of uniformity in dc sweeping process. However, if the porous SiOxlayer is added at the bottom electrode of TiN,
filaments growth has much more directionality, where, in turn, better stabilization can be achieved.
In conclusion, the single layer Zr:SiO2 RRAM and
bilayer Zr:SiO2/porous SiO2RRAM have been fabricate to
investigate the resistive switching characteristics. Bilayer RRAM devices have superior properties owing to the rela-tive stable conduction path, as pore in porous SiOxlayer has
an inclination to guide the formation of metal conduction fil-aments.COMSOLMultiphysics is used to simulate the
distribu-tion of electric field, from which mutual verificadistribu-tion with experimental data can be obtained.
This work was performed at the National Science Council Core Facilities Laboratory for Nano-Science and Nano-Technology in the Kaohsiung-Pingtung area and was supported by the National Science Council of the Republic of China under Contract Nos. NSC-101-2120-M-110-002 and NSC 101-2221-E-110-044-MY3.
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