鉬奈米點在非揮發性記憶體應用之研究

國 立 交 通 大 學

電子工程學系 電子研究所

碩士論文

鉬奈米點在非揮發性記憶體應用之研究

Study on Floating-Gate Molybdenum

Nanocrystals for Nonvolatile Memory

Application

研 究 生：廖述穎

指導教授：施 敏 院士

張鼎張 博士

鉬奈米點在非揮發性記憶體應用之研究

Study on Floating-Gate Molybdenum Nanocrystals

for Nonvolatile Memory Application

研 究 生：廖述穎

Student：Shu-Ying Liao

指導教授：施 敏 院士 Advisor：Dr. Simon M.Sze

張鼎張 博士 Advisor：Dr. Ting-Chang Chang

國 立 交 通 大 學

電子工程學系 電子研究所

碩 士 論 文

A Thesis

Submitted to Department of Electronics Engineering &

Institute of Electronics

College of Electrical and Computer Engineering

National Chiao Tung University

In Partial Fulfillment of the Requirements

For the Degree of Master

In

Electronic Engineering

August 2008

鉬奈米點在非揮發性記憶體應用之研究

研究生: 廖述穎 指導教授 : 施 敏 院士

張鼎張 博士

國立交通大學

電子工程學系 電子研究所

摘要

非揮發性記憶體(NVM)目前在元件尺寸持續微縮下的需求為高密度記憶單元、 低功率損耗、快速讀寫操作、以及良好的可靠度(Reliability)。傳統浮動閘極(floating gate)記憶體在操作過程中如果穿隧氧化層產生漏電路徑會造成所有儲存電荷流失回 到矽基板，所以在資料保存時間(Retention)和耐操度(Endurance)的考量下，很難去微 縮穿隧氧化層的厚度。非揮發性奈米點記憶體被提出希望可取代傳統浮動閘極記憶 體，由於奈米點可視為電荷儲存層中彼此分離的儲存點，可以有效改善小尺寸記憶 體元件多次操作下的資料儲存能力。近年來發展了許多方法來形成奈米點，一般而 言，大多數的方法都需要長時間高溫的熱製程，這個步驟會影響現階段半導體製程 中的熱預算和產能。 在本文中，一個簡單的製程方法用來形成鉬(Molybdenum)奈米點，並應用 於非揮發性記憶體。室溫下，共蒸鍍(co-evaporating)鈀材 Mo 和介電質(如:SiOx、 SiNx、AlOx)形成介電質包覆著鉬奈米點的非揮發性記憶體結構，我們認為在退火過 程中形成奈米點，溫度扮演一個重要的腳色，可以簡單並均勻地形成高密度(~1012 cm-2)的奈米點。我們發現高密度的鉬奈米點被包覆在氧化鋁(AlOx)中有較好的儲存 能力。此外，這個應用在非揮性記憶體的製程技術同時也適用於現階段積體電路製 程。

Study on Floating-Gate Molybdenum

Nanocrystals for Nonvolatile Memory Application

Student:

Shu-Ying Liao

Advisor：Dr. Simon M.Sze

Dr. Ting-Chang Chang

Department of Electronic Engineering and Institute of Electronics

National Chiao Tung University

Abstract

Current requirements of nonvolatile memory (NVM) are the high density cells, low-power consumption, high-speed operation and good reliability for the scaling down devices. However, all of the charges stored in the floating gate will leak into the substrate if the tunnel oxide has a leakage path in the conventional NVM during endurance test. Therefore, the tunnel oxide thickness is difficult to scale down in terms of charge retention and endurance characteristics. The nonvolatile nanocrystal memories are one of promising candidates to substitute for conventional floating gate memory, because the discrete storage nodes as the charge storage media have been effectively improve data retention under endurance test for the scaling down device. Many methods have been developed recently for the formation of nanocrystal. Generally, most methods need thermal treatment with high temperature and long duration. This procedure will influence

temperature. It can be considered that the annealing tamperature plays a critical role during sputter process for the formation of nanocrystal. In addition, the high density (~1011cm-2) nanocrystal can be simple and uniform to be fabricated in our study. We also proposed a formation of molybdenum nanocrystals embedded in AlOx by co-evaporating

molybdenum and AlOx at room temperature. It was also found that high density Mo

nanocrystals embedded in theAlOx and larger memory effect. These fabrication

techniques for the application of nonvolatile nanocrystal memory can be compatible with current manufacture process of the integrated circuit manufacture.

誌 謝

在本篇論文即將完成同時，也代表著學生生涯將告一段落，這一路走來，要感 謝的人很多，感激之情無以言表，在此願以我最誠摯的心向你們說聲：「謝謝」。 首先要感謝的是我的指導教授張鼎張老師，老師為了研究上的討論每個禮拜不 辭辛勞地南北奔波，在實驗及研究上提供我正確的研究方向以及解決所遇到的困 難。施敏老師提供了他豐富的人生經驗，教導我如何待人處事，並勉勵自己要立定 志向做大事。還要感謝劉柏村老師，在實驗上的幫忙與提供寶貴的意見。 在新竹兩年的研究生涯裡，非常感謝和我朝夕相處的學長、同學、學弟們；感 謝奈米組的峻豪、緯仁、世青、立偉、昭正、勝凱學長，謝謝你們在實驗上給我很 多寶貴的意見，不管是研究上的精神以及做人做事應有的態度，在你們身上我學習 到很多；還要感謝我的同學們，貴宇、勝杰、培堃、成能、聖錡、元駿、凱廷、派 璿，感謝你們的陪伴與鼓勵，和你們在無塵室裡一起奮鬥是我一生最難忘的日子， 你們永遠都是我的好朋友；另外還要感謝信淵、耀峰、誌陽、宥豪等學弟們，感謝 你們在生活及實驗上的幫忙，也常給實驗室帶來歡笑氣氛還。 另外，我要特別感謝中山的學長、學姐們，有你們的協助才能讓我的論文更充 實；還有成大的柯榮明大哥，很敬佩您的求學精神，並從我們之間的學術交流學到 很多，也謝謝您提供寶貴的人生經驗給我，感謝您來新竹時的招待；還要謝謝電資 418 的學長、學姐等，謝謝你們在實驗上的幫忙與鼓勵。 最後，最親愛的爸爸廖繼吉先生、媽媽陳菊香女士以及哥哥述茂、述俊，謝謝 你們這段時間在精神與生活上的支持與鼓勵，提供一個溫暖的家給我作避風港，讓 我無後顧之憂完成這個碩士學位；這兩年來我投入大部分的心力在學業研究上，和

Contents

Chinese Abstract………..Ⅰ

English Abstract………..Ⅲ

Acknowledgement………Ⅳ

Contents………Ⅴ

Table Captions………Ⅷ

Figure Captions………...Ⅹ

Chapter 1 Introduction

1.1 Overview of Nonvolatile Memory………..1

1.1.1 SONOS Nonvolatile Memory Devices………..2

1.1.2 Nanocrystal Nonvolatile Memory Devices………4

1.2 Organization of This Thesis………8

Chapter 2 Basic Principle of Nonvolatile Memory

2.1 Introduction...13

2.2 Basic Program/Erase Mechanisms...14

2.2.1 Energy band diagram during program and erase operation……….14

2.2.2 Carrier injection mechanisms………...14

2.3 Basic Reliability of Nonvolatile Memory...18

2.3.1 Retention………..19

2.3.2 Endurance………...19

2.4 Basic Physical Characteristic of Nanocrystal NVM...20

2.4.1 Quantum Confinement Effect………...20

Chapter 3 Formation and Nonvolatile Memory Effect of Mo

Nanocrystal embedded in SiO

x

3.1 Motivation………32 3.2 Nonvolatile Molybdenum Nanocrystal Memory by oxidation Mo and Si layer...32 3.2.1 Experimental Procedures……….32 3.2.2 Results and Discussions………...33 3.3 Nonvolatile Mo Nanocrystal Memory by thermal annealing Mo and SiO2

layer…...33 3.3.1 Experimental Procedures………..34 3.3.2 Results and Discussions………..36 3.4 Comparison of Electrical Characteristics between Mo nanocrystal by oxidizing Mo-Si and annealing Mo-SiO2……….36

3.5 Summary I ………37

Chapter 4 Formation and Nonvolatile Memory Effect of Mo

Nanocrystal embedded in SiN

x

4.1. Motivation...44 4.2. Nonvolatile Molybdenum Nanocrystal Memory by oxidation Mo and SiNx

layer……… ……….44 4.2.1 Experimental Procedures……….44

Nanocrystal embedded in AlO

x

5.1 Motivation………...54 5.2 Nonvolatile Molybdenum Nanocrystal Memory by oxidation Mo and AlOx

layer………...54 5.2.1 Experimental Procedures……….54 5.2.2 Results and Discussion………55 5.3 Comparison of Electrical Characteristics between Molybdenum Nanocrystals embedding in SiOx and AlOx Nonvolatile Memory……….56

5.4 Summary Ⅲ...57

Chapter 6 Conclusion

6.1 Conclusions...63

Table Captions

Chapter 3

Table 3-1 Comparisons of memory window, nanocrystal density and retention characteristics between two type nonvolatile memory devices. …………..43

Chapter 4

Table 4-1 Comparisons of memory window, nanocrystal density and retention characteristics between two type nonvolatile memory devices. ………….53

Chapter 5

Table 5-1 Comparisons of memory window, nanocrystal density and retention characteristics between two type nonvolatile memory devices. ……..……62

Figure Captions

Chapter 1

Figure 1-1 The structure of the conventional floating gate nonvolatile memory device. Continuous poly-Si floating gate is used as the charge storage element. ...9 Figure 1-2 The development of the gate stack of SONOS EEPROM memory devices.

The optimization of nitride and oxide films has been the main focus in recent years. ………..…10 Figure 1-3 The structure of the SONOS nonvolatile memory device. The nitride

layer is used as the charge-trapping element. ………11 Figure 1-4 The structure of the nanocrystal nonvolatile memory device. The semiconductor nanocrystals or metal nanocrystals are used as the charge storage element instead of the continuous poly-Si floating gate. ……….12

Chapter 2

Figure 2-1 I–V curves of an FG device when there is no charge stored in the FG (curve A) and when a negative charge Q is stored in the FG (curve B). ..22 Figure 2-2 Energy band diagrams of a dual-channel SONOS transistor under (a)

program (b) erase operation.● electrons, ○ holes. ………23 Figure 2-3 (a) Schematic cross-section of nanocrystal memory device structure; (b)

illustration of write process: inversion- layer electron tunnels into the nanocrystal; (c) illustration of erase process: accumulation layer hole tunnels into the nanocrystal, electron in nanocrystal can tunnel back to the channel. ……….………24 Figure 2-4 Fourth approaches to programming methods, described by Hu and White. (a) Direct tunneling (DT) (b) Fowler-Nordheim tunneling (FN) (c) modified Fowler-Nordheim tunneling (MFN) (d) trap assistant tunneling (TAT). ………...……25 Figure 2-5 Schematic cross section of MOSFET. The energy-distribution function at

Figure 2-6 A schematic energy band diagram describing the process involved in electron injection. ………..27 Figure 2-7 Energy-band diagram for the proposed band to band induce hot electron injection mechanism and schematic illustration cross of the Flash memory with p-channel cell. Due to the positive bias to the control gate, holes are not injected into the tunnel oxide. ……….28 Figure 2-8 Band to band induce hot hole injection mechanism and schematic illustration cross of the Flash memory with p-channel cell. ……….29 Figure 2-9 A typical result of an endurance test on a single cell. Threshold voltage

window closure as a function of program / erase cycles on a single cell. ………30 Figure 2-10 Anomalous SILC modeling. The leakage is caused by a cluster of positive

charge generated in the oxide during erase. The multitrap assisted tunneling is used to model SILC: trap parameters are energy and position. ……….31

Chapter 3

Figure 3-1 Schemas of the experimental procedures. ………38 Figure 3-2 Cross-sectional TEM images of the MOIOS structure with co-evaporating

Mo and Si and annealing in 900oC O2. ……….38

Figure 3-3 Capacitance-voltage (C-V) hysteresis of the fabricated MOIOS structure with Mo nanocrystals embedded in SiOx. ……….39

Figure 3-4 The XPS analysis of Mo 3d spectra for Mo nanocrystals embedded in SiOx.

After the thermal process, the peak signal of MoO2 and MoO3 can be

with Mo nanocrystals embedded in SiOx. (a) The sample of as-depostion (b)

After annealing 700 oC N2 30min. (C) After annealing 900 oC N2

30min. ………...41 Figure 3-9 The XPS analysis of Mo 3d and Si 2d spectra for Mo nanocrystals

embedded in SiOx. After the thermal process, the peak signal of SiOx can

be observed, apparently. ………42 Figure 3-10 Retention characteristics of the Mo nanocrystal memory by co-evaporated Mo and SiOx after annealing 900 oC and 700 oC in N2 for 30

min. ………...42

Chapter 4

Figure 4-1 Schematics of the experimental procedures. ……….49 Figure 4-2 Cross-sectional TEM images of the MOIOS structure with co-evaporating Mo and SiNx and annealing in 900oC N2. ……….49

Figure 4-3 Capacitance-voltage (C-V) hysteresis of the fabricated MOIOS structure with Mo nanocrystals embedded in SiNx. (a) The sample of as-depostion (b)

After annealing 700 oC N2 30min. (C) After annealing 900 oC N2

30min. ………...50 Figure 4-4 The XPS analysis of Mo 3d and Si 2d spectra for Mo nanocrystals

embedded in SiNx. After the thermal process, the peak signal of SiNx can

be observed, apparently. ………51 Figure 4-5 Retention characteristics of the Mo nanocrystal memory by co-evaporated Mo and SiNx after annealing 900 oC and 700 oC in N2 for 30 min. ……..51

Figure 4-6 Retention characteristics of the Mo nanocrystal embedded in SiO2 and

SiNx after annealing 900 oC in N2 for 30 min. ………..52

Figure 4-7 Modeling Retention characteristics. （a）the Mo nanocrystal embedded in SiO2 and （b） the Mo nanocrystal embedded in SiNx after annealing 900 o

C in N2 for 30 min. ………..52

Chapter 5

Figure 5-2 Cross-sectional TEM images of the MOIOS structure with co-evaporating Mo and AlOx and annealing in 900oC N2. ……….…..58

Figure 5-3 Capacitance-voltage (C-V) hysteresis of the fabricated MOIOS structure with Mo nanocrystals embedded in SiNx. (a) The sample of as-depostion (b)

After annealing 700 oC N2 30min. (C) After annealing 900 oC N2

30min. ………...59 Figure 5-4 The XPS analysis of Mo 3d and Al 2d spectra for Mo nanocrystals

embedded in AlOx. After the thermal process, the peak signal of SiOx can

be observed, apparently. ………60 Figure 5-5 Retention characteristics of the Mo nanocrystal memory by co-evaporated Mo and AlOx after annealing 900 oC and 700 oC in N2 for 30 min. …….60

Figure 5-6 Retention characteristics of the Mo nanocrystal embedded in SiNx and

AlOx after annealing 900 oC in N2 for 30 min. ……….61

Figure 5-7 Modeling Retention characteristics. （a）the Mo nanocrystal embedded in SiNz and （b） the Mo nanocrystal embedded in AlOx after annealing 900 o

Chapter 1

Introduction

1.1 Overview of Nonvolatile Memory

Today, flash memory finds wide applications and is considered a technology driver for the global semiconductor. It can be classified into two major markets: code storage application and data storage application. NOR type flash memory [1.1] is most suitable for code storage application, such as cellular phones, PC bios, and DVD player. NAND type flash memory [1.2] has been targeted at data storage market, such as PDA, memory cards, MP3 audio players, digital cameras, and USB flash personal disc. These products all are based on flash memory that is nonvolatile and can keep the stored information when the power supply is switched off. Flash memory has exhibits other advantages, such as the ability to be electrically programmed and fast simultaneous block electrical erasure, small cell size for high chip density, and good flexibility [1.3-1.4]. In addition, the flash memory fabrication process is compatible with the current CMOS process and is a suitable solution for embedded memory applications. Therefore, flash memory has replaced most of EPROMs (Erasable Programmable Read Only Memory) and EEPROMs (Electrically Erasable Programmable Read Only Memory). Since flash memory possesses these key advantages, it has become the mainstream nonvolatile memory device nowadays.

In 1967, D. Kahng and S. M. Sze invented the floating-gate (FG) nonvolatile semiconductor memory (or flash memory) at Bell Labs [1.5]. The conventional floating-gate device structure is shown in Fig. 1-1. The FG acts as the storing electrode and is electrically governed by a capacitively coupled with the control gate (CG). Charge injected the FG is maintained there, giving rise to a difference threshold voltage into for nonvolatile memory application.

Recently, nonvolatile memory devices are moving toward high density memory array, low cost, low power consumption, high-speed operation, and good reliability. Although conventional flash memory does not require refreshing and thus consumes less

power and achieves much higher array density with a stacked floating gate structure. However, floating-gate flash memory is much slower to operation and has poor endurance. In order to improve the write/erase speed of a floating-gate device, the thickness of the tunnel oxide must be reduced. But conventional FG memory devices have limited potential for aggressive scaling of the tunnel oxide thickness. The tunnel oxide must be thin enough to allow quick and efficient charge transport to and from FG. On the other hand, the tunnel oxide needs to provide superior isolation under retention, endurance, and disturbed conditions in order to guarantee the data integrity for 10 years. For faster operation speed, thin tunnel oxide is desirable. However, it is desirable to increase the thickness of tunnel oxide for better isolation and reliability. So there is a trade-off between speed and reliability for the optimum tunnel oxide thickness. Currently, commercial flash memory devices use tunnel oxide thicker about 8-11 nm, which results in high programming voltage and slow programming speed [1.6].

To alleviate the tunnel oxide design trade-off for floating-gate memory devices, memory-cell structures employing discrete traps as charge storage media have been proposed. In the conventional floating gate flash memory, if there is one defect created in the tunnel oxide, all the charges stored on the floating-gate will leak back to the channel or the source/drain through the weak spots. Unlike conventional continuous floating gate, charges stored in discrete nodes cannot easily redistribute amongst themselves. Therefore, only a relatively small number of nodes near the oxide defects will be affected. Local charge storage in discrete nodes enables more aggressive scaling of the tunnel oxide by relieving the total charge loss concern. There are two promising candidates, SONOS [1.7-1.9] and nanocrystal nonvolatile memory devices [1.10-1.12], that have been demonstrated to lead to an improvement in retention time compared with conventional floating gate memory. Hence the tunnel oxide thickness can be reduced to allow faster

cause threshold voltage shift. Then the silicon nitride trap-based devices are extensively studied for charge storage device application in the early 70s. Fig. 1-2 illustrates the progression of device cross section, which has led to the present SONOS device structure. Initial device structures in the early 1970s were p-channel metal-nitride-oxide-silicon (MNOS) structures with aluminum gate electrodes and thick (45nm) silicon nitride charge storage layers. Write/erase voltages were typically 25-30 V. In the late 1970s and early 1980s, scaling moved to n-channel SNOS devices with write/erase voltages of 14-18 V. In the late 1980s and early 1990s, n- and p-channel SONOS devices emerged with write/erase voltages of 5-12 V. The advantages of the ONO triple dielectric structure are: (1) lower programming voltage since the blocking action of the top oxide removes any limitation on the reduction of the nitride thickness; (2) charge injection from and to the gate electrode is minimized for both gate polarities, particularly for hole injection; (3) improved memory retention since there is minimal loss of charge to the gate electrode.

The SONOS (poly-Silicon-Oxide-Nitride-Oxide-Silicon) memory devices, as shown in Fig. 1-3, have attracted a lot of attention due to its advantages over the traditional floating-gate flash device. These include reduced process complexity, high speed operation, lower voltage operation, improved cycling endurance, and elimination of drain-induced turn-on [1.14-1.16]. The main difference between floating-gate and SONOS structure is the method of charge storage. The charge storage media in the floating-gate structure is the conducting polysilicon floating-gate electrode. In the SONOS memory structure, charges are stored in the physical discrete traps of silicon nitride dielectric. A typical trap has a density of the order 1018-1019 cm-3 according to Yang et al [1.17] and stores both electrons and holes injected from the channel. The charges cannot move freely between the discrete trap locations, hence the SONOS memory device is very robust against the defects inside the tunnel oxide and has good endurance.

The SONOS memory devices still face challenge in the future for high density nonvolatile memory application, which requires low voltage (< 5V), low power consumption, long-term retention, and superior endurance. Various approaches have been proposed for improving the SONOS performance and reliability. Chen et al. demonstrated a Si3N4 bandgap engineering (BE) control method for better endurance and

retention. A nitride with varied relative Si/N ratio throughout the film has increased the charge-trapping efficiency significantly [1.18]. Tan et al. showed that over-erase phenomenon in SONOS memory structures can be minimized by replacing silicon nitride with HfO2 as the charge storage layer. The charge retention and endurance performance

is improved by the addition of 10% Al2O3 in HfO2 to form HfAlO, while maintaining the

over-erase resistance of HfO2 [1.19]. She et al. demonstrates that high-quality nitride is

applied as the tunnel dielectric for a SONOS-type memory device. Compared to control devices with SiO2 tunnel dielectric, faster programming speed and better retention time

are achieved with low programming voltage [1.20]. Lee et al. presents a device structure of SiO2/SiN/Al2O3 (SANOS) with TaN metal gate. It is demonstrated that the use of TaN

metal gate blocks electron current through Al2O3 layer more efficiently than a

conventional polysilicon gate, resulting in faster program/erase speed and significant decrease of the saturation level of the erase VT [1.21].

Chen et al. studies a polycrystalline silicon thin-film transistor (poly-Si TFT) with oxide/nitride/oxide (ONO) stack gate dielectrics and multiple nanowire channels for the applications of both nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory and switch transistor [1.22]. The proposed NW SONOS-TFT exhibits superior memory device characteristics with high program/erase efficiency and stable retention characteristics at high temperature. Such a SONOS-TFT is thereby highly promising for application in the future system-on-panel display applications.

New device structures are also indispensable in making flash memory more scalable. Since SONOS flash memory offers a thinner gate stack than floating gate flash memory, and a FinFET structure controls the short channel effect much better than a bulk structure. It has been demonstrated that the FinFET SONOS flash memory devices with a much smaller cell size can provide both excellent performance and reliability. Therefore,

nanocrystals [1.25]. Fig. 1-4 illustrates conventional nanocrystal nonvolatile memory (NVM) device structures. It is observed that the nanocrystals are separated from each other within the gate dielectric. The term “nanocrystal” refers to a crystalline structure with a nanoscale dimension and its electronic properties seem more similar to an atom or molecule rather than the bulk crystal. For a nanocrystal NVM device, the charge storage media is in the form of mutually isolated nanocrystals instead of the continuous polysilicon layer. The limited size and capacitance of nanocrystals limit the numbers of stored electron, collectively the stored charges screen the gate charge and control the channel conductivity of the memory transistor.

Nanocrystal-based NVM devices have recently received much attention due to their potential to overcome the limitations of conventional polysilicon-based flash memory. Using nanocrystals as charge storage media offers several advantages, the main one being the potential to use thinner tunnel oxide without sacrificing non-volatility. This is a quite attractive proposition since reducing the tunnel oxide thickness is a key to lowering operating voltages and/or increasing operating speeds. This claim of improved scalability results from the local charge storage in discrete nodes, which makes the storage more fault-tolerant and immune to the leakage caused by localized oxide defects. Further, the lateral charge migration effect between nanocrystals can be suppressed by the strongly isolation of surrounded dielectric. There are other important advantages though. First, nanocrystal memories use a more simplified fabrication process as compared to conventional stacked-gate FG NVM’s by avoiding the fabrication complications and costs of a dual-poly process. Second, due to the absence of drain to FG coupling, nanocrystal memories suffer less from drain-induced-barrier-lowering (DIBL) and therefore have intrinsically better punch-through characteristics. One way to exploit this advantage is to use a higher drain bias during the read operation, thus improving memory access time [1.26]. Alternatively, it allows the use of shorter channel lengths and therefore smaller cell area. Finally, nanocrystal memories are characterized by excellent immunity to stress induced leakage current (SILC) and oxide defects due to the distributed nature of the charge storage in the nanocrystal layer.

Research in this regime has focused on the development of fabrication processes and nanocrystal materials, and on the integration of nanocrystal-based storage layers in actual

memory devices.

The fabrication of a nonvolatile memory cell requires a perfect control of four main parameters: (1) the tunnel oxide thickness, (2) the nanocrystal density, (3) the nanocrystal size, and (4) the control oxide thickness. An important consideration is the average size and aerial density of the nanocrystals. Larger-size nanocrystal array provides higher program/erase efficient due to small quantum confinement and coulomb blockade effects, and hence larger tunneling probability. However, it is desirable to reduce the nanocrystal size for better reliability (stress induced leakage during retention). So there is a trade-off between programming speed and reliability in selecting the nanocrystal size. A typical target is a density of at least 1012 cm-2, and requires nanocrystal size of 5 nm and below. Moreover, good process control is needed with regards to such nanocrystal features as: planar nanocrystal layer; inter-crystal interaction (lateral isolation); and crystal doping (type and level). Finally, it is preferred that that the fabrication process is simple and that it uses standard semiconductor equipment.

After the first proposal of a memory transistor using silicon nanocrystals as floating gates. In order to improve the data retention in NVM, double layer Si nanocrystals memory has been investigated [1.27]. It seems interesting to use Ge nanocrystals rather than Si nanocrystals because of its smaller band gap. Indeed King and Hu have recently demonstrated the superior memory properties of Ge based nanocrystal memories over those based on Si [1.28]. Recently, germanium/silicon (Ge/Si) nanocrystals have been reported to possess superior charge retention capability than Ge or Si nanocrystals. This is due to the fact that Ge has a smaller band gap than Si and thus by introducing a Si interface around the Ge nanocrystal, it would create an additional barrier height at the Ge/Si interface which makes it harder for electrons to leak out of the nanocrystal [1.29,1.30]. However, semiconductor nanocrystal memory may not be the ultimate

small barrier for writing and a large barrier for retention between the substrate and the storage nodes. This can be achieved if the storage nodes are made of metal nanocrystals by engineering the metal work function. The major advantages of metal nanocrystals over semiconductor nanocrystals include higher density of states around the Fermi level, scalability for the nanocrystal size, a wide range of available work functions, and smaller energy perturbation due to carrier confinement [1.31]. In addition, an electrostatic modeling from both analytical formulation and numerical simulation is demonstrated that the metal nanocrystals will significantly enhance the electric field between the nanocrystal and the sensing channel set up by the control gate bias, and hence can achieve much higher efficiency in low-voltage P/E [1.32].

Toward better NVM device performance and reliability, numerous attempts have been made using metal nanocrystals. Liu et al. reported the growth of Au, Pt, and Ag nanocrystals on SiO2 using an e-beam deposition method [1.31]. Lee et al. proposed a

NVM structure using the Ni nanocrystals and high-k dielectrics [1.33]. Chen et al. present the stacked Ni silicide nanocrystal memory was fabricated by sputtering a comix target followed by a low temperature RTO process [1.34]. W nanocrystals on atomic-layer-deposited HfAlO/Al2O3 tunnel oxide were presented for application in a

memory device [1.35]. Using W nanocrystal double layers embedded in HfAlO to enhancement of memory window was demonstrated from the short channel devices down to 100nm [1.36]. Tang et al demonstrate that a chaperonin protein lattice can be used as a template to assemble PbSe and Co nanocrystal arrays for Flash memory fabrication. This provides a new approach to achieve a high density and good distribution uniformity nanocrystal array [1.37].

In the future, the primary drivers behind nanocrystal memories are the potential to scale the tunnel oxide thickness, resulting in lower operating voltages, and the simplicity of a single poly-silicon process. But there are still challenges await nanocrystal memories in the long road to commercialization. Nanocrystal memories have yet to deliver on most of their promises. In reality, part of the voltage gain is offset because of the poor control gate coupling. For fabrication processes, it is hard to control the uniformity of the nanocrystal size and their physical locations in the channel. It is not a surprise that nanocrystal memories exhibit large device-to-device variation. Moreover, it has yet to be

demonstrated that both the nominal and the statistical retention behavior are sufficient to meet true non-volatility requirements. Although single-dot memories have been demonstrated [1.38,1.39], but a more fundamental understanding of the scaling limits of nanocrystal memories is necessary, concentrating especially on the aspect of controlling channel conductance when relying on only a few discrete charge centers [1.40]. Finally, in order for that to happen, their claimed benefits will need to be more unambiguously substantiated, and a more appealing bundle of memory features will have to be demonstrated.

1.2 Organization of This Thesis

In Chapter 1, general background of flash, SONOS, and nanocrystal nonvolatile

memory devices are introduced.

In Chapter 2, basic principle of nonvolatile memory is introduced.

In Chapter 3, formation and nonvolatile memory effect of Ni-Si-O and Ni-Si-N

nanocrystal.

In Chapter 4, improved performance of nonvolatile Ni-Si-O and Ni-Si-N nanocrystal

memory after thermal treatment.

In Chapter 5, multi-layer Ni silicide nanocrystal memory.

Figure 1-1 The structure of the conventional floating-gate nonvolatile

memory device. Continuous poly-Si floating gate is used as the

charge storage element.

Figure 1-2 The development of the gate stack of SONOS EEPROM

memory devices. The optimization of nitride and oxide films has been

the main focus in recent years.

Figure 1-3 The structure of the SONOS nonvolatile memory device.

The nitride layer is used as the charge trapping media.

Figure 1-4 The structure of the nanocrystal nonvolatile memory device.

The semiconductor nanocrystals or metal nanocrystals are used as the

charge storage element instead of the continuous poly-Si floating gate.

Chapter 2

Basic Principle of Nonvolatile Memory

2.1 Introduction

There is a widespread variety of Nonvolatile Memory (NVM) devices, and they all show different characteristics according to the structure of the selected cell and the complexity of the array organization. A NVM memory cell has to commute from one state to the other and that can store the information independently of external conditions. There are several methods to achieve the NVM memory characteristic, such as transistor VT shifts, charge displacements, and resistance change [2.1]. In this thesis, we focus on

one solution that a transistor with a threshold voltage that can change repetitively from a high to a low state, corresponding to the two states of the memory cell. Most operations with a shift in the threshold voltage on novel nonvolatile memories, such as nanocrystal and SONOS memories are base on the concept of Flash memory. If a datum has to be stored in a bit of the memory, there are different procedures. The threshold voltage shift of a Flash transistor can be written as [2.2][2.3]:

FC T C Q V =− ∆

where Q is the charge weighted with respect to its position in the gate oxide, and the capacitances between the floating gate and control gate. The threshold voltage of the memory cell can be altered by changing the amount of charge present between the gate and the channel, corresponding to the two states of the memory cell, i.e., the binary values (“1” and “0”) of the stored bit. Figure 2-1 shows the threshold voltage shift between two states in a Flash memory. To a nonvolatile memory, it can be “written” into either state “1” or “0” by either “programming” or “erasing” methods, which are decided by the definition of memory cell itself. There are many solutions to achieve “programming” or “erasing”.

between bias and energy band bending. Tunneling injection, channel hot electron injection, and band to band assisted electron/hole injection will be discussed briefly. The reliability of nonvolatile memory and physical characteristic of nanocrystal NVM will be also discussed.

2.2 Basic Program and Erase Mechanisms

2.2.1 Energy band diagram during program and erase operation

Fig. 2-2 illustrates the program/erase physical operation of a SONOS memory device. In the write operation, a positive voltage is applied on gate electrode relative to the p-type substrate, which forms an electron channel. Then the electrons tunnel through the tunnel oxide into the silicon nitride film and can be stored in deep-level traps. Some electrons which are not trapped in the nitride film will tunnel through a blocking oxide into the gate electrode. The trapped electrons provide the electrostatic screening of the channel from the control gate, and result in a threshold voltage (VT) shift. During the

erase operation under a negative voltage bias on the gate electrode, the holes tunnel from the substrate into the silicon nitride and are partially trapped in a manner similar to electrons. And some holes “pile-up” at the blocking oxide interface because of the larger barrier height (5eV). Further, trapped electrons may be de-trapped into the nitride conduction band and then tunnel back to the channel. Thus, for SONOS memory device operation both carrier types are involved in the transport process.

The write and erase processes for an n-channel semiconductor nanocrystal memory device are illustrated schematically in Fig. 2-3. During the write process, a positive gate voltage is applied to inject channel inversion-layer electrons into the nanocrystals. During

Tunneling is a quantum mechanical process akin to throwing as ball against a wall often enough that the ball goes through the wall without damaging the wall or the ball. It also loses no energy during the tunnel event. The tunneling probability, depending on electron barrier height (φ(x) ), tunnel dielectric thickness (d), and effective mass (me)

inside the tunnel dielectric, is express as [2-4]

Basically, tunneling injection must to have available states on the other side of the barrier for the carriers to tunnel into. Tunneling through the oxide can be attributed to different carrier-injection mechanisms. Which process applies depends on the oxide thickness and the applied gate field or voltage. Direct tunneling (DT), Fowler-Nordheim tunneling (FN), modified Fowler-Nordheim tunneling (MFN) and trap assistant tunneling (TAT) are the main programming mechanisms employed in memory [2.5-2.7] as shown in Figure 2-4.

Direct Tunneling

Direct Tunneling is the flow of electrons through the full oxide thickness illustrated in Figure 2-4(a). For nanocrystal memories, the control-gate coupling ratio of nanocrystal memory devices is inherently small [2.8]. As a result, F-N tunneling cannot serve as an efficient write/erase mechanism when a relatively thick tunnel oxide is used, because the strong electric field cannot be confined in one oxide layer. The direct tunneling is employed in nanocrystal memories instead. In the direct-tunneling regime, a thin oxide with thickness less than 3 nm is used to separate the nanocrystals from the channel. During program/erase operations, electrons/holes can pass through the oxide by direct tunneling, which gives the advantages of fast write/erase and low operation voltage. In the other hand, the direct tunneling is more sensitive to the barrier width than barrier height, two to four orders of magnitude reduction in leakage current can still be achieved if large work function metals, such as Au or Pt [2.9].

Fowler–Nordheim Tunneling

potential barrier illustrated in Figure 2-4(b). FN tunneling mechanism occurs when applying a strong electric field (in the range of 8–10 MV/cm) across a thin oxide. In these conditions, the energy band diagram of the oxide region is very steep. Therefore, there is a high probability of electrons’ passing through the energy barrier itself. Using a free-electron gas model for the metal and the Wentzel–Kramers–Brillouin (WKB) approximation for the tunneling probability [2.10], one obtains the following expression for current density [2.11]:

       _{− Φ} Φ = ∗ qF m h F q J OX B B 3h ) 2 ( 4 exp 16 2 3 2 1 2 2 2 3 π

Where ФB is the barrier height, mOX∗ is the effective mass of the electron in the forbidden

gap of the dielectric, h is the Planck’s constant, q is the electronic charge, and F is the electrical field through the oxide. The exponential dependence of tunnel current on the oxide-electric field causes some critical problems of process control because, for example, a very small variation of oxide thickness among the cells in a memory array produces a great difference in programming or erasing currents, thus spreading the threshold voltage distribution in both logical states.

Modified Fowler–Nordheim Tunneling

Modified Fowler–Nordheim tunneling (MFN) is similar to the traditional FN tunneling mechanism, yet the carriers enter the nitride at a distance further from the tunnel oxide-nitride interface. MFN mechanism is frequently observed in SONOS memories. The SONOS memory is designed for low-voltage operation (< 10V,

injection the traps are emptied with a smaller time constant then they are filled. The charge carriers are thus injected at the same distance into the nitride as for MFN injection. Because of the sufficient injection current, trap assistant tunneling may influence in retention [2.12].

(b) Channel Hot Electron Injection (CHEI)

The physical mechanism of HEI is relatively simple to understand qualitatively. An electron traveling from the source to the drain gains energy from the lateral electric field and loses energy to the lattice vibrations (acoustic and optical phonons). At low fields, this is a dynamic equilibrium condition, which holds until the field strength reaches approximately 100 kV/cm [2.13]. For fields exceeding this value, electrons are no longer in equilibrium with the lattice, and their energy relative to the conduction band edge begins to increase. Electrons are “heated” by the high lateral electric field, and a small fraction of them have enough energy to surmount the barrier between oxide and silicon conduction band edges (channel hot electron, CHE). Figure 2-5 shows schematic representation of CHEI MOSFET and the energy-distribution function with different fields. In the other hand, the effective mass of hole is heavier than one of electron. It is too hard to obtain enough energy to surmount oxide barrier. Therefore, hot-hole injection rarely is employed in nonvolatile memory operation.

Nevertheless, a description of the injection conditions can be accomplished with two different approaches. The HEI current is often explained and simulated following the “lucky electron” model [2.14]. This model is based on the probability of an electron’s being lucky enough to travel ballistically in the field ε for a distance several times the mean free path without scattering, eventually acquiring enough energy to cross the potential barrier if a collision pushes it toward the Si/SiO2 interface. Consequently, the

probability of injection is the lumped probability of the following events [2.15], which are depicted in Figure 2-6

1) The carrier has to be “lucky” enough to acquire enough energy from the lateral electric field to overcome the oxide barrier and to retain its energy after the collision that redirects the electron toward the interface (PΦb).

(PED).

3) The carrier can surmount the repulsive oxide field at the injection point, due to the Schottky barrier lowering effect, without suffering an energy-robbing collision in the oxide (POC).

(c) Band to Band Tunneling (BTBT)

Band to band tunneling application to nonvolatile memory was first proposed in 1989. I. C. Chen and et al. demonstrated a high injection efficiency (~1%) method to programming EPROM devices [2.16].

Band to Band Hot Electron Tunneling Injection

The injection is applied for n-type substrate nonvolatile memory device. Figure 2-7 shows the energy-band diagram and device operation during the band to band tunneling induced hot electron (BBHE) injection. When band-bending is higher than the energy gap of the semiconductor, the tunneling electron from the valence band to the conduction band becomes significant. The electrons are accelerated by a lateral electric field toward the channel region and some of the electrons with sufficient energy can surmount the potential barrier of SiO2 like hot electron injection [2.16-2.18].

Band to Band Hot Hole Tunneling Injection

In p-type substrate, when a negative gate voltage and a positive drain voltage are applied to the cell, electron-hole pairs are generated by BTBT in the drain region, as shown in Figure 2-8. The holes are accelerated by a lateral electric field toward the channel region and some of them obtain high energy. The hot holes inject into charge trapping layer through the tunnel oxide and recombine the stored electrons. This injection is used for a new erase operation for nonvolatile memory device [2.19].

investigate Flash-cell reliability. In general, NVMs are required to withstand up to 10-100K program/erase cycles (endurance) with 10-year memory retention at temperatures as high as 85 °C.

2.3.1 Retention

Retention describes the ability to the NVM to store and recover information after a number of program cycles at a specified temperature. In any nonvolatile memory technology, it is essential to retain data for over ten years. This means the loss of charge stored in the storage medium must be as minimal as possible. For example, in modern Flash cells, FG capacitance is approximately 1 fF. A loss of only 1 fC can cause a 1V threshold voltage shift. If we consider the constraints on data retention in ten years, this means that a loss of less than five electrons per day can be tolerated [2.20]. Possible causes of charge loss are: 1) by tunneling or thermionic emission mechanisms; 2) defects in the tunnel oxide; and 3) detrapping of charge from insulating layers surrounding the storage medium; 4) mobile ion contamination. Further, the retention capability of Flash memories has to be checked by using accelerated tests that usually adopt screening electric fields and hostile environments at high temperature.

2.3.2 Endurance

The term “endurance” refers to the ability of the nonvolatile memory to withstand repeated program cycles and still meet the specifications in the data sheet. In a conventional Flash memory the maximum number of erase/program cycles that the device must sustain is 105.

A typical result of an endurance test on a single cell is shown in Figure 2-9. As the experiment was performed applying constant pulses, the variations of program and erase threshold voltage levels are described as “program/erase threshold voltage window closure” and give a measure of the tunnel oxide aging. In particular, the reduction of the programmed threshold with cycling is due to trap generation in the oxide and to interface state generation at the drain side of the channel, which are mechanisms specific to hot-electron degradation. The initial lowering of VT the erase is due to a pile-up of

positive charge which enhances tunneling efficiency. While the long-term increase of VT

Actually, endurance problems are mostly given by single-cell failures, which present themselves like a retention problem after program/erase cycles. In fact, a high field stress on thin oxide is known to increase the current density at low electric field. The excess current component, which causes a significant deviation from the current–voltage curves from the theoretical FN characteristics at low field, is known as stress-induced leakage current (SILC). SILC is clearly attributed to stress-induced oxide defects and, as far as a conduction mechanism, it is attributed to a trap assisted tunneling, as shown in Figure 2-10. The main parameters controlling SILC are the stress field, the amount of charge injected during the stress, and the oxide thickness. For fixed stress conditions, the leakage current increases strongly with decreasing oxide thickness [2.21-2.23]

2.4 Basic Physical Characteristic of Nanocrystal NVM

2.4.1 Quantum Confinement Effect

The quantum dot, is quasi-zero-dimensional nanoscaled material, and is composed by small amount atoms. The quantum confinement energy dependence on nanocrystal size has been studied both experimentally and theoretically with the tight-binding model [2.24]. The quantum confinement effect becomes significant when the nanocrystal size shrinks to the nanometer range, which causes the conduction band in the nanocrystal to shift to higher energy compared with bulk material [2.25]. For example, a 3nm Ge nanocrystal can have a conduction band shift of 0.5eV as compared with bulk Ge, which is significant enough to affect the electrical performance of the nanocrystal memory cell.

2.4.2 Coulomb Blockade Effect

programming voltages (< 3V). In a flash memory array, device cells often encounter disturbances with low gate voltage soft-programming. The Coulomb blockade effect can effectively inhibit the electron tunneling at low gate voltage and improve the flash memory array immunity to disturbance. However, the Coulomb blockade effect should be reduced by employing large nanocrystal if large tunneling current and fast programming speed were desired. The Coulomb blockade effect has a detrimental effect on the retention time, since the electrons in the nanocrystal have large tendency to tunnel back into the channel if the nanocrystal potential energy is high in retention mode. In the energy band diagram, the Coulomb blockade charging energy only raises the electrostatic potential of the nanocrystal; the quantum confinement energy shifts the nanocrystal conduction band edge upward so that the conduction band offset between the nanocrystal and the surrounding oxide is reduced.

Figure 2-1 I–V curves of the floating-gate device when there is no charge

stored in the floating-gate (curve A) and when a negative charge Q is stored

in the floating-gate (curve B).

Figure 2-2 Energy band diagrams of the SONOS memory device under (a)

program (b) erase operation.● electrons, ○ holes.

Figure 2-3 (a) Schematic cross-section of nanocrystal memory device

structure; (b) illustration of write process: inversion-layer electrons tunnel

(a) (b)

DT occur when OT OT OT X E X 2 1 1

φ

φ

φ

− > > FN occur when OT OT X E > φ1

(c) (d)

MFN occur when TAT occur when

N N OX OT OT OT _{X X} E X _      + − > > − ε ε φ φ φ φ_{1 2 1 2}

N N OX OT OT OT _{X X} E X       + > > ε ε φ φ_{3 3} t φ φ φ φ₃ = ₁− ₂−

Figure 2-4 Fourth approaches to programming methods (a) Direct tunneling

(DT) (b) Fowler-Nordheim (FN) tunneling (c) Modified Fowler-Nordheim

(MFN) tunneling (d) Trap assistant tunneling (TAT).

Figure 2-6 A schematic of energy band diagram describing the process

involved in electron injection.

N-Sub

P

+

FG

P

+

V

_G

< 0

V

D

> 0

Figure 2-8 Band to band induce hot hole injection mechanism and schematic

illustration cross of the Flash memory with p-channel cell.

Figure 2-9 A typical result of an endurance test on a single cell.

Threshold voltage window closure as a function of program / erase cycles.

Figure 2-10 Anomalous SILC modeling. The leakage is caused by a

cluster of positive charge generated in the oxide during erase. The

multitrap assisted tunneling is used to model SILC: trap parameters

are energy and position.

Chapter 3

Formation and Nonvolatile Memory Effect of Mo Nanocrystal

embedded in SiO

2

3.1 Motivation

A floating gate (FG) device composed of nonvolatile memory (NVM) is widely applicable to portable productions. The device is made up of the metal-oxide-semiconductor field-effect transistor (MOSFET) embedded with a continuous conductive poly-Si layer in the gate oxide for charge storage [3.1]. To enable high-speed and lowpower consumption operations of the device, the oxide layer has to be scaled down, especially the oxide layer between the FG and Si substrate (tunnel oxide). However, the long retention time demands a thick tunnel oxide to prevent the stored charges from leaking out of the FG [3.2]. One way to satisfy the conflicting requirements on tunnel oxide is to employ the distributed nanocrystals as the discrete charge trapping centers [3.3]. Recently, much attention has been directed toward metallic NC for their several advantages, such as a stronger coupling with the conduction channel and a wide range of available work functions [3.4]. Metal has been studied for the fabrication of NC memory for their extensive applications on the semiconductor fabrication process [3.5-3.8]. Furthermore, a conventional MOSFET required a high-temperature process for

dopant activation (>900°C) [3.9]. Therefore, the thermal stability of NC should also be considered. Mo has been proposed for the metal gate, and is compatible with the

oxidation Mo and Si layer

3.2.1 Experimental Procedures

Figure 3-1 exhibit schemas of the experimental procedures. The nonvolatile memory-cell structure in this letter was fabricated on a 6 in. p-type silicon (100) wafer. After a standard RCA process which removed native oxide and micro-particles, 5-nm-thick tunnel oxide was thermally grown by a dry oxidation process in an atmospheric pressure chemical vapor deposition furnace (APCVD). Subsequently, a 10-nm-thick charge tapping layer was deposited by co-evaporating of Mo and Si pellets at room temperature. A 30-nm-thick blocking oxide was deposited by a plasma enhanced chemical vapor deposition (PECVD) system at 300oC. Afterward, rapid thermal oxidation process was performed to form the NC. Al gate electrodes on back and front side of the sample were finally deposited and patterned to form a metal/oxide/insulator/oxide/silicon (MOIOS) structure.

Electrical characteristics, including the capacitance-voltage (C-V), retention characteristics, were also performed. The C-V characteristics were measured by Keithley 4200 and HP4284 Precision LCR Meter with high frequency 1 MHz. In addition, Transmission electron microscope (TEM) and X-ray photoelectron spectroscopy (XPS) were adopted for the micro-structure analysis and chemical material analysis.

3.2.2 Results and Discussion

Figure 3-2 show cross-sectional TEM image of trapping layer. The average diameter of NC is about 20 nm and the density is about 5.9 × 1011 cm-2. In addition, the tunnel oxide seems to be damaged.

To investigate the chemical composition after thermal annealing, the The XPS analysis was performed by using an Al Kα (1486.6 eV) x-ray radiation. Figure 3-3 shows

the Mo 3d XPS spectra. The Mo and Mo oxide signals were found after thermal oxidation.

The result indicates that the Mo was over-oxidized. It is know that the melting point of Mo oxide is about 850 oC. Therefore, the Mo oxide may be reaction with and degrade the tunnel oxide during the oxidation process at 900 oC.

The capacitance-voltage (C-V) hysteresis is shown in Figure 3-4. After annealing, it is clearly observed memory windows, which have 5 V in temperature 900oC O2 for

operating under flat band voltage(VFB) ±10 V gate voltage, as shown in Fig. 3-3(b) and

Fig 3-3(c). Moreover, the hysteresis loops follow the counterclockwise due to injection of electrons from the deep inversion layer and discharge of electrons from the deep accumulation layer of Si substrate [3.11]. Hence, the memory window is larger enough to define “1” and “0” states using this nanocrystal memory structure.

Figure 3-5 demonstrates the data retention characteristics of the nonvolatile molybdenum nanocrystal memory at room temperature. The memory cell is programmed by 4 V, 5 s, gate pulses for Data “1” and “0”, respectively. The flat band voltage shift is obtained by comparing the C-V curves from a charged state and the quasi-neutral state.

The memory window was significantly decay (-193 mV/dec) after 1000s due to charge emission from defects of molybdenum oxide damaged tunneling oxide. It does not any memory window from the elongation line of the decay trend can obtain even after 10 years.

3.3 Nonvolatile Mo Nanocrystal Memory by thermal annealing

Mo and SiO

2

layer

3.3.1 Experimental Procedures

Figure 3-6 exhibit schema of the experimental procedures. This nonvolatile memory-cell structure in this letter was fabricated on a 4 in. p-type silicon (100) wafer. After a standard RCA process which removed native oxide and micro-particles,

foregoing process, the Molybdenum nanocrystals could be found to precipitate and embedded in SiOx layer. Al gate electrodes on back and front side of the sample were

finally deposited and patterned by shadow mask to form a metal/oxide/insulator/oxide/silicon (MOIOS) structure. A control sample that went through the same processing steps except for the trapping layer different by evaporating pure Si and annealing in 900 oC O2) was fabricated for comparison

Electrical characteristics, including the capacitance-voltage (C-V), retention characteristics, were also performed. The C-V characteristics were measured by Keithley 4200 and HP4284 Precision LCR Meter with high frequency 1 MHz. In addition, Transmission electron microscope (TEM) and X-ray photoelectron spectroscopy (XPS) were adopted for the micro-structure analysis and chemical material analysis.

3.3.2 Results and Discussion

Figure 3-7 show cross-sectional TEM image of trapping layer which is molybdenum nanocrystals in temperature 900 oC. The average diameter of NC is about 6 nm and the density is about 8 × 1011 cm-2

The capacitance-voltage (C-V) hysteresis is shown in Figure 3-8. In Figure 3-8(a), the sample of as-depostion has not any memory window or charge storage ability for this MOIOS structure. After annealing , it is clearly observed memory windows, which have 2.9 V in 700 oC N2 30 min and 2 V in temperature 900 oC N2 30 min for operating under

flat band voltage(VFB) ±10 V gate voltage , as shown in Fig. 3-8(b) and Fig 3-8(c).

Moreover, the hysteresis loops follow the counterclockwise due to injection of electrons from the deep inversion layer and discharge of electrons from the deep accumulation layer of Si substrate [3.22]. Hence, we can be enough to define “1” and “0” states using this nanocrystal memory structure. As a result, our electrical characteristics of C-V show that nonvolatile memory effect is influenced by annealing temperature.

The XPS analysis by using an Al Kα (1486.6 eV) x-ray radiation is demonstrated the

chemical composition of the charge trapping layer, as shown in Figure 3-3. From the Si 2p core-level spectrum, we can see that the Si-O bounding is about 103.3 eV for the sample with annealing 900 oC. Therefore, we consider that the silicon oxide was deficient in as-depostion. The incomplete bounding cause defects in trapping layer. After

annealing, those incomplete bounding could be repaire.

The reliability issues, such as retention and endurance, were also tested in this work. Figure 3-5 demonstrates the data retention characteristics of the nonvolatile molybdenum nanocrystal memory at room temperature. The memory cell is programmed by 9 V, 5 s, gate pulses for Data “1” and “0”, respectively. The flat band voltage shift is obtained by comparing the C-V curves from a charged state and the quasi-neutral state. The memory

window which anneal in 700 oC N2 30 min significantly decays during the first 600 s and

a decay rate -61.73 mV/dec after 1000s due to charge emission from the shallow traps in SiOx (partial oxidized a-Si) matrix. It does not any memory window from the elongation

line of the decay trend after 10 years. In contrast, the 900 oC annealed sample has better retention characteristic which have a small decay rate -37.1 mV/dec. We speculate that the better retention of the 900 oC sample are due to less deficiency of the surrounding oxide, deficiency of which can cause lateral leak.

3.4 Comparison of Electrical Characteristics between Mo

nanocrystal by oxidizing Mo-Si and annealing Mo-SiO

2

The comparisons of memory window, nanocrystal density and retention characteristics between the two type process flows for nonvolatile memory devices of molybdenum nanocrastal are listed in Table 3-1. The estimated density of Mo nanocrystal which manufacture by oxidizing co-evaporated Mo and Si (Mo-Si) layer by TEM analysis is close to that manufacture by annealing co-evaporated Mo and SiO2 (Mo-SiO2)

layer. Compared with Mo nanocrystal formation by oxidizing Mo-Si layer, the Mo nanocrystal fabricated by annealing Mo-SiO2 layer exhibits the lager memory window

3.5 Summary I

The nonvolatile memory structure of Mo nanocrystals embedded in the SiOx layer

was fabricated by annealing Mo-SiO2 layer at room temperature. The fabrication method

can avoid the over-oxidation phenomenon. The high density (~1011 cm-2) and good uniformity nanocrystals can be fabricated through this simple process. The memory window of molybdenum nanocrystals (>2 V) is large enough to define “1” and “0” for the nonvolatile memory application. The retention characteristic are good enough to be maintained after 10 years. In addition, this novel and ease fabrication technique of Mo nanocrystals can be compatible with current manufacture process of the integrated circuit manufacture.

Figure 3-3 Capacitance-voltage (C-V) hysteresis of the fabricated MOIOS structure with Mo nanocrystals embedded in SiOx

Figure 3-4 The XPS analysis of Mo 3d spectra for Mo nanocrystals embedded in SiOx. After the thermal process, the peak signal of MoO2 and MoO3 can be observed,

Figure 3-5 Retention characteristics of the Mo nanocrystal memory after annealing 900oC in O2

Figure 3-7 Cross-sectional TEM images of the MOIOS structure with co-evaporating Mo and SiOx and annealing in 900

o C O2. VG (V) -8 -6 -4 -2 0 C /Co x 0.0 0.2 0.4 0.6 0.8 1.0 6 <=> -14 Mo+SiO2 10 nm SiO25nm Si Mo+SiO2 10 nm SiO25nm Si Memory window ~0V under V_FB±10V operation VG (V) -6 -4 -2 0 2 C /Co x 0.0 0.2 0.4 0.6 0.8 1.0 3 <=> -7 8 <=> -12 VG (V) -6 -4 -2 0 2 C /C o x 0.2 0.4 0.6 0.8 1.0 3 <=> -7 8 <=> -12 Mo+SiO2 10nm SiO25nm Si Mo+SiO2 10nm SiO25nm Si Mo+SiO2 10nm SiO25nm Si Mo+SiO2 10nm SiO25nm Si Memory window ~2V under VFB±10V operation Memory window Memory window ~2.9V under VFB±10V operation

Annealing N2700 ℃ 30min Annealing N2900 ℃ 30min

a.

b. c.

Figure 3-8 Capacitance-voltage (C-V) hysteresis of the fabricated MOIOS structure with Mo nanocrystals embedded in SiOx. (a) The sample of as-depostion (b) After

Figure 3-9 The XPS analysis of Mo 3d and Si 2d spectra for Mo nanocrystals embedded in SiOx. After the thermal process, the peak signal of SiOx can be

Table 3-1 Comparisons of memory window, nanocrystal density and retention characteristics between two type nonvolatile memory devices.

Nonvolatile

Memory

Memory window under ±10V Nanocrystals density Memory window after 10 years Decay rate (mV/dec) Mo-Si 5 V 5.9 x 1011 cm-2 0% -193 Mo-SiO2 2 V 8 x1011 cm-2 41.3% -37.1

Chapter 4

Formation and Nonvolatile Memory Effect of Mo Nanocrystal

embedded in SiN

x

4.1 Motivation

Introduction

As we mentioned at the first chapter in the thesis, poly-si/oxide/nitride/oxide/silicon (SONOS) nonvolatile memory devices have been widely used in the integrated circuit market. The charge storage elements in SONOS memory are the charge traps distributed throughout the volume of the silicon nitride (Si3N4) layer. A typical trap has a density of

the order 1018-1019 cm-3according to Yang et al [4.1] and stores both electrons and holes (positive charge) injected from channel.

Base on the high trap density of silicon nitride, some study were reported to fabricate germanium nanocrystal embedded in SiNx dielectric [4.2]. The nitride can

increase trapping states to improve memory window under electrical operation. Comparing to SONOS and Ge nanocrystals NVMs, a larger memory window can be obtained. When a memory device has a large memory window, retention is easier to maintain the requirement of 10 years.

In this chapter, we propose molybdenum nanocrystals embedded in SiNx dielectric

as the charge trapping layer for nonvolatile memory application. .